ARM: SoC fixes for 3.18-rc4
Another quiet week:
- A fix to silence edma probe error on non-supported platforms from Arnd
- A fix to enable the PL clock for Parallella, to make mainline usable with
the SDK.
- A somewhat verbose fix for the PLL clock tree on VF610
- Enabling of SD/MMC on one of the VF610-based boards (for testing)
- A fix for i.MX where CONFIG_SPI used to be implicitly enabled and now needs
to be added to the defconfig instead
- Another maintainer added for bcm2835: Lee Jones
ARM: dts: zynq: Enable PL clocks for Parallella
The Parallella board comes with a U-Boot bootloader that loads one of
two predefined FPGA bitstreams before booting the kernel. Both define an
AXI interface to the on-board Epiphany processor.
Enable clocks FCLK0..FCLK3 for the Programmable Logic by default.
Otherwise accessing, e.g., the ESYSRESET register freezes the board,
as seen with the Epiphany SDK tools e-reset and e-hw-rev, using /dev/mem.
Cc: <stable@vger.kernel.org> # 3.17.x
Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
1 file changed
