| commit | c1d676cec572544616273d5853cb7cc38fbaa62b | [log] [tgz] |
|---|---|---|
| author | Thierry Reding <treding@nvidia.com> | Thu Mar 26 17:53:01 2015 +0100 |
| committer | Thierry Reding <treding@nvidia.com> | Fri Apr 10 16:04:22 2015 +0200 |
| tree | 009f67bdeb71c6ea86a503265690f2729b043239 | |
| parent | a84724a1c3cccd03b4ca1c8aea135095d0a6204e [diff] |
clk: tegra: Use the proper parent for plld_dsi
The current parent, plld_out0, does not exist. The proper name is
pll_d_out0. While at it, rename the plld_dsi clock to pll_d_dsi_out to
be more consistent with other clock names.
Fixes: b270491eb9a0 ("clk: tegra: Define PLLD_DSI and remove dsia(b)_mux")
Signed-off-by: Thierry Reding <treding@nvidia.com>