tag 789552319507544c822c731d32794ff3b47b2ddb
tagger Abel Vesa <abel.vesa@linaro.org> Mon Sep 19 13:15:41 2022 +0300
object 67e16ac1fec475e64dcb8238f471c6fd154ef806

i.MX clocks changes for 6.1

- Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
  clocks for i.MX8MP
- Drop unnecessary newline in i.MX8MM dt-bindings
- Add more MU1 and SAI clocks dt-bindings Ids
- Introduce slice busy bit check for i.MX93 composite clock
- Introduce white list bit check for i.MX93 composite clock
- Add new i.MX93 clock gate
- Add MU1 and MU2 clocks to i.MX93 clock provider
- Add SAI IPG clocks to i.MX93 clock provider

commit 67e16ac1fec475e64dcb8238f471c6fd154ef806
author Peng Fan <peng.fan@nxp.com> Tue Aug 30 11:31:37 2022 +0800
committer Abel Vesa <abel.vesa@linaro.org> Mon Sep 19 13:06:45 2022 +0300
tree cd896277c054990707aee5ec4a5755bfa5c98903
parent 92d1496fe8644f6612b7adff7581a31002dc8dd0

clk: imx93: add SAI IPG clk

The clk topology is as below:
bus_aon_root------>\                  /--->SAI IPG
                    -->SAI LPCG gate-->
sai[x]_clk_root--->/                  \--->SAI MCLK

So use shared count as i.MX93 MU_B gate.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-9-peng.fan@oss.nxp.com