i.MX clocks changes for 6.4

- Add clock generic devm_clk_hw_register_gate_parent_data.
- Add audiomix block control for i.MX8MP.
- Add support for determine_rate to composite-8m.
- Add new macro for composite-8m to allow custom flags.
- Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate.
- Provide clock name in error message for clk-gpr-mux on get parent
- Drop duplicate imx_clk_mux_flags macro.
- Register the i.MX8MP Media Disp2 Pix clock as bus clock.
- Add Media LDB root clock to i.MX8MP.
- Make i.MX8MP nand_usdhc_bus clock as non-critical.
- Fix the rate table for fracn-gppll.
- Disable HW control for the fracn-gppll in order to be controlled by
  register write.
- Add support for interger PLL in fracn-gppll.
- Add mcore_booted module parameter to i.MX93 provider.
- Add NIC, A55 and ARM PLL clocks to i.MX93.
- Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents.
- Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to
  get more accurate clock rates.
- Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical.
- Update some of the critical clocks flags to allow glitchless
  on-the-fly rate change.
clk: imx: imx8ulp: update clk flag for system critical clock

In order to support bus fabric clock frequency changed on the fly,
need to update some bus clocks'flags to make sure these clocks'frequency
and parent can be changed on the fly. For these clocks, HW can make sure
no glitch will be introduced when changing on the fly.

In order to support DDR DFS, the HW register bit for DDR_SEL
and DDR_DIV clock will be modified by TF-A. So need to update
these two clock's flag to make sure that the linux kernel side
can correct these clocks' SW state to reflect the actual HW state.

Reviewed-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20230331063814.2462059-6-peng.fan@oss.nxp.com
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
1 file changed