// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for the V3H Starter Kit board
 *
 * Copyright (C) 2018 Renesas Electronics Corp.
 * Copyright (C) 2018 Cogent Embedded, Inc.
 */

/dts-v1/;
#include "r8a77980.dtsi"

/ {
	model = "Renesas V3H Starter Kit board";
	compatible = "renesas,v3hsk", "renesas,r8a77980";

	aliases {
		serial0 = &scif0;
		ethernet0 = &gether;
	};

	chosen {
		stdout-path = "serial0:115200n8";
	};

	memory@48000000 {
		device_type = "memory";
		/* first 128MB is reserved for secure area. */
		reg = <0 0x48000000 0 0x78000000>;
	};
};

&extal_clk {
	clock-frequency = <16666666>;
};

&extalr_clk {
	clock-frequency = <32768>;
};

&gether {
	pinctrl-0 = <&gether_pins>;
	pinctrl-names = "default";

	phy-mode = "rgmii";
	phy-handle = <&phy0>;
	renesas,no-ether-link;
	status = "okay";

	phy0: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio4>;
		interrupts = <23 IRQ_TYPE_LEVEL_LOW>;
	};
};

&pfc {
	gether_pins: gether {
		groups = "gether_mdio_a", "gether_rgmii",
			 "gether_txcrefclk", "gether_txcrefclk_mega";
		function = "gether";
	};

	scif0_pins: scif0 {
		groups = "scif0_data";
		function = "scif0";
	};

	scif_clk_pins: scif_clk {
		groups = "scif_clk_b";
		function = "scif_clk";
	};
};

&scif0 {
	pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
	pinctrl-names = "default";

	status = "okay";
};

&scif_clk {
	clock-frequency = <14745600>;
};