)]}'
{
  "commit": "d47aff08ce2c783b5e8afa249e12fec24b342c39",
  "tree": "8f755a57d742bbdf04fd67940901b4105b976975",
  "parents": [
    "9e6aca1fe84d4f7bbfe580a6e6f03a235bd24908"
  ],
  "author": {
    "name": "Ard Biesheuvel",
    "email": "ard.biesheuvel@linaro.org",
    "time": "Tue Jul 25 11:58:35 2017 +0100"
  },
  "committer": {
    "name": "Ard Biesheuvel",
    "email": "ard.biesheuvel@linaro.org",
    "time": "Sun Sep 03 11:28:45 2017 +0100"
  },
  "message": "arm64: kernel: implement fast refcount checking\n\nThis adds support to arm64 for fast refcount checking, as proposed by\nKees for x86 based on the implementation by grsecurity/PaX.\n\nThe general approach is identical: the existing atomic_t helpers are\ncloned for refcount_t, with the arithmetic instruction modified to set\nthe PSTATE flags, and one or two branch instructions added that jump to\nan out of line handler if overflow, decrement to zero or increment from\nzero are detected.\n\nOne complication that we have to deal with on arm64 is the fact that\nit has two atomics implementations: the original LL/SC implementation\nusing load/store exclusive loops, and the newer LSE one that does mostly\nthe same in a single instruction. So we need to clone some parts of\nboth for the refcount handlers, but we also need to deal with the way\nLSE builds fall back to LL/SC at runtime if the hardware does not\nsupport it.\n\nAs is the case with the x86 version, the performance delta is in the\nnoise (Cortex-A57 @ 2 GHz, using LL/SC not LSE), even though the arm64\nimplementation incorporates an add-from-zero check as well:\n\nperf stat -B -- echo ATOMIC_TIMING \u003e/sys/kernel/debug/provoke-crash/DIRECT\n\n Performance counter stats for \u0027cat /dev/fd/63\u0027:\n\n      65716.592696      task-clock (msec)         #    1.000 CPUs utilized\n                 2      context-switches          #    0.000 K/sec\n                 0      cpu-migrations            #    0.000 K/sec\n                46      page-faults               #    0.001 K/sec\n      131341846242      cycles                    #    1.999 GHz\n       36712622640      instructions              #    0.28  insn per cycle\n   \u003cnot supported\u003e      branches\n            792754      branch-misses\n\n      65.736371584 seconds time elapsed\n\nperf stat -B -- echo REFCOUNT_TIMING \u003e/sys/kernel/debug/provoke-crash/DIRECT\n\n      65615.259736      task-clock (msec)         #    1.000 CPUs utilized\n                 2      context-switches          #    0.000 K/sec\n                 0      cpu-migrations            #    0.000 K/sec\n                45      page-faults               #    0.001 K/sec\n      131138621533      cycles                    #    1.999 GHz\n       43155978260      instructions              #    0.33  insn per cycle\n   \u003cnot supported\u003e      branches\n            779668      branch-misses\n\n      65.616216112 seconds time elapsed\n\nFor comparison, the numbers below were captured using CONFIG_REFCOUNT_FULL,\nwhich uses the validation routines implemented in C:\n\nperf stat -B -- echo REFCOUNT_TIMING \u003e/sys/kernel/debug/provoke-crash/DIRECT\n\n Performance counter stats for \u0027cat /dev/fd/63\u0027:\n\n     104566.154096      task-clock (msec)         #    1.000 CPUs utilized\n                 2      context-switches          #    0.000 K/sec\n                 0      cpu-migrations            #    0.000 K/sec\n                46      page-faults               #    0.000 K/sec\n      208929924555      cycles                    #    1.998 GHz\n      131354624418      instructions              #    0.63  insn per cycle\n   \u003cnot supported\u003e      branches\n           1604302      branch-misses\n\n     104.586265040 seconds time elapsed\n\nSigned-off-by: Ard Biesheuvel \u003card.biesheuvel@linaro.org\u003e\n",
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