)]}'
{
  "commit": "b03c9fa1f2d03aeece38f4b8ea8c05edb0e156b2",
  "tree": "65c9d3927b19c499491eace97aa1d1da960eacfa",
  "parents": [
    "65a6575de6d32d221edf90dd2a21fc3a04bb1e85"
  ],
  "author": {
    "name": "Ard Biesheuvel",
    "email": "ardb@kernel.org",
    "time": "Wed Oct 30 08:54:56 2024 +0100"
  },
  "committer": {
    "name": "Ard Biesheuvel",
    "email": "ardb@kernel.org",
    "time": "Sat Nov 09 16:29:01 2024 +0100"
  },
  "message": "arm64/mm: Account for reduced VA sizes in T0SZ and skip the levels\n\nNow that a smaller value for TASK_SIZE is used when running with a\nreduced virtual address space for userland, it is guaranteed that only\nthe first entry of each root level page table is populated. This means\nthat we can reduce the number of levels of translation performed by the\nMMU by programming this entry into TTBR0_EL1 directly, and updating T0SZ\naccordingly.\n\nThis is a quick and dirty hack, but should reap all the benefits in\nterms of MMU performance and reduced TLB pressure, at the cost of one\nwasted page per process (or 2 on 52-bit VA capable hardware).\n\nSigned-off-by: Ard Biesheuvel \u003cardb@kernel.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "48b3d9553b675c3c0b8bbe1b0030ed089afd3990",
      "old_mode": 33188,
      "old_path": "arch/arm64/include/asm/mmu_context.h",
      "new_id": "7536c1989c16fd47d548a9c96679c489a8d52e24",
      "new_mode": 33188,
      "new_path": "arch/arm64/include/asm/mmu_context.h"
    }
  ]
}