| /* |
| * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| /dts-v1/; |
| |
| #include "omap36xx.dtsi" |
| #include "omap3-evm-common.dtsi" |
| |
| |
| / { |
| model = "TI OMAP37XX EVM (TMDSEVM3730)"; |
| compatible = "ti,omap3-evm-37xx", "ti,omap3630", "ti,omap3"; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| reg = <0x80000000 0x10000000>; /* 256 MB */ |
| }; |
| |
| wl12xx_vmmc: wl12xx_vmmc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&wl12xx_gpio>; |
| }; |
| }; |
| |
| &dss { |
| pinctrl-names = "default"; |
| pinctrl-0 = < |
| &dss_dpi_pins1 |
| &dss_dpi_pins2 |
| >; |
| }; |
| |
| &omap3_pmx_core { |
| dss_dpi_pins1: pinmux_dss_dpi_pins2 { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x20d4, PIN_OUTPUT | MUX_MODE0) /* dss_pclk.dss_pclk */ |
| OMAP3_CORE1_IOPAD(0x20d6, PIN_OUTPUT | MUX_MODE0) /* dss_hsync.dss_hsync */ |
| OMAP3_CORE1_IOPAD(0x20d8, PIN_OUTPUT | MUX_MODE0) /* dss_vsync.dss_vsync */ |
| OMAP3_CORE1_IOPAD(0x20da, PIN_OUTPUT | MUX_MODE0) /* dss_acbias.dss_acbias */ |
| |
| OMAP3_CORE1_IOPAD(0x20e8, PIN_OUTPUT | MUX_MODE0) /* dss_data6.dss_data6 */ |
| OMAP3_CORE1_IOPAD(0x20ea, PIN_OUTPUT | MUX_MODE0) /* dss_data7.dss_data7 */ |
| OMAP3_CORE1_IOPAD(0x20ec, PIN_OUTPUT | MUX_MODE0) /* dss_data8.dss_data8 */ |
| OMAP3_CORE1_IOPAD(0x20ee, PIN_OUTPUT | MUX_MODE0) /* dss_data9.dss_data9 */ |
| OMAP3_CORE1_IOPAD(0x20f0, PIN_OUTPUT | MUX_MODE0) /* dss_data10.dss_data10 */ |
| OMAP3_CORE1_IOPAD(0x20f2, PIN_OUTPUT | MUX_MODE0) /* dss_data11.dss_data11 */ |
| OMAP3_CORE1_IOPAD(0x20f4, PIN_OUTPUT | MUX_MODE0) /* dss_data12.dss_data12 */ |
| OMAP3_CORE1_IOPAD(0x20f6, PIN_OUTPUT | MUX_MODE0) /* dss_data13.dss_data13 */ |
| OMAP3_CORE1_IOPAD(0x20f8, PIN_OUTPUT | MUX_MODE0) /* dss_data14.dss_data14 */ |
| OMAP3_CORE1_IOPAD(0x20fa, PIN_OUTPUT | MUX_MODE0) /* dss_data15.dss_data15 */ |
| OMAP3_CORE1_IOPAD(0x20fc, PIN_OUTPUT | MUX_MODE0) /* dss_data16.dss_data16 */ |
| OMAP3_CORE1_IOPAD(0x20fe, PIN_OUTPUT | MUX_MODE0) /* dss_data17.dss_data17 */ |
| |
| OMAP3_CORE1_IOPAD(0x2100, PIN_OUTPUT | MUX_MODE3) /* dss_data18.dss_data0 */ |
| OMAP3_CORE1_IOPAD(0x2102, PIN_OUTPUT | MUX_MODE3) /* dss_data19.dss_data1 */ |
| OMAP3_CORE1_IOPAD(0x2104, PIN_OUTPUT | MUX_MODE3) /* dss_data20.dss_data2 */ |
| OMAP3_CORE1_IOPAD(0x2106, PIN_OUTPUT | MUX_MODE3) /* dss_data21.dss_data3 */ |
| OMAP3_CORE1_IOPAD(0x2108, PIN_OUTPUT | MUX_MODE3) /* dss_data22.dss_data4 */ |
| OMAP3_CORE1_IOPAD(0x210a, PIN_OUTPUT | MUX_MODE3) /* dss_data23.dss_data5 */ |
| >; |
| }; |
| |
| mmc1_pins: pinmux_mmc1_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x2144, PIN_OUTPUT_PULLUP | MUX_MODE0) /* sdmmc1_clk.sdmmc1_clk */ |
| OMAP3_CORE1_IOPAD(0x2146, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_cmd.sdmmc1_cmd */ |
| OMAP3_CORE1_IOPAD(0x2148, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat0.sdmmc1_dat0 */ |
| OMAP3_CORE1_IOPAD(0x214a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat1.sdmmc1_dat1 */ |
| OMAP3_CORE1_IOPAD(0x214c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat2.sdmmc1_dat2 */ |
| OMAP3_CORE1_IOPAD(0x214e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat3.sdmmc1_dat3 */ |
| OMAP3_CORE1_IOPAD(0x2150, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat4.sdmmc1_dat4 */ |
| OMAP3_CORE1_IOPAD(0x2152, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat5.sdmmc1_dat5 */ |
| OMAP3_CORE1_IOPAD(0x2154, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat6.sdmmc1_dat6 */ |
| OMAP3_CORE1_IOPAD(0x2156, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc1_dat7.sdmmc1_dat7 */ |
| >; |
| }; |
| |
| /* NOTE: Clocked externally, needs INPUT also for sdmmc2_clk.sdmmc2_clk */ |
| mmc2_pins: pinmux_mmc2_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x2158, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_clk.sdmmc2_clk */ |
| OMAP3_CORE1_IOPAD(0x215a, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_cmd.sdmmc2_cmd */ |
| OMAP3_CORE1_IOPAD(0x215c, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat0.sdmmc2_dat0 */ |
| OMAP3_CORE1_IOPAD(0x215e, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat1.sdmmc2_dat1 */ |
| OMAP3_CORE1_IOPAD(0x2160, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat2.sdmmc2_dat2 */ |
| OMAP3_CORE1_IOPAD(0x2162, PIN_INPUT_PULLUP | MUX_MODE0) /* sdmmc2_dat3.sdmmc2_dat3 */ |
| >; |
| }; |
| |
| uart3_pins: pinmux_uart3_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x219e, WAKEUP_EN | PIN_INPUT | MUX_MODE0) /* uart3_rx_irrx.uart3_rx_irrx */ |
| OMAP3_CORE1_IOPAD(0x21a0, PIN_OUTPUT | MUX_MODE0) /* uart3_tx_irtx.uart3_tx_irtx */ |
| >; |
| }; |
| |
| wl12xx_gpio: pinmux_wl12xx_gpio { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x2180, PIN_OUTPUT | MUX_MODE4) /* uart1_cts.gpio_150 */ |
| OMAP3_CORE1_IOPAD(0x217e, PIN_INPUT | MUX_MODE4) /* uart1_rts.gpio_149 */ |
| >; |
| }; |
| |
| smsc911x_pins: pinmux_smsc911x_pins { |
| pinctrl-single,pins = < |
| OMAP3_CORE1_IOPAD(0x21d2, PIN_INPUT | MUX_MODE4) /* mcspi1_cs2.gpio_176 */ |
| >; |
| }; |
| }; |
| |
| &omap3_pmx_wkup { |
| dss_dpi_pins2: pinmux_dss_dpi_pins1 { |
| pinctrl-single,pins = < |
| OMAP3_WKUP_IOPAD(0x2a0a, PIN_OUTPUT | MUX_MODE3) /* sys_boot0.dss_data18 */ |
| OMAP3_WKUP_IOPAD(0x2a0c, PIN_OUTPUT | MUX_MODE3) /* sys_boot1.dss_data19 */ |
| OMAP3_WKUP_IOPAD(0x2a10, PIN_OUTPUT | MUX_MODE3) /* sys_boot3.dss_data20 */ |
| OMAP3_WKUP_IOPAD(0x2a12, PIN_OUTPUT | MUX_MODE3) /* sys_boot4.dss_data21 */ |
| OMAP3_WKUP_IOPAD(0x2a14, PIN_OUTPUT | MUX_MODE3) /* sys_boot5.dss_data22 */ |
| OMAP3_WKUP_IOPAD(0x2a16, PIN_OUTPUT | MUX_MODE3) /* sys_boot6.dss_data23 */ |
| >; |
| }; |
| }; |
| |
| &mmc1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc1_pins>; |
| }; |
| |
| &mmc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&mmc2_pins>; |
| }; |
| |
| &mmc3 { |
| status = "disabled"; |
| }; |
| |
| &uart1 { |
| interrupts-extended = <&intc 72 &omap3_pmx_core OMAP3_UART1_RX>; |
| }; |
| |
| &uart2 { |
| interrupts-extended = <&intc 73 &omap3_pmx_core OMAP3_UART2_RX>; |
| }; |
| |
| &uart3 { |
| interrupts-extended = <&intc 74 &omap3_pmx_core OMAP3_UART3_RX>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&uart3_pins>; |
| }; |
| |
| &gpmc { |
| ranges = <0 0 0x30000000 0x1000000>, /* CS0: 16MB for NAND */ |
| <5 0 0x2c000000 0x01000000>; |
| |
| nand@0,0 { |
| compatible = "ti,omap2-nand"; |
| reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ |
| interrupt-parent = <&gpmc>; |
| interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ |
| <1 IRQ_TYPE_NONE>; /* termcount */ |
| linux,mtd-name= "hynix,h8kds0un0mer-4em"; |
| nand-bus-width = <16>; |
| gpmc,device-width = <2>; |
| ti,nand-ecc-opt = "bch8"; |
| |
| gpmc,sync-clk-ps = <0>; |
| gpmc,cs-on-ns = <0>; |
| gpmc,cs-rd-off-ns = <44>; |
| gpmc,cs-wr-off-ns = <44>; |
| gpmc,adv-on-ns = <6>; |
| gpmc,adv-rd-off-ns = <34>; |
| gpmc,adv-wr-off-ns = <44>; |
| gpmc,we-off-ns = <40>; |
| gpmc,oe-off-ns = <54>; |
| gpmc,access-ns = <64>; |
| gpmc,rd-cycle-ns = <82>; |
| gpmc,wr-cycle-ns = <82>; |
| gpmc,wr-access-ns = <40>; |
| gpmc,wr-data-mux-bus-ns = <0>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| partition@0 { |
| label = "X-Loader"; |
| reg = <0 0x80000>; |
| }; |
| partition@0x80000 { |
| label = "U-Boot"; |
| reg = <0x80000 0x1c0000>; |
| }; |
| partition@0x1c0000 { |
| label = "Environment"; |
| reg = <0x240000 0x40000>; |
| }; |
| partition@0x280000 { |
| label = "Kernel"; |
| reg = <0x280000 0x500000>; |
| }; |
| partition@0x780000 { |
| label = "Filesystem"; |
| reg = <0x780000 0x1f880000>; |
| }; |
| }; |
| |
| ethernet@gpmc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&smsc911x_pins>; |
| }; |
| }; |
