| /* |
| * Based on arch/arm/mm/proc-macros.S |
| * |
| * Copyright (C) 2012 ARM Ltd. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| */ |
| |
| #include <asm/asm-offsets.h> |
| #include <asm/thread_info.h> |
| |
| /* |
| * vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm) |
| */ |
| .macro vma_vm_mm, rd, rn |
| ldr \rd, [\rn, #VMA_VM_MM] |
| .endm |
| |
| /* |
| * mmid - get context id from mm pointer (mm->context.id) |
| */ |
| .macro mmid, rd, rn |
| ldr \rd, [\rn, #MM_CONTEXT_ID] |
| .endm |
| |
| /* |
| * dcache_line_size - get the minimum D-cache line size from the CTR register. |
| */ |
| .macro dcache_line_size, reg, tmp |
| mrs \tmp, ctr_el0 // read CTR |
| ubfm \tmp, \tmp, #16, #19 // cache line size encoding |
| mov \reg, #4 // bytes per word |
| lsl \reg, \reg, \tmp // actual cache line size |
| .endm |
| |
| /* |
| * icache_line_size - get the minimum I-cache line size from the CTR register. |
| */ |
| .macro icache_line_size, reg, tmp |
| mrs \tmp, ctr_el0 // read CTR |
| and \tmp, \tmp, #0xf // cache line size encoding |
| mov \reg, #4 // bytes per word |
| lsl \reg, \reg, \tmp // actual cache line size |
| .endm |
| |
| /* |
| * tcr_set_idmap_t0sz - update TCR.T0SZ so that we can load the ID map |
| */ |
| .macro tcr_set_idmap_t0sz, valreg, tmpreg |
| #ifndef CONFIG_ARM64_VA_BITS_48 |
| ldr_l \tmpreg, idmap_t0sz |
| bfi \valreg, \tmpreg, #TCR_T0SZ_OFFSET, #TCR_TxSZ_WIDTH |
| #endif |
| .endm |
| |
| /* |
| * Macro to perform a data cache maintenance for the interval |
| * [kaddr, kaddr + size) |
| * |
| * op: operation passed to dc instruction |
| * domain: domain used in dsb instruciton |
| * kaddr: starting virtual address of the region |
| * size: size of the region |
| * Corrupts: kaddr, size, tmp1, tmp2 |
| */ |
| .macro dcache_by_line_op op, domain, kaddr, size, tmp1, tmp2 |
| dcache_line_size \tmp1, \tmp2 |
| add \size, \kaddr, \size |
| sub \tmp2, \tmp1, #1 |
| bic \kaddr, \kaddr, \tmp2 |
| 9998: dc \op, \kaddr |
| add \kaddr, \kaddr, \tmp1 |
| cmp \kaddr, \size |
| b.lo 9998b |
| dsb \domain |
| .endm |
