)]}'
{
  "commit": "2f7ae8ab6aa73daaf080d5332110357c29df9c36",
  "tree": "eab889b42cd9c2d4c92145f00b9a83e4b808f3f7",
  "parents": [
    "6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f"
  ],
  "author": {
    "name": "Conor Dooley",
    "email": "conor.dooley@microchip.com",
    "time": "Tue Feb 24 09:35:25 2026 +0000"
  },
  "committer": {
    "name": "Conor Dooley",
    "email": "conor.dooley@microchip.com",
    "time": "Mon Mar 02 17:12:45 2026 +0000"
  },
  "message": "clk: microchip: mpfs-ccc: fix out of bounds access during output registration\n\nUBSAN reported an out of bounds access during registration of the last\ntwo outputs. This out of bounds access occurs because space is only\nallocated in the hws array for two PLLs and the four output dividers\nthat each has, but the defined IDs contain two DLLS and their two\noutputs each, which are not supported by the driver. The ID order is\nPLLs -\u003e DLLs -\u003e PLL outputs -\u003e DLL outputs. Decrement the PLL output IDs\nby two while adding them to the array to avoid the problem.\n\nFixes: d39fb172760e (\"clk: microchip: add PolarFire SoC fabric clock support\")\nCC: stable@vger.kernel.org\nReviewed-by: Brian Masney \u003cbmasney@redhat.com\u003e\nSigned-off-by: Conor Dooley \u003cconor.dooley@microchip.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3a3ea2d142f8a2a39c5f5aef2e506a96039f7400",
      "old_mode": 33188,
      "old_path": "drivers/clk/microchip/clk-mpfs-ccc.c",
      "new_id": "0a76a1aaa50f7f3950057d99ddab0ae7a040dc7c",
      "new_mode": 33188,
      "new_path": "drivers/clk/microchip/clk-mpfs-ccc.c"
    }
  ]
}