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/*
* Copyright 2006-2007 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/****************************************************************************/
/*Portion I: Definitions shared between VBIOS and Driver */
/****************************************************************************/
#ifndef _ATOMBIOS_H
#define _ATOMBIOS_H
#define ATOM_VERSION_MAJOR 0x00020000
#define ATOM_VERSION_MINOR 0x00000002
#define ATOM_HEADER_VERSION (ATOM_VERSION_MAJOR | ATOM_VERSION_MINOR)
/* Endianness should be specified before inclusion,
* default to little endian
*/
#ifndef ATOM_BIG_ENDIAN
#error Endian not specified
#endif
#ifdef _H2INC
#ifndef ULONG
typedef unsigned long ULONG;
#endif
#ifndef UCHAR
typedef unsigned char UCHAR;
#endif
#ifndef USHORT
typedef unsigned short USHORT;
#endif
#endif
#define ATOM_DAC_A 0
#define ATOM_DAC_B 1
#define ATOM_EXT_DAC 2
#define ATOM_CRTC1 0
#define ATOM_CRTC2 1
#define ATOM_CRTC3 2
#define ATOM_CRTC4 3
#define ATOM_CRTC5 4
#define ATOM_CRTC6 5
#define ATOM_UNDERLAY_PIPE0 16
#define ATOM_UNDERLAY_PIPE1 17
#define ATOM_CRTC_INVALID 0xFF
#define ATOM_DIGA 0
#define ATOM_DIGB 1
#define ATOM_PPLL1 0
#define ATOM_PPLL2 1
#define ATOM_DCPLL 2
#define ATOM_PPLL0 2
#define ATOM_PPLL3 3
#define ATOM_PHY_PLL0 4
#define ATOM_PHY_PLL1 5
#define ATOM_EXT_PLL1 8
#define ATOM_GCK_DFS 8
#define ATOM_EXT_PLL2 9
#define ATOM_FCH_CLK 9
#define ATOM_EXT_CLOCK 10
#define ATOM_DP_DTO 11
#define ATOM_COMBOPHY_PLL0 20
#define ATOM_COMBOPHY_PLL1 21
#define ATOM_COMBOPHY_PLL2 22
#define ATOM_COMBOPHY_PLL3 23
#define ATOM_COMBOPHY_PLL4 24
#define ATOM_COMBOPHY_PLL5 25
#define ATOM_PPLL_INVALID 0xFF
#define ENCODER_REFCLK_SRC_P1PLL 0
#define ENCODER_REFCLK_SRC_P2PLL 1
#define ENCODER_REFCLK_SRC_DCPLL 2
#define ENCODER_REFCLK_SRC_EXTCLK 3
#define ENCODER_REFCLK_SRC_INVALID 0xFF
#define ATOM_SCALER_DISABLE 0 //For Fudo, it's bypass and auto-cengter & no replication
#define ATOM_SCALER_CENTER 1 //For Fudo, it's bypass and auto-center & auto replication
#define ATOM_SCALER_EXPANSION 2 //For Fudo, it's 2 Tap alpha blending mode
#define ATOM_SCALER_MULTI_EX 3 //For Fudo only, it's multi-tap mode only used to drive TV or CV, only used by Bios
#define ATOM_DISABLE 0
#define ATOM_ENABLE 1
#define ATOM_LCD_BLOFF (ATOM_DISABLE+2)
#define ATOM_LCD_BLON (ATOM_ENABLE+2)
#define ATOM_LCD_BL_BRIGHTNESS_CONTROL (ATOM_ENABLE+3)
#define ATOM_LCD_SELFTEST_START (ATOM_DISABLE+5)
#define ATOM_LCD_SELFTEST_STOP (ATOM_ENABLE+5)
#define ATOM_ENCODER_INIT (ATOM_DISABLE+7)
#define ATOM_INIT (ATOM_DISABLE+7)
#define ATOM_GET_STATUS (ATOM_DISABLE+8)
#define ATOM_BLANKING 1
#define ATOM_BLANKING_OFF 0
#define ATOM_CRT1 0
#define ATOM_CRT2 1
#define ATOM_TV_NTSC 1
#define ATOM_TV_NTSCJ 2
#define ATOM_TV_PAL 3
#define ATOM_TV_PALM 4
#define ATOM_TV_PALCN 5
#define ATOM_TV_PALN 6
#define ATOM_TV_PAL60 7
#define ATOM_TV_SECAM 8
#define ATOM_TV_CV 16
#define ATOM_DAC1_PS2 1
#define ATOM_DAC1_CV 2
#define ATOM_DAC1_NTSC 3
#define ATOM_DAC1_PAL 4
#define ATOM_DAC2_PS2 ATOM_DAC1_PS2
#define ATOM_DAC2_CV ATOM_DAC1_CV
#define ATOM_DAC2_NTSC ATOM_DAC1_NTSC
#define ATOM_DAC2_PAL ATOM_DAC1_PAL
#define ATOM_PM_ON 0
#define ATOM_PM_STANDBY 1
#define ATOM_PM_SUSPEND 2
#define ATOM_PM_OFF 3
// For ATOM_LVDS_INFO_V12
// Bit0:{=0:single, =1:dual},
// Bit1 {=0:666RGB, =1:888RGB},
// Bit2:3:{Grey level}
// Bit4:{=0:LDI format for RGB888, =1 FPDI format for RGB888}
#define ATOM_PANEL_MISC_DUAL 0x00000001
#define ATOM_PANEL_MISC_888RGB 0x00000002
#define ATOM_PANEL_MISC_GREY_LEVEL 0x0000000C
#define ATOM_PANEL_MISC_FPDI 0x00000010
#define ATOM_PANEL_MISC_GREY_LEVEL_SHIFT 2
#define ATOM_PANEL_MISC_SPATIAL 0x00000020
#define ATOM_PANEL_MISC_TEMPORAL 0x00000040
#define ATOM_PANEL_MISC_API_ENABLED 0x00000080
#define MEMTYPE_DDR1 "DDR1"
#define MEMTYPE_DDR2 "DDR2"
#define MEMTYPE_DDR3 "DDR3"
#define MEMTYPE_DDR4 "DDR4"
#define ASIC_BUS_TYPE_PCI "PCI"
#define ASIC_BUS_TYPE_AGP "AGP"
#define ASIC_BUS_TYPE_PCIE "PCI_EXPRESS"
//Maximum size of that FireGL flag string
#define ATOM_FIREGL_FLAG_STRING "FGL" //Flag used to enable FireGL Support
#define ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING 3 //sizeof( ATOM_FIREGL_FLAG_STRING )
#define ATOM_FAKE_DESKTOP_STRING "DSK" //Flag used to enable mobile ASIC on Desktop
#define ATOM_MAX_SIZE_OF_FAKE_DESKTOP_STRING ATOM_MAX_SIZE_OF_FIREGL_FLAG_STRING
#define ATOM_M54T_FLAG_STRING "M54T" //Flag used to enable M54T Support
#define ATOM_MAX_SIZE_OF_M54T_FLAG_STRING 4 //sizeof( ATOM_M54T_FLAG_STRING )
#define HW_ASSISTED_I2C_STATUS_FAILURE 2
#define HW_ASSISTED_I2C_STATUS_SUCCESS 1
#pragma pack(1) // BIOS data must use byte aligment
// Define offset to location of ROM header.
#define OFFSET_TO_POINTER_TO_ATOM_ROM_HEADER 0x00000048L
#define OFFSET_TO_ATOM_ROM_IMAGE_SIZE 0x00000002L
#define OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE 0x94
#define MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE 20 //including the terminator 0x0!
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_NUMBER 0x002f
#define OFFSET_TO_GET_ATOMBIOS_STRINGS_START 0x006e
/****************************************************************************/
// Common header for all tables (Data table, Command table).
// Every table pointed _ATOM_MASTER_DATA_TABLE has this common header.
// And the pointer actually points to this header.
/****************************************************************************/
typedef struct _ATOM_COMMON_TABLE_HEADER
{
USHORT usStructureSize;
UCHAR ucTableFormatRevision; //Change it when the Parser is not backward compatible
UCHAR ucTableContentRevision; //Change it only when the table needs to change but the firmware
//Image can't be updated, while Driver needs to carry the new table!
}ATOM_COMMON_TABLE_HEADER;
/****************************************************************************/
// Structure stores the ROM header.
/****************************************************************************/
typedef struct _ATOM_ROM_HEADER
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
//atombios should init it as "ATOM", don't change the position
USHORT usBiosRuntimeSegmentAddress;
USHORT usProtectedModeInfoOffset;
USHORT usConfigFilenameOffset;
USHORT usCRC_BlockOffset;
USHORT usBIOS_BootupMessageOffset;
USHORT usInt10Offset;
USHORT usPciBusDevInitCode;
USHORT usIoBaseAddress;
USHORT usSubsystemVendorID;
USHORT usSubsystemID;
USHORT usPCI_InfoOffset;
USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
UCHAR ucExtendedFunctionCode;
UCHAR ucReserved;
}ATOM_ROM_HEADER;
typedef struct _ATOM_ROM_HEADER_V2_1
{
ATOM_COMMON_TABLE_HEADER sHeader;
UCHAR uaFirmWareSignature[4]; //Signature to distinguish between Atombios and non-atombios,
//atombios should init it as "ATOM", don't change the position
USHORT usBiosRuntimeSegmentAddress;
USHORT usProtectedModeInfoOffset;
USHORT usConfigFilenameOffset;
USHORT usCRC_BlockOffset;
USHORT usBIOS_BootupMessageOffset;
USHORT usInt10Offset;
USHORT usPciBusDevInitCode;
USHORT usIoBaseAddress;
USHORT usSubsystemVendorID;
USHORT usSubsystemID;
USHORT usPCI_InfoOffset;
USHORT usMasterCommandTableOffset;//Offest for SW to get all command table offsets, Don't change the position
USHORT usMasterDataTableOffset; //Offest for SW to get all data table offsets, Don't change the position
UCHAR ucExtendedFunctionCode;
UCHAR ucReserved;
ULONG ulPSPDirTableOffset;
}ATOM_ROM_HEADER_V2_1;
//==============================Command Table Portion====================================
/****************************************************************************/
// Structures used in Command.mtb
/****************************************************************************/
typedef struct _ATOM_MASTER_LIST_OF_COMMAND_TABLES{
USHORT ASIC_Init; //Function Table, used by various SW components,latest version 1.1
USHORT GetDisplaySurfaceSize; //Atomic Table, Used by Bios when enabling HW ICON
USHORT ASIC_RegistersInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT VRAM_BlockVenderDetection; //Atomic Table, used only by Bios
USHORT DIGxEncoderControl; //Only used by Bios
USHORT MemoryControllerInit; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT EnableCRTCMemReq; //Function Table,directly used by various SW components,latest version 2.1
USHORT MemoryParamAdjust; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock if needed
USHORT DVOEncoderControl; //Function Table,directly used by various SW components,latest version 1.2
USHORT GPIOPinControl; //Atomic Table, only used by Bios
USHORT SetEngineClock; //Function Table,directly used by various SW components,latest version 1.1
USHORT SetMemoryClock; //Function Table,directly used by various SW components,latest version 1.1
USHORT SetPixelClock; //Function Table,directly used by various SW components,latest version 1.2
USHORT EnableDispPowerGating; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT ResetMemoryDLL; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT ResetMemoryDevice; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT MemoryPLLInit; //Atomic Table, used only by Bios
USHORT AdjustDisplayPll; //Atomic Table, used by various SW componentes.
USHORT AdjustMemoryController; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT EnableASIC_StaticPwrMgt; //Atomic Table, only used by Bios
USHORT SetUniphyInstance; //Atomic Table, only used by Bios
USHORT DAC_LoadDetection; //Atomic Table, directly used by various SW components,latest version 1.2
USHORT LVTMAEncoderControl; //Atomic Table,directly used by various SW components,latest version 1.3
USHORT HW_Misc_Operation; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DAC1EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DAC2EncoderControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT DVOOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT CV1OutputControl; //Atomic Table, Atomic Table, Obsolete from Ry6xx, use DAC2 Output instead
USHORT GetConditionalGoldenSetting; //Only used by Bios
USHORT SMC_Init; //Function Table,directly used by various SW components,latest version 1.1
USHORT PatchMCSetting; //only used by BIOS
USHORT MC_SEQ_Control; //only used by BIOS
USHORT Gfx_Harvesting; //Atomic Table, Obsolete from Ry6xx, Now only used by BIOS for GFX harvesting
USHORT EnableScaler; //Atomic Table, used only by Bios
USHORT BlankCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableCRTC; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT GetPixelClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableVGA_Render; //Function Table,directly used by various SW components,latest version 1.1
USHORT GetSCLKOverMCLKRatio; //Atomic Table, only used by Bios
USHORT SetCRTC_Timing; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetCRTC_OverScan; //Atomic Table, used by various SW components,latest version 1.1
USHORT GetSMUClockInfo; //Atomic Table, used only by Bios
USHORT SelectCRTC_Source; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT EnableGraphSurfaces; //Atomic Table, used only by Bios
USHORT UpdateCRTC_DoubleBufferRegisters; //Atomic Table, used only by Bios
USHORT LUT_AutoFill; //Atomic Table, only used by Bios
USHORT SetDCEClock; //Atomic Table, start from DCE11.1, shared by driver and VBIOS, change DISPCLK and DPREFCLK
USHORT GetMemoryClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT GetEngineClock; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetCRTC_UsingDTDTiming; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ExternalEncoderControl; //Atomic Table, directly used by various SW components,latest version 2.1
USHORT LVTMAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT VRAM_BlockDetectionByStrap; //Atomic Table, used only by Bios
USHORT MemoryCleanUp; //Atomic Table, only used by Bios
USHORT ProcessI2cChannelTransaction; //Function Table,only used by Bios
USHORT WriteOneByteToHWAssistedI2C; //Function Table,indirectly used by various SW components
USHORT ReadHWAssistedI2CStatus; //Atomic Table, indirectly used by various SW components
USHORT SpeedFanControl; //Function Table,indirectly used by various SW components,called from ASIC_Init
USHORT PowerConnectorDetection; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT MC_Synchronization; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT ComputeMemoryEnginePLL; //Atomic Table, indirectly used by various SW components,called from SetMemory/EngineClock
USHORT Gfx_Init; //Atomic Table, indirectly used by various SW components,called from SetMemory or SetEngineClock
USHORT VRAM_GetCurrentInfoBlock; //Atomic Table, used only by Bios
USHORT DynamicMemorySettings; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT MemoryTraining; //Atomic Table, used only by Bios
USHORT EnableSpreadSpectrumOnPPLL; //Atomic Table, directly used by various SW components,latest version 1.2
USHORT TMDSAOutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT SetVoltage; //Function Table,directly and/or indirectly used by various SW components,latest version 1.1
USHORT DAC1OutputControl; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ReadEfuseValue; //Atomic Table, directly used by various SW components,latest version 1.1
USHORT ComputeMemoryClockParam; //Function Table,only used by Bios, obsolete soon.Switch to use "ReadEDIDFromHWAssistedI2C"
USHORT ClockSource; //Atomic Table, indirectly used by various SW components,called from ASIC_Init
USHORT MemoryDeviceInit; //Atomic Table, indirectly used by various SW components,called from SetMemoryClock
USHORT GetDispObjectInfo; //Atomic Table, indirectly used by various SW components,called from EnableVGARender
USHORT DIG1EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG2EncoderControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG1TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT DIG2TransmitterControl; //Atomic Table,directly used by various SW components,latest version 1.1
USHORT ProcessAuxChannelTransaction; //Function Table,only used by Bios
USHORT DPEncoderService; //Function Table,only used by Bios
USHORT GetVoltageInfo; //Function Table,only used by Bios since SI
}ATOM_MASTER_LIST_OF_COMMAND_TABLES;
// For backward compatible
#define ReadEDIDFromHWAssistedI2C ProcessI2cChannelTransaction
#define DPTranslatorControl DIG2EncoderControl
#define UNIPHYTransmitterControl DIG1TransmitterControl
#define LVTMATransmitterControl DIG2TransmitterControl
#define SetCRTC_DPM_State GetConditionalGoldenSetting
#define ASIC_StaticPwrMgtStatusChange SetUniphyInstance
#define HPDInterruptService ReadHWAssistedI2CStatus
#define EnableVGA_Access GetSCLKOverMCLKRatio
#define EnableYUV GetDispObjectInfo
#define DynamicClockGating EnableDispPowerGating
#define SetupHWAssistedI2CStatus ComputeMemoryClockParam
#define DAC2OutputControl ReadEfuseValue
#define TMDSAEncoderControl PatchMCSetting
#define LVDSEncoderControl MC_SEQ_Control
#define LCD1OutputControl HW_Misc_Operation
#define TV1OutputControl Gfx_Harvesting
#define TVEncoderControl SMC_Init
#define EnableHW_IconCursor SetDCEClock
#define SetCRTC_Replication GetSMUClockInfo
#define MemoryRefreshConversion Gfx_Init
typedef struct _ATOM_MASTER_COMMAND_TABLE
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_MASTER_LIST_OF_COMMAND_TABLES ListOfCommandTables;
}ATOM_MASTER_COMMAND_TABLE;
/****************************************************************************/
// Structures used in every command table
/****************************************************************************/
typedef struct _ATOM_TABLE_ATTRIBUTE
{
#if ATOM_BIG_ENDIAN
USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
#else
USHORT WS_SizeInBytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
USHORT PS_SizeInBytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
USHORT UpdatedByUtility:1; //[15]=Table updated by utility flag
#endif
}ATOM_TABLE_ATTRIBUTE;
/****************************************************************************/
// Common header for all command tables.
// Every table pointed by _ATOM_MASTER_COMMAND_TABLE has this common header.
// And the pointer actually points to this header.
/****************************************************************************/
typedef struct _ATOM_COMMON_ROM_COMMAND_TABLE_HEADER
{
ATOM_COMMON_TABLE_HEADER CommonHeader;
ATOM_TABLE_ATTRIBUTE TableAttribute;
}ATOM_COMMON_ROM_COMMAND_TABLE_HEADER;
/****************************************************************************/
// Structures used by ComputeMemoryEnginePLLTable
/****************************************************************************/
#define COMPUTE_MEMORY_PLL_PARAM 1
#define COMPUTE_ENGINE_PLL_PARAM 2
#define ADJUST_MC_SETTING_PARAM 3
/****************************************************************************/
// Structures used by AdjustMemoryControllerTable
/****************************************************************************/
typedef struct _ATOM_ADJUST_MEMORY_CLOCK_FREQ
{
#if ATOM_BIG_ENDIAN
ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
ULONG ulClockFreq:24;
#else
ULONG ulClockFreq:24;
ULONG ulMemoryModuleNumber:7; // BYTE_3[6:0]
ULONG ulPointerReturnFlag:1; // BYTE_3[7]=1 - Return the pointer to the right Data Block; BYTE_3[7]=0 - Program the right Data Block
#endif
}ATOM_ADJUST_MEMORY_CLOCK_FREQ;
#define POINTER_RETURN_FLAG 0x80
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
{
ULONG ulClock; //When returen, it's the re-calculated clock based on given Fb_div Post_Div and ref_div
UCHAR ucAction; //0:reserved //1:Memory //2:Engine
UCHAR ucReserved; //may expand to return larger Fbdiv later
UCHAR ucFbDiv; //return value
UCHAR ucPostDiv; //return value
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS;
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2
{
ULONG ulClock; //When return, [23:0] return real clock
UCHAR ucAction; //0:reserved;COMPUTE_MEMORY_PLL_PARAM:Memory;COMPUTE_ENGINE_PLL_PARAM:Engine. it return ref_div to be written to register
USHORT usFbDiv; //return Feedback value to be written to register
UCHAR ucPostDiv; //return post div to be written to register
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2;
#define COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS
#define SET_CLOCK_FREQ_MASK 0x00FFFFFF //Clock change tables only take bit [23:0] as the requested clock value
#define USE_NON_BUS_CLOCK_MASK 0x01000000 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
#define USE_MEMORY_SELF_REFRESH_MASK 0x02000000 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
#define SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04000000 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
#define FIRST_TIME_CHANGE_CLOCK 0x08000000 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
#define SKIP_SW_PROGRAM_PLL 0x10000000 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
#define USE_SS_ENABLED_PIXEL_CLOCK USE_NON_BUS_CLOCK_MASK
#define b3USE_NON_BUS_CLOCK_MASK 0x01 //Applicable to both memory and engine clock change, when set, it uses another clock as the temporary clock (engine uses memory and vice versa)
#define b3USE_MEMORY_SELF_REFRESH 0x02 //Only applicable to memory clock change, when set, using memory self refresh during clock transition
#define b3SKIP_INTERNAL_MEMORY_PARAMETER_CHANGE 0x04 //Only applicable to memory clock change, when set, the table will skip predefined internal memory parameter change
#define b3FIRST_TIME_CHANGE_CLOCK 0x08 //Applicable to both memory and engine clock change,when set, it means this is 1st time to change clock after ASIC bootup
#define b3SKIP_SW_PROGRAM_PLL 0x10 //Applicable to both memory and engine clock change, when set, it means the table will not program SPLL/MPLL
#define b3DRAM_SELF_REFRESH_EXIT 0x20 //Applicable to DRAM self refresh exit only. when set, it means it will go to program DRAM self refresh exit path
#define b3SRIOV_INIT_BOOT 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
#define b3SRIOV_LOAD_UCODE 0x40 //Use by HV GPU driver only, to load uCode. for ASIC_InitTable SCLK parameter only
#define b3SRIOV_SKIP_ASIC_INIT 0x02 //Use by HV GPU driver only, skip ASIC_Init for primary adapter boot. for ASIC_InitTable SCLK parameter only
typedef struct _ATOM_COMPUTE_CLOCK_FREQ
{
#if ATOM_BIG_ENDIAN
ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
ULONG ulClockFreq:24; // in unit of 10kHz
#else
ULONG ulClockFreq:24; // in unit of 10kHz
ULONG ulComputeClockFlag:8; // =1: COMPUTE_MEMORY_PLL_PARAM, =2: COMPUTE_ENGINE_PLL_PARAM
#endif
}ATOM_COMPUTE_CLOCK_FREQ;
typedef struct _ATOM_S_MPLL_FB_DIVIDER
{
USHORT usFbDivFrac;
USHORT usFbDiv;
}ATOM_S_MPLL_FB_DIVIDER;
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3
{
union
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
};
UCHAR ucRefDiv; //Output Parameter
UCHAR ucPostDiv; //Output Parameter
UCHAR ucCntlFlag; //Output Parameter
UCHAR ucReserved;
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3;
// ucCntlFlag
#define ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN 1
#define ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE 2
#define ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE 4
#define ATOM_PLL_CNTL_FLAG_SPLL_ISPARE_9 8
// V4 are only used for APU which PLL outside GPU
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4
{
#if ATOM_BIG_ENDIAN
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
ULONG ulClock:24; //Input= target clock, output = actual clock
#else
ULONG ulClock:24; //Input= target clock, output = actual clock
ULONG ucPostDiv:8; //return parameter: post divider which is used to program to register directly
#endif
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4;
typedef struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5
{
union
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter
};
UCHAR ucRefDiv; //Output Parameter
UCHAR ucPostDiv; //Output Parameter
union
{
UCHAR ucCntlFlag; //Output Flags
UCHAR ucInputFlag; //Input Flags. ucInputFlag[0] - Strobe(1)/Performance(0) mode
};
UCHAR ucReserved;
}COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5;
typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ULONG ulReserved[2];
}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6;
//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6
{
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output Parameter: PLL FB divider
UCHAR ucPllRefDiv; //Output Parameter: PLL ref divider
UCHAR ucPllPostDiv; //Output Parameter: PLL post divider
UCHAR ucPllCntlFlag; //Output Flags: control flag
UCHAR ucReserved;
}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6;
//ucPllCntlFlag
#define SPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
typedef struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7
{
ATOM_COMPUTE_CLOCK_FREQ ulClock; //Input Parameter
ULONG ulReserved[5];
}COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7;
//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
#define COMPUTE_GPUCLK_INPUT_FLAG_CLK_TYPE_MASK 0x0f
#define COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK 0x00
#define COMPUTE_GPUCLK_INPUT_FLAG_SCLK 0x01
typedef struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7
{
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock; //Output Parameter: ucPostDiv=DFS divider
USHORT usSclk_fcw_frac; //fractional divider of fcw = usSclk_fcw_frac/65536
USHORT usSclk_fcw_int; //integer divider of fcwc
UCHAR ucSclkPostDiv; //PLL post divider = 2^ucSclkPostDiv
UCHAR ucSclkVcoMode; //0: 4G~8Ghz, 1:3G~6Ghz,3: 2G~4Ghz, 2:Reserved
UCHAR ucSclkPllRange; //GreenTable SCLK PLL range entry index ( 0~7 )
UCHAR ucSscEnable;
USHORT usSsc_fcw1_frac; //fcw1_frac when SSC enable
USHORT usSsc_fcw1_int; //fcw1_int when SSC enable
USHORT usReserved;
USHORT usPcc_fcw_int;
USHORT usSsc_fcw_slew_frac; //fcw_slew_frac when SSC enable
USHORT usPcc_fcw_slew_frac;
}COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_7;
// ucInputFlag
#define ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN 1 // 1-StrobeMode, 0-PerformanceMode
// use for ComputeMemoryClockParamTable
typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1
{
union
{
ULONG ulClock;
ATOM_S_MPLL_FB_DIVIDER ulFbDiv; //Output:UPPER_WORD=FB_DIV_INTEGER, LOWER_WORD=FB_DIV_FRAC shl (16-FB_FRACTION_BITS)
};
UCHAR ucDllSpeed; //Output
UCHAR ucPostDiv; //Output
union{
UCHAR ucInputFlag; //Input : ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN: 1-StrobeMode, 0-PerformanceMode
UCHAR ucPllCntlFlag; //Output:
};
UCHAR ucBWCntl;
}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1;
// definition of ucInputFlag
#define MPLL_INPUT_FLAG_STROBE_MODE_EN 0x01
// definition of ucPllCntlFlag
#define MPLL_CNTL_FLAG_VCO_MODE_MASK 0x03
#define MPLL_CNTL_FLAG_BYPASS_DQ_PLL 0x04
#define MPLL_CNTL_FLAG_QDR_ENABLE 0x08
#define MPLL_CNTL_FLAG_AD_HALF_RATE 0x10
//MPLL_CNTL_FLAG_BYPASS_AD_PLL has a wrong name, should be BYPASS_DQ_PLL
#define MPLL_CNTL_FLAG_BYPASS_AD_PLL 0x04
// use for ComputeMemoryClockParamTable
typedef struct _COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2
{
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 ulClock;
ULONG ulReserved;
}COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_2;
//Input parameter of DynamicMemorySettingsTable
//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag = COMPUTE_MEMORY_PLL_PARAM
typedef struct _DYNAMICE_MEMORY_SETTINGS_PARAMETER
{
ATOM_COMPUTE_CLOCK_FREQ ulClock;
ULONG ulReserved[2];
}DYNAMICE_MEMORY_SETTINGS_PARAMETER;
//Input parameter of DynamicMemorySettingsTable
//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == COMPUTE_ENGINE_PLL_PARAM
typedef struct _DYNAMICE_ENGINE_SETTINGS_PARAMETER
{
ATOM_COMPUTE_CLOCK_FREQ ulClock;
ULONG ulMemoryClock;
ULONG ulReserved;
}DYNAMICE_ENGINE_SETTINGS_PARAMETER;
//Input parameter of DynamicMemorySettingsTable ver2.1 and above
//when ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag == ADJUST_MC_SETTING_PARAM
typedef struct _DYNAMICE_MC_DPM_SETTINGS_PARAMETER
{
ATOM_COMPUTE_CLOCK_FREQ ulClock;
UCHAR ucMclkDPMState;
UCHAR ucReserved[3];
ULONG ulReserved;
}DYNAMICE_MC_DPM_SETTINGS_PARAMETER;
//ucMclkDPMState
#define DYNAMIC_MC_DPM_SETTING_LOW_DPM_STATE 0
#define DYNAMIC_MC_DPM_SETTING_MEDIUM_DPM_STATE 1
#define DYNAMIC_MC_DPM_SETTING_HIGH_DPM_STATE 2
typedef union _DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1
{
DYNAMICE_MEMORY_SETTINGS_PARAMETER asMCReg;
DYNAMICE_ENGINE_SETTINGS_PARAMETER asMCArbReg;
DYNAMICE_MC_DPM_SETTINGS_PARAMETER asDPMMCReg;
}DYNAMICE_MEMORY_SETTINGS_PARAMETER_V2_1;
/****************************************************************************/
// Structures used by SetEngineClockTable
/****************************************************************************/
typedef struct _SET_ENGINE_CLOCK_PARAMETERS
{
ULONG ulTargetEngineClock; //In 10Khz unit
}SET_ENGINE_CLOCK_PARAMETERS;
typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION
{
ULONG ulTargetEngineClock; //In 10Khz unit
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
}SET_ENGINE_CLOCK_PS_ALLOCATION;
typedef struct _SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2
{
ULONG ulTargetEngineClock; //In 10Khz unit
COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_7 sReserved;
}SET_ENGINE_CLOCK_PS_ALLOCATION_V1_2;
/****************************************************************************/
// Structures used by SetMemoryClockTable
/****************************************************************************/
typedef struct _SET_MEMORY_CLOCK_PARAMETERS
{
ULONG ulTargetMemoryClock; //In 10Khz unit
}SET_MEMORY_CLOCK_PARAMETERS;
typedef struct _SET_MEMORY_CLOCK_PS_ALLOCATION
{
ULONG ulTargetMemoryClock; //In 10Khz unit
COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_PS_ALLOCATION sReserved;
}SET_MEMORY_CLOCK_PS_ALLOCATION;
/****************************************************************************/
// Structures used by ASIC_Init.ctb
/****************************************************************************/
typedef struct _ASIC_INIT_PARAMETERS
{
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
}ASIC_INIT_PARAMETERS;
typedef struct _ASIC_INIT_PS_ALLOCATION
{
ASIC_INIT_PARAMETERS sASICInitClocks;
SET_ENGINE_CLOCK_PS_ALLOCATION sReserved; //Caller doesn't need to init this structure
}ASIC_INIT_PS_ALLOCATION;
typedef struct _ASIC_INIT_CLOCK_PARAMETERS
{
ULONG ulClkFreqIn10Khz:24;
ULONG ucClkFlag:8;
}ASIC_INIT_CLOCK_PARAMETERS;
typedef struct _ASIC_INIT_PARAMETERS_V1_2
{
ASIC_INIT_CLOCK_PARAMETERS asSclkClock; //In 10Khz unit
ASIC_INIT_CLOCK_PARAMETERS asMemClock; //In 10Khz unit
}ASIC_INIT_PARAMETERS_V1_2;
typedef struct _ASIC_INIT_PS_ALLOCATION_V1_2
{
ASIC_INIT_PARAMETERS_V1_2 sASICInitClocks;
ULONG ulReserved[8];
}ASIC_INIT_PS_ALLOCATION_V1_2;
/****************************************************************************/
// Structure used by DynamicClockGatingTable.ctb
/****************************************************************************/
typedef struct _DYNAMIC_CLOCK_GATING_PARAMETERS
{
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[3];
}DYNAMIC_CLOCK_GATING_PARAMETERS;
#define DYNAMIC_CLOCK_GATING_PS_ALLOCATION DYNAMIC_CLOCK_GATING_PARAMETERS
/****************************************************************************/
// Structure used by EnableDispPowerGatingTable.ctb
/****************************************************************************/
typedef struct _ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1
{
UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[2];
}ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1;
typedef struct _ENABLE_DISP_POWER_GATING_PS_ALLOCATION
{
UCHAR ucDispPipeId; // ATOM_CRTC1, ATOM_CRTC2, ...
UCHAR ucEnable; // ATOM_ENABLE/ATOM_DISABLE/ATOM_INIT
UCHAR ucPadding[2];
ULONG ulReserved[4];
}ENABLE_DISP_POWER_GATING_PS_ALLOCATION;
/****************************************************************************/
// Structure used by EnableASIC_StaticPwrMgtTable.ctb
/****************************************************************************/
typedef struct _ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
{
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[3];
}ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS;
#define ENABLE_ASIC_STATIC_PWR_MGT_PS_ALLOCATION ENABLE_ASIC_STATIC_PWR_MGT_PARAMETERS
/****************************************************************************/
// Structures used by DAC_LoadDetectionTable.ctb
/****************************************************************************/
typedef struct _DAC_LOAD_DETECTION_PARAMETERS
{
USHORT usDeviceID; //{ATOM_DEVICE_CRTx_SUPPORT,ATOM_DEVICE_TVx_SUPPORT,ATOM_DEVICE_CVx_SUPPORT}
UCHAR ucDacType; //{ATOM_DAC_A,ATOM_DAC_B, ATOM_EXT_DAC}
UCHAR ucMisc; //Valid only when table revision =1.3 and above
}DAC_LOAD_DETECTION_PARAMETERS;
// DAC_LOAD_DETECTION_PARAMETERS.ucMisc
#define DAC_LOAD_MISC_YPrPb 0x01
typedef struct _DAC_LOAD_DETECTION_PS_ALLOCATION
{
DAC_LOAD_DETECTION_PARAMETERS sDacload;
ULONG Reserved[2];// Don't set this one, allocation for EXT DAC
}DAC_LOAD_DETECTION_PS_ALLOCATION;
/****************************************************************************/
// Structures used by DAC1EncoderControlTable.ctb and DAC2EncoderControlTable.ctb
/****************************************************************************/
typedef struct _DAC_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucDacStandard; // See definition of ATOM_DACx_xxx, For DEC3.0, bit 7 used as internal flag to indicate DAC2 (==1) or DAC1 (==0)
UCHAR ucAction; // 0: turn off encoder
// 1: setup and turn on encoder
// 7: ATOM_ENCODER_INIT Initialize DAC
}DAC_ENCODER_CONTROL_PARAMETERS;
#define DAC_ENCODER_CONTROL_PS_ALLOCATION DAC_ENCODER_CONTROL_PARAMETERS
/****************************************************************************/
// Structures used by DIG1EncoderControlTable
// DIG2EncoderControlTable
// ExternalEncoderControlTable
/****************************************************************************/
typedef struct _DIG_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucConfig;
// [2] Link Select:
// =0: PHY linkA if bfLane<3
// =1: PHY linkB if bfLanes<3
// =0: PHY linkA+B if bfLanes=3
// [3] Transmitter Sel
// =0: UNIPHY or PCIEPHY
// =1: LVTMA
UCHAR ucAction; // =0: turn off encoder
// =1: turn on encoder
UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucReserved[2];
}DIG_ENCODER_CONTROL_PARAMETERS;
#define DIG_ENCODER_CONTROL_PS_ALLOCATION DIG_ENCODER_CONTROL_PARAMETERS
#define EXTERNAL_ENCODER_CONTROL_PARAMETER DIG_ENCODER_CONTROL_PARAMETERS
//ucConfig
#define ATOM_ENCODER_CONFIG_DPLINKRATE_MASK 0x01
#define ATOM_ENCODER_CONFIG_DPLINKRATE_1_62GHZ 0x00
#define ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ 0x01
#define ATOM_ENCODER_CONFIG_DPLINKRATE_5_40GHZ 0x02
#define ATOM_ENCODER_CONFIG_LINK_SEL_MASK 0x04
#define ATOM_ENCODER_CONFIG_LINKA 0x00
#define ATOM_ENCODER_CONFIG_LINKB 0x04
#define ATOM_ENCODER_CONFIG_LINKA_B ATOM_TRANSMITTER_CONFIG_LINKA
#define ATOM_ENCODER_CONFIG_LINKB_A ATOM_ENCODER_CONFIG_LINKB
#define ATOM_ENCODER_CONFIG_TRANSMITTER_SEL_MASK 0x08
#define ATOM_ENCODER_CONFIG_UNIPHY 0x00
#define ATOM_ENCODER_CONFIG_LVTMA 0x08
#define ATOM_ENCODER_CONFIG_TRANSMITTER1 0x00
#define ATOM_ENCODER_CONFIG_TRANSMITTER2 0x08
#define ATOM_ENCODER_CONFIG_DIGB 0x80 // VBIOS Internal use, outside SW should set this bit=0
// ucAction
// ATOM_ENABLE: Enable Encoder
// ATOM_DISABLE: Disable Encoder
//ucEncoderMode
#define ATOM_ENCODER_MODE_DP 0
#define ATOM_ENCODER_MODE_LVDS 1
#define ATOM_ENCODER_MODE_DVI 2
#define ATOM_ENCODER_MODE_HDMI 3
#define ATOM_ENCODER_MODE_SDVO 4
#define ATOM_ENCODER_MODE_DP_AUDIO 5
#define ATOM_ENCODER_MODE_TV 13
#define ATOM_ENCODER_MODE_CV 14
#define ATOM_ENCODER_MODE_CRT 15
#define ATOM_ENCODER_MODE_DVO 16
#define ATOM_ENCODER_MODE_DP_SST ATOM_ENCODER_MODE_DP // For DP1.2
#define ATOM_ENCODER_MODE_DP_MST 5 // For DP1.2
typedef struct _ATOM_DIG_ENCODER_CONFIG_V2
{
#if ATOM_BIG_ENDIAN
UCHAR ucReserved1:2;
UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
UCHAR ucReserved:1;
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
#else
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
UCHAR ucReserved:1;
UCHAR ucLinkSel:1; // =0: linkA/C/E =1: linkB/D/F
UCHAR ucTransmitterSel:2; // =0: UniphyAB, =1: UniphyCD =2: UniphyEF
UCHAR ucReserved1:2;
#endif
}ATOM_DIG_ENCODER_CONFIG_V2;
typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V2
{
USHORT usPixelClock; // in 10KHz; for bios convenient
ATOM_DIG_ENCODER_CONFIG_V2 acConfig;
UCHAR ucAction;
UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucStatus; // = DP_LINK_TRAINING_COMPLETE or DP_LINK_TRAINING_INCOMPLETE, only used by VBIOS with command ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS
UCHAR ucReserved;
}DIG_ENCODER_CONTROL_PARAMETERS_V2;
//ucConfig
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_MASK 0x01
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_1_62GHZ 0x00
#define ATOM_ENCODER_CONFIG_V2_DPLINKRATE_2_70GHZ 0x01
#define ATOM_ENCODER_CONFIG_V2_LINK_SEL_MASK 0x04
#define ATOM_ENCODER_CONFIG_V2_LINKA 0x00
#define ATOM_ENCODER_CONFIG_V2_LINKB 0x04
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER_SEL_MASK 0x18
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER1 0x00
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER2 0x08
#define ATOM_ENCODER_CONFIG_V2_TRANSMITTER3 0x10
// ucAction:
// ATOM_DISABLE
// ATOM_ENABLE
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_START 0x08
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 0x09
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 0x0a
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 0x13
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE 0x0b
#define ATOM_ENCODER_CMD_DP_VIDEO_OFF 0x0c
#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
#define ATOM_ENCODER_CMD_SETUP 0x0f
#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
// New Command for DIGxEncoderControlTable v1.5
#define ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 0x14
#define ATOM_ENCODER_CMD_STREAM_SETUP 0x0F //change name ATOM_ENCODER_CMD_SETUP
#define ATOM_ENCODER_CMD_LINK_SETUP 0x11 //internal use, called by other Command Table
#define ATOM_ENCODER_CMD_ENCODER_BLANK 0x12 //internal use, called by other Command Table
// ucStatus
#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
#define ATOM_ENCODER_STATUS_LINK_TRAINING_INCOMPLETE 0x00
//ucTableFormatRevision=1
//ucTableContentRevision=3
// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
typedef struct _ATOM_DIG_ENCODER_CONFIG_V3
{
#if ATOM_BIG_ENDIAN
UCHAR ucReserved1:1;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved:3;
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
#else
UCHAR ucDPLinkRate:1; // =0: 1.62Ghz, =1: 2.7Ghz
UCHAR ucReserved:3;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved1:1;
#endif
}ATOM_DIG_ENCODER_CONFIG_V3;
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
#define ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
#define ATOM_ENCODER_CONFIG_V3_ENCODER_SEL 0x70
#define ATOM_ENCODER_CONFIG_V3_DIG0_ENCODER 0x00
#define ATOM_ENCODER_CONFIG_V3_DIG1_ENCODER 0x10
#define ATOM_ENCODER_CONFIG_V3_DIG2_ENCODER 0x20
#define ATOM_ENCODER_CONFIG_V3_DIG3_ENCODER 0x30
#define ATOM_ENCODER_CONFIG_V3_DIG4_ENCODER 0x40
#define ATOM_ENCODER_CONFIG_V3_DIG5_ENCODER 0x50
typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V3
{
USHORT usPixelClock; // in 10KHz; for bios convenient
ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
UCHAR ucAction;
union{
UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
// =5: DP audio
UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
// =0: external DP
// =0x1: internal DP2
// =0x11: internal DP1 for NutMeg/Travis DP translator
};
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
UCHAR ucReserved;
}DIG_ENCODER_CONTROL_PARAMETERS_V3;
//ucTableFormatRevision=1
//ucTableContentRevision=4
// start from NI
// Following function ENABLE sub-function will be used by driver when TMDS/HDMI/LVDS is used, disable function will be used by driver
typedef struct _ATOM_DIG_ENCODER_CONFIG_V4
{
#if ATOM_BIG_ENDIAN
UCHAR ucReserved1:1;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved:2;
UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
#else
UCHAR ucDPLinkRate:2; // =0: 1.62Ghz, =1: 2.7Ghz, 2=5.4Ghz <= Changed comparing to previous version
UCHAR ucReserved:2;
UCHAR ucDigSel:3; // =0/1/2/3/4/5: DIG0/1/2/3/4/5 (In register spec also referred as DIGA/B/C/D/E/F)
UCHAR ucReserved1:1;
#endif
}ATOM_DIG_ENCODER_CONFIG_V4;
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_MASK 0x03
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ 0x00
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ 0x01
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ 0x02
#define ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ 0x03
#define ATOM_ENCODER_CONFIG_V4_ENCODER_SEL 0x70
#define ATOM_ENCODER_CONFIG_V4_DIG0_ENCODER 0x00
#define ATOM_ENCODER_CONFIG_V4_DIG1_ENCODER 0x10
#define ATOM_ENCODER_CONFIG_V4_DIG2_ENCODER 0x20
#define ATOM_ENCODER_CONFIG_V4_DIG3_ENCODER 0x30
#define ATOM_ENCODER_CONFIG_V4_DIG4_ENCODER 0x40
#define ATOM_ENCODER_CONFIG_V4_DIG5_ENCODER 0x50
#define ATOM_ENCODER_CONFIG_V4_DIG6_ENCODER 0x60
typedef struct _DIG_ENCODER_CONTROL_PARAMETERS_V4
{
USHORT usPixelClock; // in 10KHz; for bios convenient
union{
ATOM_DIG_ENCODER_CONFIG_V4 acConfig;
UCHAR ucConfig;
};
UCHAR ucAction;
union{
UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
// =5: DP audio
UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
// =0: external DP
// =0x1: internal DP2
// =0x11: internal DP1 for NutMeg/Travis DP translator
};
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
}DIG_ENCODER_CONTROL_PARAMETERS_V4;
// define ucBitPerColor:
#define PANEL_BPC_UNDEFINE 0x00
#define PANEL_6BIT_PER_COLOR 0x01
#define PANEL_8BIT_PER_COLOR 0x02
#define PANEL_10BIT_PER_COLOR 0x03
#define PANEL_12BIT_PER_COLOR 0x04
#define PANEL_16BIT_PER_COLOR 0x05
//define ucPanelMode
#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
typedef struct _ENCODER_STREAM_SETUP_PARAMETERS_V5
{
UCHAR ucDigId; // 0~6 map to DIG0~DIG6
UCHAR ucAction; // = ATOM_ENOCODER_CMD_STREAM_SETUP
UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
UCHAR ucLaneNum; // Lane number
ULONG ulPixelClock; // Pixel Clock in 10Khz
UCHAR ucBitPerColor;
UCHAR ucLinkRateIn270Mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
UCHAR ucReserved[2];
}ENCODER_STREAM_SETUP_PARAMETERS_V5;
typedef struct _ENCODER_LINK_SETUP_PARAMETERS_V5
{
UCHAR ucDigId; // 0~6 map to DIG0~DIG6
UCHAR ucAction; // = ATOM_ENOCODER_CMD_LINK_SETUP
UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
UCHAR ucLaneNum; // Lane number
ULONG ulSymClock; // Symbol Clock in 10Khz
UCHAR ucHPDSel;
UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
UCHAR ucReserved[2];
}ENCODER_LINK_SETUP_PARAMETERS_V5;
typedef struct _DP_PANEL_MODE_SETUP_PARAMETERS_V5
{
UCHAR ucDigId; // 0~6 map to DIG0~DIG6
UCHAR ucAction; // = ATOM_ENCODER_CMD_DPLINK_SETUP
UCHAR ucPanelMode; // =0: external DP
// =0x1: internal DP2
// =0x11: internal DP1 NutMeg/Travis DP Translator
UCHAR ucReserved;
ULONG ulReserved[2];
}DP_PANEL_MODE_SETUP_PARAMETERS_V5;
typedef struct _ENCODER_GENERIC_CMD_PARAMETERS_V5
{
UCHAR ucDigId; // 0~6 map to DIG0~DIG6
UCHAR ucAction; // = rest of generic encoder command which does not carry any parameters
UCHAR ucReserved[2];
ULONG ulReserved[2];
}ENCODER_GENERIC_CMD_PARAMETERS_V5;
//ucDigId
#define ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER 0x00
#define ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER 0x01
#define ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER 0x02
#define ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER 0x03
#define ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER 0x04
#define ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER 0x05
#define ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER 0x06
typedef union _DIG_ENCODER_CONTROL_PARAMETERS_V5
{
ENCODER_GENERIC_CMD_PARAMETERS_V5 asCmdParam;
ENCODER_STREAM_SETUP_PARAMETERS_V5 asStreamParam;
ENCODER_LINK_SETUP_PARAMETERS_V5 asLinkParam;
DP_PANEL_MODE_SETUP_PARAMETERS_V5 asDPPanelModeParam;
}DIG_ENCODER_CONTROL_PARAMETERS_V5;
/****************************************************************************/
// Structures used by UNIPHYTransmitterControlTable
// LVTMATransmitterControlTable
// DVOOutputControlTable
/****************************************************************************/
typedef struct _ATOM_DP_VS_MODE
{
UCHAR ucLaneSel;
UCHAR ucLaneSet;
}ATOM_DP_VS_MODE;
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS
{
union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
UCHAR ucConfig;
// [0]=0: 4 lane Link,
// =1: 8 lane Link ( Dual Links TMDS )
// [1]=0: InCoherent mode
// =1: Coherent Mode
// [2] Link Select:
// =0: PHY linkA if bfLane<3
// =1: PHY linkB if bfLanes<3
// =0: PHY linkA+B if bfLanes=3
// [5:4]PCIE lane Sel
// =0: lane 0~3 or 0~7
// =1: lane 4~7
// =2: lane 8~11 or 8~15
// =3: lane 12~15
UCHAR ucAction; // =0: turn off encoder
// =1: turn on encoder
UCHAR ucReserved[4];
}DIG_TRANSMITTER_CONTROL_PARAMETERS;
#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PARAMETERS
//ucInitInfo
#define ATOM_TRAMITTER_INITINFO_CONNECTOR_MASK 0x00ff
//ucConfig
#define ATOM_TRANSMITTER_CONFIG_8LANE_LINK 0x01
#define ATOM_TRANSMITTER_CONFIG_COHERENT 0x02
#define ATOM_TRANSMITTER_CONFIG_LINK_SEL_MASK 0x04
#define ATOM_TRANSMITTER_CONFIG_LINKA 0x00
#define ATOM_TRANSMITTER_CONFIG_LINKB 0x04
#define ATOM_TRANSMITTER_CONFIG_LINKA_B 0x00
#define ATOM_TRANSMITTER_CONFIG_LINKB_A 0x04
#define ATOM_TRANSMITTER_CONFIG_ENCODER_SEL_MASK 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
#define ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER 0x00 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
#define ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER 0x08 // only used when ATOM_TRANSMITTER_ACTION_ENABLE
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_MASK 0x30
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL 0x00
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_PCIE 0x20
#define ATOM_TRANSMITTER_CONFIG_CLKSRC_XTALIN 0x30
#define ATOM_TRANSMITTER_CONFIG_LANE_SEL_MASK 0xc0
#define ATOM_TRANSMITTER_CONFIG_LANE_0_3 0x00
#define ATOM_TRANSMITTER_CONFIG_LANE_0_7 0x00
#define ATOM_TRANSMITTER_CONFIG_LANE_4_7 0x40
#define ATOM_TRANSMITTER_CONFIG_LANE_8_11 0x80
#define ATOM_TRANSMITTER_CONFIG_LANE_8_15 0x80
#define ATOM_TRANSMITTER_CONFIG_LANE_12_15 0xc0
//ucAction
#define ATOM_TRANSMITTER_ACTION_DISABLE 0
#define ATOM_TRANSMITTER_ACTION_ENABLE 1
#define ATOM_TRANSMITTER_ACTION_LCD_BLOFF 2
#define ATOM_TRANSMITTER_ACTION_LCD_BLON 3
#define ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL 4
#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START 5
#define ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP 6
#define ATOM_TRANSMITTER_ACTION_INIT 7
#define ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT 8
#define ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT 9
#define ATOM_TRANSMITTER_ACTION_SETUP 10
#define ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH 11
#define ATOM_TRANSMITTER_ACTION_POWER_ON 12
#define ATOM_TRANSMITTER_ACTION_POWER_OFF 13
// Following are used for DigTransmitterControlTable ver1.2
typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V2
{
#if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucReserved:1;
UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
#else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA( DIG inst0 ). =1: Data/clk path source from DIGB ( DIG inst1 )
UCHAR fDPConnector:1; //bit4=0: DP connector =1: None DP connector
UCHAR ucReserved:1;
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
#endif
}ATOM_DIG_TRANSMITTER_CONFIG_V2;
//ucConfig
//Bit0
#define ATOM_TRANSMITTER_CONFIG_V2_DUAL_LINK_CONNECTOR 0x01
//Bit1
#define ATOM_TRANSMITTER_CONFIG_V2_COHERENT 0x02
//Bit2
#define ATOM_TRANSMITTER_CONFIG_V2_LINK_SEL_MASK 0x04
#define ATOM_TRANSMITTER_CONFIG_V2_LINKA 0x00
#define ATOM_TRANSMITTER_CONFIG_V2_LINKB 0x04
// Bit3
#define ATOM_TRANSMITTER_CONFIG_V2_ENCODER_SEL_MASK 0x08
#define ATOM_TRANSMITTER_CONFIG_V2_DIG1_ENCODER 0x00 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
#define ATOM_TRANSMITTER_CONFIG_V2_DIG2_ENCODER 0x08 // only used when ucAction == ATOM_TRANSMITTER_ACTION_ENABLE or ATOM_TRANSMITTER_ACTION_SETUP
// Bit4
#define ATOM_TRASMITTER_CONFIG_V2_DP_CONNECTOR 0x10
// Bit7:6
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER_SEL_MASK 0xC0
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER1 0x00 //AB
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER2 0x40 //CD
#define ATOM_TRANSMITTER_CONFIG_V2_TRANSMITTER3 0x80 //EF
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V2
{
union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
ATOM_DIG_TRANSMITTER_CONFIG_V2 acConfig;
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucReserved[4];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V2;
typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V3
{
#if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
#else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
#endif
}ATOM_DIG_TRANSMITTER_CONFIG_V3;
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V3
{
union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE asMode; // DP Voltage swing mode
};
ATOM_DIG_TRANSMITTER_CONFIG_V3 acConfig;
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucLaneNum;
UCHAR ucReserved[3];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V3;
//ucConfig
//Bit0
#define ATOM_TRANSMITTER_CONFIG_V3_DUAL_LINK_CONNECTOR 0x01
//Bit1
#define ATOM_TRANSMITTER_CONFIG_V3_COHERENT 0x02
//Bit2
#define ATOM_TRANSMITTER_CONFIG_V3_LINK_SEL_MASK 0x04
#define ATOM_TRANSMITTER_CONFIG_V3_LINKA 0x00
#define ATOM_TRANSMITTER_CONFIG_V3_LINKB 0x04
// Bit3
#define ATOM_TRANSMITTER_CONFIG_V3_ENCODER_SEL_MASK 0x08
#define ATOM_TRANSMITTER_CONFIG_V3_DIG1_ENCODER 0x00
#define ATOM_TRANSMITTER_CONFIG_V3_DIG2_ENCODER 0x08
// Bit5:4
#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SEL_MASK 0x30
#define ATOM_TRASMITTER_CONFIG_V3_P1PLL 0x00
#define ATOM_TRASMITTER_CONFIG_V3_P2PLL 0x10
#define ATOM_TRASMITTER_CONFIG_V3_REFCLK_SRC_EXT 0x20
// Bit7:6
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER_SEL_MASK 0xC0
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER1 0x00 //AB
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER2 0x40 //CD
#define ATOM_TRANSMITTER_CONFIG_V3_TRANSMITTER3 0x80 //EF
/****************************************************************************/
// Structures used by UNIPHYTransmitterControlTable V1.4
// ASIC Families: NI
// ucTableFormatRevision=1
// ucTableContentRevision=4
/****************************************************************************/
typedef struct _ATOM_DP_VS_MODE_V4
{
UCHAR ucLaneSel;
union
{
UCHAR ucLaneSet;
struct {
#if ATOM_BIG_ENDIAN
UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
#else
UCHAR ucVOLTAGE_SWING:3; //Bit[2:0] Voltage Swing Level
UCHAR ucPRE_EMPHASIS:3; //Bit[5:3] Pre-emphasis Level
UCHAR ucPOST_CURSOR2:2; //Bit[7:6] Post Cursor2 Level <= New in V4
#endif
};
};
}ATOM_DP_VS_MODE_V4;
typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V4
{
#if ATOM_BIG_ENDIAN
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
#else
UCHAR fDualLinkConnector:1; //bit0=1: Dual Link DVI connector
UCHAR fCoherentMode:1; //bit1=1: Coherent Mode ( for DVI/HDMI mode )
UCHAR ucLinkSel:1; //bit2=0: Uniphy LINKA or C or E when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is A or C or E
// =1: Uniphy LINKB or D or F when fDualLinkConnector=0. when fDualLinkConnector=1, it means master link of dual link is B or D or F
UCHAR ucEncoderSel:1; //bit3=0: Data/Clk path source from DIGA/C/E. =1: Data/clk path source from DIGB/D/F
UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
UCHAR ucTransmitterSel:2; //bit7:6: =0 Dig Transmitter 1 ( Uniphy AB )
// =1 Dig Transmitter 2 ( Uniphy CD )
// =2 Dig Transmitter 3 ( Uniphy EF )
#endif
}ATOM_DIG_TRANSMITTER_CONFIG_V4;
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V4
{
union
{
USHORT usPixelClock; // in 10KHz; for bios convenient
USHORT usInitInfo; // when init uniphy,lower 8bit is used for connector type defined in objectid.h
ATOM_DP_VS_MODE_V4 asMode; // DP Voltage swing mode Redefined comparing to previous version
};
union
{
ATOM_DIG_TRANSMITTER_CONFIG_V4 acConfig;
UCHAR ucConfig;
};
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_XXX
UCHAR ucLaneNum;
UCHAR ucReserved[3];
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V4;
//ucConfig
//Bit0
#define ATOM_TRANSMITTER_CONFIG_V4_DUAL_LINK_CONNECTOR 0x01
//Bit1
#define ATOM_TRANSMITTER_CONFIG_V4_COHERENT 0x02
//Bit2
#define ATOM_TRANSMITTER_CONFIG_V4_LINK_SEL_MASK 0x04
#define ATOM_TRANSMITTER_CONFIG_V4_LINKA 0x00
#define ATOM_TRANSMITTER_CONFIG_V4_LINKB 0x04
// Bit3
#define ATOM_TRANSMITTER_CONFIG_V4_ENCODER_SEL_MASK 0x08
#define ATOM_TRANSMITTER_CONFIG_V4_DIG1_ENCODER 0x00
#define ATOM_TRANSMITTER_CONFIG_V4_DIG2_ENCODER 0x08
// Bit5:4
#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SEL_MASK 0x30
#define ATOM_TRANSMITTER_CONFIG_V4_P1PLL 0x00
#define ATOM_TRANSMITTER_CONFIG_V4_P2PLL 0x10
#define ATOM_TRANSMITTER_CONFIG_V4_DCPLL 0x20 // New in _V4
#define ATOM_TRANSMITTER_CONFIG_V4_REFCLK_SRC_EXT 0x30 // Changed comparing to V3
// Bit7:6
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER_SEL_MASK 0xC0
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER1 0x00 //AB
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER2 0x40 //CD
#define ATOM_TRANSMITTER_CONFIG_V4_TRANSMITTER3 0x80 //EF
typedef struct _ATOM_DIG_TRANSMITTER_CONFIG_V5
{
#if ATOM_BIG_ENDIAN
UCHAR ucReservd1:1;
UCHAR ucHPDSel:3;
UCHAR ucPhyClkSrcId:2;
UCHAR ucCoherentMode:1;
UCHAR ucReserved:1;
#else
UCHAR ucReserved:1;
UCHAR ucCoherentMode:1;
UCHAR ucPhyClkSrcId:2;
UCHAR ucHPDSel:3;
UCHAR ucReservd1:1;
#endif
}ATOM_DIG_TRANSMITTER_CONFIG_V5;
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
{
USHORT usSymClock; // Encoder Clock in 10kHz,(DP mode)= linkclock/10, (TMDS/LVDS/HDMI)= pixel clock, (HDMI deep color), =pixel clock * deep_color_ratio
UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
UCHAR ucLaneNum; // indicate lane number 1-8
UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
UCHAR ucDigMode; // indicate DIG mode
union{
ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
UCHAR ucConfig;
};
UCHAR ucDigEncoderSel; // indicate DIG front end encoder
UCHAR ucDPLaneSet;
UCHAR ucReserved;
UCHAR ucReserved1;
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5;
//ucPhyId
#define ATOM_PHY_ID_UNIPHYA 0
#define ATOM_PHY_ID_UNIPHYB 1
#define ATOM_PHY_ID_UNIPHYC 2
#define ATOM_PHY_ID_UNIPHYD 3
#define ATOM_PHY_ID_UNIPHYE 4
#define ATOM_PHY_ID_UNIPHYF 5
#define ATOM_PHY_ID_UNIPHYG 6
// ucDigEncoderSel
#define ATOM_TRANMSITTER_V5__DIGA_SEL 0x01
#define ATOM_TRANMSITTER_V5__DIGB_SEL 0x02
#define ATOM_TRANMSITTER_V5__DIGC_SEL 0x04
#define ATOM_TRANMSITTER_V5__DIGD_SEL 0x08
#define ATOM_TRANMSITTER_V5__DIGE_SEL 0x10
#define ATOM_TRANMSITTER_V5__DIGF_SEL 0x20
#define ATOM_TRANMSITTER_V5__DIGG_SEL 0x40
// ucDigMode
#define ATOM_TRANSMITTER_DIGMODE_V5_DP 0
#define ATOM_TRANSMITTER_DIGMODE_V5_LVDS 1
#define ATOM_TRANSMITTER_DIGMODE_V5_DVI 2
#define ATOM_TRANSMITTER_DIGMODE_V5_HDMI 3
#define ATOM_TRANSMITTER_DIGMODE_V5_SDVO 4
#define ATOM_TRANSMITTER_DIGMODE_V5_DP_MST 5
// ucDPLaneSet
#define DP_LANE_SET__0DB_0_4V 0x00
#define DP_LANE_SET__0DB_0_6V 0x01
#define DP_LANE_SET__0DB_0_8V 0x02
#define DP_LANE_SET__0DB_1_2V 0x03
#define DP_LANE_SET__3_5DB_0_4V 0x08
#define DP_LANE_SET__3_5DB_0_6V 0x09
#define DP_LANE_SET__3_5DB_0_8V 0x0a
#define DP_LANE_SET__6DB_0_4V 0x10
#define DP_LANE_SET__6DB_0_6V 0x11
#define DP_LANE_SET__9_5DB_0_4V 0x18
// ATOM_DIG_TRANSMITTER_CONFIG_V5 asConfig;
// Bit1
#define ATOM_TRANSMITTER_CONFIG_V5_COHERENT 0x02
// Bit3:2
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_MASK 0x0c
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SEL_SHIFT 0x02
#define ATOM_TRANSMITTER_CONFIG_V5_P1PLL 0x00
#define ATOM_TRANSMITTER_CONFIG_V5_P2PLL 0x04
#define ATOM_TRANSMITTER_CONFIG_V5_P0PLL 0x08
#define ATOM_TRANSMITTER_CONFIG_V5_REFCLK_SRC_EXT 0x0c
// Bit6:4
#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_MASK 0x70
#define ATOM_TRANSMITTER_CONFIG_V5_HPD_SEL_SHIFT 0x04
#define ATOM_TRANSMITTER_CONFIG_V5_NO_HPD_SEL 0x00
#define ATOM_TRANSMITTER_CONFIG_V5_HPD1_SEL 0x10
#define ATOM_TRANSMITTER_CONFIG_V5_HPD2_SEL 0x20
#define ATOM_TRANSMITTER_CONFIG_V5_HPD3_SEL 0x30
#define ATOM_TRANSMITTER_CONFIG_V5_HPD4_SEL 0x40
#define ATOM_TRANSMITTER_CONFIG_V5_HPD5_SEL 0x50
#define ATOM_TRANSMITTER_CONFIG_V5_HPD6_SEL 0x60
#define DIG_TRANSMITTER_CONTROL_PS_ALLOCATION_V1_5 DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5
typedef struct _DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6
{
UCHAR ucPhyId; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
UCHAR ucAction; // define as ATOM_TRANSMITER_ACTION_xxx
union
{
UCHAR ucDigMode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
UCHAR ucDPLaneSet; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
};
UCHAR ucLaneNum; // Lane number
ULONG ulSymClock; // Symbol Clock in 10Khz
UCHAR ucHPDSel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
UCHAR ucDigEncoderSel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
UCHAR ucConnObjId; // Connector Object Id defined in ObjectId.h
UCHAR ucReserved;
ULONG ulReserved;
}DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_6;
// ucDigEncoderSel
#define ATOM_TRANMSITTER_V6__DIGA_SEL 0x01
#define ATOM_TRANMSITTER_V6__DIGB_SEL 0x02
#define ATOM_TRANMSITTER_V6__DIGC_SEL 0x04
#define ATOM_TRANMSITTER_V6__DIGD_SEL 0x08
#define ATOM_TRANMSITTER_V6__DIGE_SEL 0x10
#define ATOM_TRANMSITTER_V6__DIGF_SEL 0x20
#define ATOM_TRANMSITTER_V6__DIGG_SEL 0x40
// ucDigMode
#define ATOM_TRANSMITTER_DIGMODE_V6_DP 0
#define ATOM_TRANSMITTER_DIGMODE_V6_DVI 2
#define ATOM_TRANSMITTER_DIGMODE_V6_HDMI 3
#define ATOM_TRANSMITTER_DIGMODE_V6_DP_MST 5
//ucHPDSel
#define ATOM_TRANSMITTER_V6_NO_HPD_SEL 0x00
#define ATOM_TRANSMITTER_V6_HPD1_SEL 0x01
#define ATOM_TRANSMITTER_V6_HPD2_SEL 0x02
#define ATOM_TRANSMITTER_V6_HPD3_SEL 0x03
#define ATOM_TRANSMITTER_V6_HPD4_SEL 0x04
#define ATOM_TRANSMITTER_V6_HPD5_SEL 0x05
#define ATOM_TRANSMITTER_V6_HPD6_SEL 0x06
/****************************************************************************/
// Structures used by ExternalEncoderControlTable V1.3
// ASIC Families: Evergreen, Llano, NI
// ucTableFormatRevision=1
// ucTableContentRevision=3
/****************************************************************************/
typedef struct _EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3
{
union{
USHORT usPixelClock; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
USHORT usConnectorId; // connector id, valid when ucAction = INIT
};
UCHAR ucConfig; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucAction; //
UCHAR ucEncoderMode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucLaneNum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
UCHAR ucBitPerColor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
UCHAR ucReserved;
}EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3;
// ucAction
#define EXTERANL_ENCODER_ACTION_V3_DISABLE_OUTPUT 0x00
#define EXTERANL_ENCODER_ACTION_V3_ENABLE_OUTPUT 0x01
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT 0x07
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP 0x0f
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF 0x10
#define EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING 0x11
#define EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION 0x12
#define EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP 0x14
// ucConfig
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK 0x03
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ 0x00
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ 0x01
#define EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ 0x02
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS 0x70
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 0x00
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 0x10
#define EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 0x20
typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3
{
EXTERNAL_ENCODER_CONTROL_PARAMETERS_V3 sExtEncoder;
ULONG ulReserved[2];
}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3;
/****************************************************************************/
// Structures used by DAC1OuputControlTable
// DAC2OuputControlTable
// LVTMAOutputControlTable (Before DEC30)
// TMDSAOutputControlTable (Before DEC30)
/****************************************************************************/
typedef struct _DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
{
UCHAR ucAction; // Possible input:ATOM_ENABLE||ATOMDISABLE
// When the display is LCD, in addition to above:
// ATOM_LCD_BLOFF|| ATOM_LCD_BLON ||ATOM_LCD_BL_BRIGHTNESS_CONTROL||ATOM_LCD_SELFTEST_START||
// ATOM_LCD_SELFTEST_STOP
UCHAR aucPadding[3]; // padding to DWORD aligned
}DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS;
#define DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define CRT1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define CRT1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define CRT2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define CRT2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define CV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define CV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define TV1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define TV1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define DFP1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define DFP1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define DFP2_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define DFP2_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define LCD1_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define LCD1_OUTPUT_CONTROL_PS_ALLOCATION DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION
#define DVO_OUTPUT_CONTROL_PARAMETERS DISPLAY_DEVICE_OUTPUT_CONTROL_PARAMETERS
#define DVO_OUTPUT_CONTROL_PS_ALLOCATION DIG_TRANSMITTER_CONTROL_PS_ALLOCATION
#define DVO_OUTPUT_CONTROL_PARAMETERS_V3 DIG_TRANSMITTER_CONTROL_PARAMETERS
typedef struct _LVTMA_OUTPUT_CONTROL_PARAMETERS_V2
{
// Possible value of ucAction
// ATOM_TRANSMITTER_ACTION_LCD_BLON
// ATOM_TRANSMITTER_ACTION_LCD_BLOFF
// ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL
// ATOM_TRANSMITTER_ACTION_POWER_ON
// ATOM_TRANSMITTER_ACTION_POWER_OFF
UCHAR ucAction;
UCHAR ucBriLevel;
USHORT usPwmFreq; // in unit of Hz, 200 means 200Hz
}LVTMA_OUTPUT_CONTROL_PARAMETERS_V2;
/****************************************************************************/
// Structures used by BlankCRTCTable
/****************************************************************************/
typedef struct _BLANK_CRTC_PARAMETERS
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucBlanking; // ATOM_BLANKING or ATOM_BLANKINGOFF
USHORT usBlackColorRCr;
USHORT usBlackColorGY;
USHORT usBlackColorBCb;
}BLANK_CRTC_PARAMETERS;
#define BLANK_CRTC_PS_ALLOCATION BLANK_CRTC_PARAMETERS
/****************************************************************************/
// Structures used by EnableCRTCTable
// EnableCRTCMemReqTable
// UpdateCRTC_DoubleBufferRegistersTable
/****************************************************************************/
typedef struct _ENABLE_CRTC_PARAMETERS
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[2];
}ENABLE_CRTC_PARAMETERS;
#define ENABLE_CRTC_PS_ALLOCATION ENABLE_CRTC_PARAMETERS
/****************************************************************************/
// Structures used by SetCRTC_OverScanTable
/****************************************************************************/
typedef struct _SET_CRTC_OVERSCAN_PARAMETERS
{
USHORT usOverscanRight; // right
USHORT usOverscanLeft; // left
USHORT usOverscanBottom; // bottom
USHORT usOverscanTop; // top
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucPadding[3];
}SET_CRTC_OVERSCAN_PARAMETERS;
#define SET_CRTC_OVERSCAN_PS_ALLOCATION SET_CRTC_OVERSCAN_PARAMETERS
/****************************************************************************/
// Structures used by SetCRTC_ReplicationTable
/****************************************************************************/
typedef struct _SET_CRTC_REPLICATION_PARAMETERS
{
UCHAR ucH_Replication; // horizontal replication
UCHAR ucV_Replication; // vertical replication
UCHAR usCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucPadding;
}SET_CRTC_REPLICATION_PARAMETERS;
#define SET_CRTC_REPLICATION_PS_ALLOCATION SET_CRTC_REPLICATION_PARAMETERS
/****************************************************************************/
// Structures used by SelectCRTC_SourceTable
/****************************************************************************/
typedef struct _SELECT_CRTC_SOURCE_PARAMETERS
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucDevice; // ATOM_DEVICE_CRT1|ATOM_DEVICE_CRT2|....
UCHAR ucPadding[2];
}SELECT_CRTC_SOURCE_PARAMETERS;
#define SELECT_CRTC_SOURCE_PS_ALLOCATION SELECT_CRTC_SOURCE_PARAMETERS
typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V2
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
UCHAR ucPadding;
}SELECT_CRTC_SOURCE_PARAMETERS_V2;
//ucEncoderID
//#define ASIC_INT_DAC1_ENCODER_ID 0x00
//#define ASIC_INT_TV_ENCODER_ID 0x02
//#define ASIC_INT_DIG1_ENCODER_ID 0x03
//#define ASIC_INT_DAC2_ENCODER_ID 0x04
//#define ASIC_EXT_TV_ENCODER_ID 0x06
//#define ASIC_INT_DVO_ENCODER_ID 0x07
//#define ASIC_INT_DIG2_ENCODER_ID 0x09
//#define ASIC_EXT_DIG_ENCODER_ID 0x05
//ucEncodeMode
//#define ATOM_ENCODER_MODE_DP 0
//#define ATOM_ENCODER_MODE_LVDS 1
//#define ATOM_ENCODER_MODE_DVI 2
//#define ATOM_ENCODER_MODE_HDMI 3
//#define ATOM_ENCODER_MODE_SDVO 4
//#define ATOM_ENCODER_MODE_TV 13
//#define ATOM_ENCODER_MODE_CV 14
//#define ATOM_ENCODER_MODE_CRT 15
typedef struct _SELECT_CRTC_SOURCE_PARAMETERS_V3
{
UCHAR ucCRTC; // ATOM_CRTC1 or ATOM_CRTC2
UCHAR ucEncoderID; // DAC1/DAC2/TVOUT/DIG1/DIG2/DVO
UCHAR ucEncodeMode; // Encoding mode, only valid when using DIG1/DIG2/DVO
UCHAR ucDstBpc; // PANEL_6/8/10/12BIT_PER_COLOR
}SELECT_CRTC_SOURCE_PARAMETERS_V3;
/****************************************************************************/
// Structures used by SetPixelClockTable
// GetPixelClockTable
/****************************************************************************/
//Major revision=1., Minor revision=1
typedef struct _PIXEL_CLOCK_PARAMETERS
{
USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
// 0 means disable PPLL
USHORT usRefDiv; // Reference divider
USHORT usFbDiv; // feedback divider
UCHAR ucPostDiv; // post divider
UCHAR ucFracFbDiv; // fractional feedback divider
UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
UCHAR ucCRTC; // Which CRTC uses this Ppll
UCHAR ucPadding;
}PIXEL_CLOCK_PARAMETERS;
//Major revision=1., Minor revision=2, add ucMiscIfno
//ucMiscInfo:
#define MISC_FORCE_REPROG_PIXEL_CLOCK 0x1
#define MISC_DEVICE_INDEX_MASK 0xF0
#define MISC_DEVICE_INDEX_SHIFT 4
typedef struct _PIXEL_CLOCK_PARAMETERS_V2
{
USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
// 0 means disable PPLL
USHORT usRefDiv; // Reference divider
USHORT usFbDiv; // feedback divider
UCHAR ucPostDiv; // post divider
UCHAR ucFracFbDiv; // fractional feedback divider
UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
UCHAR ucRefDivSrc; // ATOM_PJITTER or ATO_NONPJITTER
UCHAR ucCRTC; // Which CRTC uses this Ppll
UCHAR ucMiscInfo; // Different bits for different purpose, bit [7:4] as device index, bit[0]=Force prog
}PIXEL_CLOCK_PARAMETERS_V2;
//Major revision=1., Minor revision=3, structure/definition change
//ucEncoderMode:
//ATOM_ENCODER_MODE_DP
//ATOM_ENOCDER_MODE_LVDS
//ATOM_ENOCDER_MODE_DVI
//ATOM_ENOCDER_MODE_HDMI
//ATOM_ENOCDER_MODE_SDVO
//ATOM_ENCODER_MODE_TV 13
//ATOM_ENCODER_MODE_CV 14
//ATOM_ENCODER_MODE_CRT 15
//ucDVOConfig
//#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
//#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
//#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
//#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
//#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
//#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
//#define DVO_ENCODER_CONFIG_24BIT 0x08
//ucMiscInfo: also changed, see below
#define PIXEL_CLOCK_MISC_FORCE_PROG_PPLL 0x01
#define PIXEL_CLOCK_MISC_VGA_MODE 0x02
#define PIXEL_CLOCK_MISC_CRTC_SEL_MASK 0x04
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC1 0x00
#define PIXEL_CLOCK_MISC_CRTC_SEL_CRTC2 0x04
#define PIXEL_CLOCK_MISC_USE_ENGINE_FOR_DISPCLK 0x08
#define PIXEL_CLOCK_MISC_REF_DIV_SRC 0x10
// V1.4 for RoadRunner
#define PIXEL_CLOCK_V4_MISC_SS_ENABLE 0x10
#define PIXEL_CLOCK_V4_MISC_COHERENT_MODE 0x20
typedef struct _PIXEL_CLOCK_PARAMETERS_V3
{
USHORT usPixelClock; // in 10kHz unit; for bios convenient = (RefClk*FB_Div)/(Ref_Div*Post_Div)
// 0 means disable PPLL. For VGA PPLL,make sure this value is not 0.
USHORT usRefDiv; // Reference divider
USHORT usFbDiv; // feedback divider
UCHAR ucPostDiv; // post divider
UCHAR ucFracFbDiv; // fractional feedback divider
UCHAR ucPpll; // ATOM_PPLL1 or ATOM_PPL2
UCHAR ucTransmitterId; // graphic encoder id defined in objectId.h
union
{
UCHAR ucEncoderMode; // encoder type defined as ATOM_ENCODER_MODE_DP/DVI/HDMI/
UCHAR ucDVOConfig; // when use DVO, need to know SDR/DDR, 12bit or 24bit
};
UCHAR ucMiscInfo; // bit[0]=Force program, bit[1]= set pclk for VGA, b[2]= CRTC sel
// bit[3]=0:use PPLL for dispclk source, =1: use engine clock for dispclock source
// bit[4]=0:use XTALIN as the source of reference divider,=1 use the pre-defined clock as the source of reference divider
}PIXEL_CLOCK_PARAMETERS_V3;
#define PIXEL_CLOCK_PARAMETERS_LAST PIXEL_CLOCK_PARAMETERS_V2
#define GET_PIXEL_CLOCK_PS_ALLOCATION PIXEL_CLOCK_PARAMETERS_LAST
typedef struct _PIXEL_CLOCK_PARAMETERS_V5
{
UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
// drive the pixel clock. not used for DCPLL case.
union{
UCHAR ucReserved;
UCHAR ucFracFbDiv; // [gphan] temporary to prevent build problem. remove it after driver code is changed.
};
USHORT usPixelClock; // target the pixel clock to drive the CRTC timing
// 0 means disable PPLL/DCPLL.
USHORT usFbDiv; // feedback divider integer part.
UCHAR ucPostDiv; // post divider.
UCHAR ucRefDiv; // Reference divider
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
// indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PPLL
// bit[1]= when VGA timing is used.
// bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
// bit[4]= RefClock source for PPLL.
// =0: XTLAIN( default mode )
// =1: other external clock source, which is pre-defined
// by VBIOS depend on the feature required.
// bit[7:5]: reserved.
ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
}PIXEL_CLOCK_PARAMETERS_V5;
#define PIXEL_CLOCK_V5_MISC_FORCE_PROG_PPLL 0x01
#define PIXEL_CLOCK_V5_MISC_VGA_MODE 0x02
#define PIXEL_CLOCK_V5_MISC_HDMI_BPP_MASK 0x0c
#define PIXEL_CLOCK_V5_MISC_HDMI_24BPP 0x00
#define PIXEL_CLOCK_V5_MISC_HDMI_30BPP 0x04
#define PIXEL_CLOCK_V5_MISC_HDMI_32BPP 0x08
#define PIXEL_CLOCK_V5_MISC_REF_DIV_SRC 0x10
typedef struct _CRTC_PIXEL_CLOCK_FREQ
{
#if ATOM_BIG_ENDIAN
ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
// drive the pixel clock. not used for DCPLL case.
ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
// 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
#else
ULONG ulPixelClock:24; // target the pixel clock to drive the CRTC timing.
// 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to previous version.
ULONG ucCRTC:8; // ATOM_CRTC1~6, indicate the CRTC controller to
// drive the pixel clock. not used for DCPLL case.
#endif
}CRTC_PIXEL_CLOCK_FREQ;
typedef struct _PIXEL_CLOCK_PARAMETERS_V6
{
union{
CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq; // pixel clock and CRTC id frequency
ULONG ulDispEngClkFreq; // dispclk frequency
};
USHORT usFbDiv; // feedback divider integer part.
UCHAR ucPostDiv; // post divider.
UCHAR ucRefDiv; // Reference divider
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2/ATOM_DCPLL
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
// indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PPLL
// bit[1]= when VGA timing is used.
// bit[3:2]= HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:32bpp
// bit[4]= RefClock source for PPLL.
// =0: XTLAIN( default mode )
// =1: other external clock source, which is pre-defined
// by VBIOS depend on the feature required.
// bit[7:5]: reserved.
ULONG ulFbDivDecFrac; // 20 bit feedback divider decimal fraction part, range from 1~999999 ( 0.000001 to 0.999999 )
}PIXEL_CLOCK_PARAMETERS_V6;
#define PIXEL_CLOCK_V6_MISC_FORCE_PROG_PPLL 0x01
#define PIXEL_CLOCK_V6_MISC_VGA_MODE 0x02
#define PIXEL_CLOCK_V6_MISC_HDMI_BPP_MASK 0x0c
#define PIXEL_CLOCK_V6_MISC_HDMI_24BPP 0x00
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP 0x04
#define PIXEL_CLOCK_V6_MISC_HDMI_36BPP_V6 0x08 //for V6, the correct defintion for 36bpp should be 2 for 36bpp(2:1)
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP 0x08
#define PIXEL_CLOCK_V6_MISC_HDMI_30BPP_V6 0x04 //for V6, the correct defintion for 30bpp should be 1 for 36bpp(5:4)
#define PIXEL_CLOCK_V6_MISC_HDMI_48BPP 0x0c
#define PIXEL_CLOCK_V6_MISC_REF_DIV_SRC 0x10
#define PIXEL_CLOCK_V6_MISC_GEN_DPREFCLK 0x40
#define PIXEL_CLOCK_V6_MISC_DPREFCLK_BYPASS 0x40
typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2
{
PIXEL_CLOCK_PARAMETERS_V3 sDispClkInput;
}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V2;
typedef struct _GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2
{
UCHAR ucStatus;
UCHAR ucRefDivSrc; // =1: reference clock source from XTALIN, =0: source from PCIE ref clock
UCHAR ucReserved[2];
}GET_DISP_PLL_STATUS_OUTPUT_PARAMETERS_V2;
typedef struct _GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3
{
PIXEL_CLOCK_PARAMETERS_V5 sDispClkInput;
}GET_DISP_PLL_STATUS_INPUT_PARAMETERS_V3;
typedef struct _PIXEL_CLOCK_PARAMETERS_V7
{
ULONG ulPixelClock; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
UCHAR ucPpll; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
UCHAR ucTransmitterID; // ASIC encoder id defined in objectId.h,
// indicate which graphic encoder will be used.
UCHAR ucEncoderMode; // Encoder mode:
UCHAR ucMiscInfo; // bit[0]= Force program PLL for pixclk
// bit[1]= Force program PHY PLL only ( internally used by VBIOS only in DP case which PHYPLL is programmed for SYMCLK, not Pixclk )
// bit[5:4]= RefClock source for PPLL.
// =0: XTLAIN( default mode )
// =1: pcie
// =2: GENLK
UCHAR ucCRTC; // ATOM_CRTC1~6, indicate the CRTC controller to
UCHAR ucDeepColorRatio; // HDMI panel bit depth: =0: 24bpp =1:30bpp, =2:36bpp
UCHAR ucReserved[2];
ULONG ulReserved;
}PIXEL_CLOCK_PARAMETERS_V7;
//ucMiscInfo
#define PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL 0x01
#define PIXEL_CLOCK_V7_MISC_PROG_PHYPLL 0x02
#define PIXEL_CLOCK_V7_MISC_YUV420_MODE 0x04
#define PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN 0x08
#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC 0x30
#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN 0x00
#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE 0x10
#define PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK 0x20
//ucDeepColorRatio
#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
#define PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
// SetDCEClockTable input parameter for DCE11.1
typedef struct _SET_DCE_CLOCK_PARAMETERS_V1_1
{
ULONG ulDISPClkFreq; // target DISPCLK frquency in unit of 10kHz, return real DISPCLK frequency. when ucFlag[1]=1, in unit of 100Hz.
UCHAR ucFlag; // bit0=1: DPREFCLK bypass DFS bit0=0: DPREFCLK not bypass DFS
UCHAR ucCrtc; // use when enable DCCG pixel clock ucFlag[1]=1
UCHAR ucPpllId; // use when enable DCCG pixel clock ucFlag[1]=1
UCHAR ucDeepColorRatio; // use when enable DCCG pixel clock ucFlag[1]=1
}SET_DCE_CLOCK_PARAMETERS_V1_1;
typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1
{
SET_DCE_CLOCK_PARAMETERS_V1_1 asParam;
ULONG ulReserved[2];
}SET_DCE_CLOCK_PS_ALLOCATION_V1_1;
//SET_DCE_CLOCK_PARAMETERS_V1_1.ucFlag
#define SET_DCE_CLOCK_FLAG_GEN_DPREFCLK 0x01
#define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01
#define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02
// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above
typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1
{
ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
UCHAR ucDCEClkType; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
UCHAR ucDCEClkSrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
UCHAR ucDCEClkFlag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
UCHAR ucCRTC; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
}SET_DCE_CLOCK_PARAMETERS_V2_1;
//ucDCEClkType
#define DCE_CLOCK_TYPE_DISPCLK 0
#define DCE_CLOCK_TYPE_DPREFCLK 1
#define DCE_CLOCK_TYPE_PIXELCLK 2 // used by VBIOS internally, called by SetPixelClockTable
//ucDCEClkFlag when ucDCEClkType == DPREFCLK
#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK 0x03
#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA 0x00
#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK 0x01
#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE 0x02
#define DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN 0x03
//ucDCEClkFlag when ucDCEClkType == PIXCLK
#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK 0x03
#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS 0x00 //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 0x01 //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 0x02 //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
#define DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 0x03 //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
#define DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE 0x04
typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V2_1
{
SET_DCE_CLOCK_PARAMETERS_V2_1 asParam;
ULONG ulReserved[2];
}SET_DCE_CLOCK_PS_ALLOCATION_V2_1;
/****************************************************************************/
// Structures used by AdjustDisplayPllTable
/****************************************************************************/
typedef struct _ADJUST_DISPLAY_PLL_PARAMETERS
{
USHORT usPixelClock;
UCHAR ucTransmitterID;
UCHAR ucEncodeMode;
union
{
UCHAR ucDVOConfig; //if DVO, need passing link rate and output 12bitlow or 24bit
UCHAR ucConfig; //if none DVO, not defined yet
};
UCHAR ucReserved[3];
}ADJUST_DISPLAY_PLL_PARAMETERS;
#define ADJUST_DISPLAY_CONFIG_SS_ENABLE 0x10
#define ADJUST_DISPLAY_PLL_PS_ALLOCATION ADJUST_DISPLAY_PLL_PARAMETERS
typedef struct _ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3
{
USHORT usPixelClock; // target pixel clock
UCHAR ucTransmitterID; // GPU transmitter id defined in objectid.h
UCHAR ucEncodeMode; // encoder mode: CRT, LVDS, DP, TMDS or HDMI
UCHAR ucDispPllConfig; // display pll configure parameter defined as following DISPPLL_CONFIG_XXXX
UCHAR ucExtTransmitterID; // external encoder id.
UCHAR ucReserved[2];
}ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3;
// usDispPllConfig v1.2 for RoadRunner
#define DISPPLL_CONFIG_DVO_RATE_SEL 0x0001 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_DDR_SPEED 0x0000 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_SDR_SPEED 0x0001 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_OUTPUT_SEL 0x000c // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_LOW12BIT 0x0000 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_UPPER12BIT 0x0004 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_DVO_24BIT 0x0008 // need only when ucTransmitterID = DVO
#define DISPPLL_CONFIG_SS_ENABLE 0x0010 // Only used when ucEncoderMode = DP or LVDS
#define DISPPLL_CONFIG_COHERENT_MODE 0x0020 // Only used when ucEncoderMode = TMDS or HDMI
#define DISPPLL_CONFIG_DUAL_LINK 0x0040 // Only used when ucEncoderMode = TMDS or LVDS
typedef struct _ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3
{
ULONG ulDispPllFreq; // return display PPLL freq which is used to generate the pixclock, and related idclk, symclk etc
UCHAR ucRefDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider and post_div ( if it is not given )
UCHAR ucPostDiv; // if it is none-zero, it is used to be calculated the other ppll parameter fb_divider
UCHAR ucReserved[2];
}ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3;
typedef struct _ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3
{
union
{
ADJUST_DISPLAY_PLL_INPUT_PARAMETERS_V3 sInput;
ADJUST_DISPLAY_PLL_OUTPUT_PARAMETERS_V3 sOutput;
};
} ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3;
/****************************************************************************/
// Structures used by EnableYUVTable
/****************************************************************************/
typedef struct _ENABLE_YUV_PARAMETERS
{
UCHAR ucEnable; // ATOM_ENABLE:Enable YUV or ATOM_DISABLE:Disable YUV (RGB)
UCHAR ucCRTC; // Which CRTC needs this YUV or RGB format
UCHAR ucPadding[2];
}ENABLE_YUV_PARAMETERS;
#define ENABLE_YUV_PS_ALLOCATION ENABLE_YUV_PARAMETERS
/****************************************************************************/
// Structures used by GetMemoryClockTable
/****************************************************************************/
typedef struct _GET_MEMORY_CLOCK_PARAMETERS
{
ULONG ulReturnMemoryClock; // current memory speed in 10KHz unit
} GET_MEMORY_CLOCK_PARAMETERS;
#define GET_MEMORY_CLOCK_PS_ALLOCATION GET_MEMORY_CLOCK_PARAMETERS
/****************************************************************************/
// Structures used by GetEngineClockTable
/****************************************************************************/
typedef struct _GET_ENGINE_CLOCK_PARAMETERS
{
ULONG ulReturnEngineClock; // current engine speed in 10KHz unit
} GET_ENGINE_CLOCK_PARAMETERS;
#define GET_ENGINE_CLOCK_PS_ALLOCATION GET_ENGINE_CLOCK_PARAMETERS
/****************************************************************************/
// Following Structures and constant may be obsolete
/****************************************************************************/
//Maxium 8 bytes,the data read in will be placed in the parameter space.
//Read operaion successeful when the paramter space is non-zero, otherwise read operation failed
typedef struct _READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
USHORT usVRAMAddress; //Adress in Frame Buffer where to pace raw EDID
USHORT usStatus; //When use output: lower byte EDID checksum, high byte hardware status
//WHen use input: lower byte as 'byte to read':currently limited to 128byte or 1byte
UCHAR ucSlaveAddr; //Read from which slave
UCHAR ucLineNumber; //Read from which HW assisted line
}READ_EDID_FROM_HW_I2C_DATA_PARAMETERS;
#define READ_EDID_FROM_HW_I2C_DATA_PS_ALLOCATION READ_EDID_FROM_HW_I2C_DATA_PARAMETERS
#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSDATABYTE 0
#define ATOM_WRITE_I2C_FORMAT_PSOFFSET_PSTWODATABYTES 1
#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_PSOFFSET_IDDATABLOCK 2
#define ATOM_WRITE_I2C_FORMAT_PSCOUNTER_IDOFFSET_PLUS_IDDATABLOCK 3
#define ATOM_WRITE_I2C_FORMAT_IDCOUNTER_IDOFFSET_IDDATABLOCK 4
typedef struct _WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
USHORT usByteOffset; //Write to which byte
//Upper portion of usByteOffset is Format of data
//1bytePS+offsetPS
//2bytesPS+offsetPS
//blockID+offsetPS
//blockID+offsetID
//blockID+counterID+offsetID
UCHAR ucData; //PS data1
UCHAR ucStatus; //Status byte 1=success, 2=failure, Also is used as PS data2
UCHAR ucSlaveAddr; //Write to which slave
UCHAR ucLineNumber; //Write from which HW assisted line
}WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS;
#define WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
typedef struct _SET_UP_HW_I2C_DATA_PARAMETERS
{
USHORT usPrescale; //Ratio between Engine clock and I2C clock
UCHAR ucSlaveAddr; //Write to which slave
UCHAR ucLineNumber; //Write from which HW assisted line
}SET_UP_HW_I2C_DATA_PARAMETERS;
/**************************************************************************/
#define SPEED_FAN_CONTROL_PS_ALLOCATION WRITE_ONE_BYTE_HW_I2C_DATA_PARAMETERS
/****************************************************************************/
// Structures used by PowerConnectorDetectionTable
/****************************************************************************/
typedef struct _POWER_CONNECTOR_DETECTION_PARAMETERS
{
UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
UCHAR ucPwrBehaviorId;
USHORT usPwrBudget; //how much power currently boot to in unit of watt
}POWER_CONNECTOR_DETECTION_PARAMETERS;
typedef struct POWER_CONNECTOR_DETECTION_PS_ALLOCATION
{
UCHAR ucPowerConnectorStatus; //Used for return value 0: detected, 1:not detected
UCHAR ucReserved;
USHORT usPwrBudget; //how much power currently boot to in unit of watt
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
}POWER_CONNECTOR_DETECTION_PS_ALLOCATION;
/****************************LVDS SS Command Table Definitions**********************/
/****************************************************************************/
// Structures used by EnableSpreadSpectrumOnPPLLTable
/****************************************************************************/
typedef struct _ENABLE_LVDS_SS_PARAMETERS
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
UCHAR ucSpreadSpectrumStepSize_Delay; //bits3:2 SS_STEP_SIZE; bit 6:4 SS_DELAY
UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
UCHAR ucPadding[3];
}ENABLE_LVDS_SS_PARAMETERS;
//ucTableFormatRevision=1,ucTableContentRevision=2
typedef struct _ENABLE_LVDS_SS_PARAMETERS_V2
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; //Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
UCHAR ucSpreadSpectrumStep; //
UCHAR ucEnable; //ATOM_ENABLE or ATOM_DISABLE
UCHAR ucSpreadSpectrumDelay;
UCHAR ucSpreadSpectrumRange;
UCHAR ucPadding;
}ENABLE_LVDS_SS_PARAMETERS_V2;
//This new structure is based on ENABLE_LVDS_SS_PARAMETERS but expands to SS on PPLL, so other devices can use SS.
typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; // Bit1=0 Down Spread,=1 Center Spread. Bit1=1 Ext. =0 Int. Others:TBD
UCHAR ucSpreadSpectrumStep; //
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
UCHAR ucSpreadSpectrumDelay;
UCHAR ucSpreadSpectrumRange;
UCHAR ucPpll; // ATOM_PPLL1/ATOM_PPLL2
}ENABLE_SPREAD_SPECTRUM_ON_PPLL;
typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2
{
USHORT usSpreadSpectrumPercentage;
UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
// Bit[1]: 1-Ext. 0-Int.
// Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
// Bits[7:4] reserved
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2;
#define ATOM_PPLL_SS_TYPE_V2_DOWN_SPREAD 0x00
#define ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD 0x01
#define ATOM_PPLL_SS_TYPE_V2_EXT_SPREAD 0x02
#define ATOM_PPLL_SS_TYPE_V2_PPLL_SEL_MASK 0x0c
#define ATOM_PPLL_SS_TYPE_V2_P1PLL 0x00
#define ATOM_PPLL_SS_TYPE_V2_P2PLL 0x04
#define ATOM_PPLL_SS_TYPE_V2_DCPLL 0x08
#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK 0x00FF
#define ATOM_PPLL_SS_AMOUNT_V2_FBDIV_SHIFT 0
#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK 0x0F00
#define ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT 8
// Used by DCE5.0
typedef struct _ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3
{
USHORT usSpreadSpectrumAmountFrac; // SS_AMOUNT_DSFRAC New in DCE5.0
UCHAR ucSpreadSpectrumType; // Bit[0]: 0-Down Spread,1-Center Spread.
// Bit[1]: 1-Ext. 0-Int.
// Bit[3:2]: =0 P1PLL =1 P2PLL =2 DCPLL
// Bits[7:4] reserved
UCHAR ucEnable; // ATOM_ENABLE or ATOM_DISABLE
USHORT usSpreadSpectrumAmount; // Includes SS_AMOUNT_FBDIV[7:0] and SS_AMOUNT_NFRAC_SLIP[11:8]
USHORT usSpreadSpectrumStep; // SS_STEP_SIZE_DSFRAC
}ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3;
#define ATOM_PPLL_SS_TYPE_V3_DOWN_SPREAD 0x00
#define ATOM_PPLL_SS_TYPE_V3_CENTRE_SPREAD 0x01
#define ATOM_PPLL_SS_TYPE_V3_EXT_SPREAD 0x02
#define ATOM_PPLL_SS_TYPE_V3_PPLL_SEL_MASK 0x0c
#define ATOM_PPLL_SS_TYPE_V3_P1PLL 0x00
#define ATOM_PPLL_SS_TYPE_V3_P2PLL 0x04
#define ATOM_PPLL_SS_TYPE_V3_DCPLL 0x08
#define ATOM_PPLL_SS_TYPE_V3_P0PLL ATOM_PPLL_SS_TYPE_V3_DCPLL
#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_MASK 0x00FF
#define ATOM_PPLL_SS_AMOUNT_V3_FBDIV_SHIFT 0
#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_MASK 0x0F00
#define ATOM_PPLL_SS_AMOUNT_V3_NFRAC_SHIFT 8
#define ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION ENABLE_SPREAD_SPECTRUM_ON_PPLL
typedef struct _SET_PIXEL_CLOCK_PS_ALLOCATION
{
PIXEL_CLOCK_PARAMETERS sPCLKInput;
ENABLE_SPREAD_SPECTRUM_ON_PPLL sReserved;//Caller doesn't need to init this portion
}SET_PIXEL_CLOCK_PS_ALLOCATION;
#define ENABLE_VGA_RENDER_PS_ALLOCATION SET_PIXEL_CLOCK_PS_ALLOCATION
/****************************************************************************/
// Structures used by ###
/****************************************************************************/
typedef struct _MEMORY_TRAINING_PARAMETERS
{
ULONG ulTargetMemoryClock; //In 10Khz unit
}MEMORY_TRAINING_PARAMETERS;
#define MEMORY_TRAINING_PS_ALLOCATION MEMORY_TRAINING_PARAMETERS
typedef struct _MEMORY_TRAINING_PARAMETERS_V1_2
{
USHORT usMemTrainingMode;
USHORT usReserved;
}MEMORY_TRAINING_PARAMETERS_V1_2;
//usMemTrainingMode
#define NORMAL_MEMORY_TRAINING_MODE 0
#define ENTER_DRAM_SELFREFRESH_MODE 1
#define EXIT_DRAM_SELFRESH_MODE 2
/****************************LVDS and other encoder command table definitions **********************/
/****************************************************************************/
// Structures used by LVDSEncoderControlTable (Before DEC30)
// LVTMAEncoderControlTable (Before DEC30)
// TMDSAEncoderControlTable (Before DEC30)
/****************************************************************************/
typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucMisc; // bit0=0: Enable single link
// =1: Enable dual link
// Bit1=0: 666RGB
// =1: 888RGB
UCHAR ucAction; // 0: turn off encoder
// 1: setup and turn on encoder
}LVDS_ENCODER_CONTROL_PARAMETERS;
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION LVDS_ENCODER_CONTROL_PARAMETERS
#define TMDS1_ENCODER_CONTROL_PARAMETERS LVDS_ENCODER_CONTROL_PARAMETERS
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION TMDS1_ENCODER_CONTROL_PARAMETERS
#define TMDS2_ENCODER_CONTROL_PARAMETERS TMDS1_ENCODER_CONTROL_PARAMETERS
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION TMDS2_ENCODER_CONTROL_PARAMETERS
//ucTableFormatRevision=1,ucTableContentRevision=2
typedef struct _LVDS_ENCODER_CONTROL_PARAMETERS_V2
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucMisc; // see PANEL_ENCODER_MISC_xx defintions below
UCHAR ucAction; // 0: turn off encoder
// 1: setup and turn on encoder
UCHAR ucTruncate; // bit0=0: Disable truncate
// =1: Enable truncate
// bit4=0: 666RGB
// =1: 888RGB
UCHAR ucSpatial; // bit0=0: Disable spatial dithering
// =1: Enable spatial dithering
// bit4=0: 666RGB
// =1: 888RGB
UCHAR ucTemporal; // bit0=0: Disable temporal dithering
// =1: Enable temporal dithering
// bit4=0: 666RGB
// =1: 888RGB
// bit5=0: Gray level 2
// =1: Gray level 4
UCHAR ucFRC; // bit4=0: 25FRC_SEL pattern E
// =1: 25FRC_SEL pattern F
// bit6:5=0: 50FRC_SEL pattern A
// =1: 50FRC_SEL pattern B
// =2: 50FRC_SEL pattern C
// =3: 50FRC_SEL pattern D
// bit7=0: 75FRC_SEL pattern E
// =1: 75FRC_SEL pattern F
}LVDS_ENCODER_CONTROL_PARAMETERS_V2;
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
#define TMDS1_ENCODER_CONTROL_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
#define TMDS2_ENCODER_CONTROL_PARAMETERS_V2 TMDS1_ENCODER_CONTROL_PARAMETERS_V2
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V2 TMDS2_ENCODER_CONTROL_PARAMETERS_V2
#define LVDS_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V2
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS1_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS1_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS2_ENCODER_CONTROL_PARAMETERS_V3 LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_V3 TMDS2_ENCODER_CONTROL_PARAMETERS_V3
/****************************************************************************/
// Structures used by ###
/****************************************************************************/
typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS
{
UCHAR ucEnable; // Enable or Disable External TMDS encoder
UCHAR ucMisc; // Bit0=0:Enable Single link;=1:Enable Dual link;Bit1 {=0:666RGB, =1:888RGB}
UCHAR ucPadding[2];
}ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS;
typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION
{
ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS sXTmdsEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION;
#define ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 LVDS_ENCODER_CONTROL_PARAMETERS_V2
typedef struct _ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2
{
ENABLE_EXTERNAL_TMDS_ENCODER_PARAMETERS_V2 sXTmdsEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; //Caller doesn't need to init this portion
}ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION_V2;
typedef struct _EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION
{
DIG_ENCODER_CONTROL_PARAMETERS sDigEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
}EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION;
/****************************************************************************/
// Structures used by DVOEncoderControlTable
/****************************************************************************/
//ucTableFormatRevision=1,ucTableContentRevision=3
//ucDVOConfig:
#define DVO_ENCODER_CONFIG_RATE_SEL 0x01
#define DVO_ENCODER_CONFIG_DDR_SPEED 0x00
#define DVO_ENCODER_CONFIG_SDR_SPEED 0x01
#define DVO_ENCODER_CONFIG_OUTPUT_SEL 0x0c
#define DVO_ENCODER_CONFIG_LOW12BIT 0x00
#define DVO_ENCODER_CONFIG_UPPER12BIT 0x04
#define DVO_ENCODER_CONFIG_24BIT 0x08
typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V3
{
USHORT usPixelClock;
UCHAR ucDVOConfig;
UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
UCHAR ucReseved[4];
}DVO_ENCODER_CONTROL_PARAMETERS_V3;
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 DVO_ENCODER_CONTROL_PARAMETERS_V3
typedef struct _DVO_ENCODER_CONTROL_PARAMETERS_V1_4
{
USHORT usPixelClock;
UCHAR ucDVOConfig;
UCHAR ucAction; //ATOM_ENABLE/ATOM_DISABLE/ATOM_HPD_INIT
UCHAR ucBitPerColor; //please refer to definition of PANEL_xBIT_PER_COLOR
UCHAR ucReseved[3];
}DVO_ENCODER_CONTROL_PARAMETERS_V1_4;
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 DVO_ENCODER_CONTROL_PARAMETERS_V1_4
//ucTableFormatRevision=1
//ucTableContentRevision=3 structure is not changed but usMisc add bit 1 as another input for
// bit1=0: non-coherent mode
// =1: coherent mode
//==========================================================================================
//Only change is here next time when changing encoder parameter definitions again!
#define LVDS_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define LVDS_ENCODER_CONTROL_PS_ALLOCATION_LAST LVDS_ENCODER_CONTROL_PARAMETERS_LAST
#define TMDS1_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS1_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS1_ENCODER_CONTROL_PARAMETERS_LAST
#define TMDS2_ENCODER_CONTROL_PARAMETERS_LAST LVDS_ENCODER_CONTROL_PARAMETERS_V3
#define TMDS2_ENCODER_CONTROL_PS_ALLOCATION_LAST TMDS2_ENCODER_CONTROL_PARAMETERS_LAST
#define DVO_ENCODER_CONTROL_PARAMETERS_LAST DVO_ENCODER_CONTROL_PARAMETERS
#define DVO_ENCODER_CONTROL_PS_ALLOCATION_LAST DVO_ENCODER_CONTROL_PS_ALLOCATION
//==========================================================================================
#define PANEL_ENCODER_MISC_DUAL 0x01
#define PANEL_ENCODER_MISC_COHERENT 0x02
#define PANEL_ENCODER_MISC_TMDS_LINKB 0x04
#define PANEL_ENCODER_MISC_HDMI_TYPE 0x08
#define PANEL_ENCODER_ACTION_DISABLE ATOM_DISABLE
#define PANEL_ENCODER_ACTION_ENABLE ATOM_ENABLE
#define PANEL_ENCODER_ACTION_COHERENTSEQ (ATOM_ENABLE+1)
#define PANEL_ENCODER_TRUNCATE_EN 0x01
#define PANEL_ENCODER_TRUNCATE_DEPTH 0x10
#define PANEL_ENCODER_SPATIAL_DITHER_EN 0x01
#define PANEL_ENCODER_SPATIAL_DITHER_DEPTH 0x10
#define PANEL_ENCODER_TEMPORAL_DITHER_EN 0x01
#define PANEL_ENCODER_TEMPORAL_DITHER_DEPTH 0x10
#define PANEL_ENCODER_TEMPORAL_LEVEL_4 0x20
#define PANEL_ENCODER_25FRC_MASK 0x10
#define PANEL_ENCODER_25FRC_E 0x00
#define PANEL_ENCODER_25FRC_F 0x10
#define PANEL_ENCODER_50FRC_MASK 0x60
#define PANEL_ENCODER_50FRC_A 0x00
#define PANEL_ENCODER_50FRC_B 0x20
#define PANEL_ENCODER_50FRC_C 0x40
#define PANEL_ENCODER_50FRC_D 0x60
#define PANEL_ENCODER_75FRC_MASK 0x80
#define PANEL_ENCODER_75FRC_E 0x00
#define PANEL_ENCODER_75FRC_F 0x80
/****************************************************************************/
// Structures used by SetVoltageTable
/****************************************************************************/
#define SET_VOLTAGE_TYPE_ASIC_VDDC 1
#define SET_VOLTAGE_TYPE_ASIC_MVDDC 2
#define SET_VOLTAGE_TYPE_ASIC_MVDDQ 3
#define SET_VOLTAGE_TYPE_ASIC_VDDCI 4
#define SET_VOLTAGE_INIT_MODE 5
#define SET_VOLTAGE_GET_MAX_VOLTAGE 6 //Gets the Max. voltage for the soldered Asic
#define SET_ASIC_VOLTAGE_MODE_ALL_SOURCE 0x1
#define SET_ASIC_VOLTAGE_MODE_SOURCE_A 0x2
#define SET_ASIC_VOLTAGE_MODE_SOURCE_B 0x4
#define SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE 0x0
#define SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL 0x1
#define SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK 0x2
typedef struct _SET_VOLTAGE_PARAMETERS
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
UCHAR ucVoltageMode; // To set all, to set source A or source B or ...
UCHAR ucVoltageIndex; // An index to tell which voltage level
UCHAR ucReserved;
}SET_VOLTAGE_PARAMETERS;
typedef struct _SET_VOLTAGE_PARAMETERS_V2
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ
UCHAR ucVoltageMode; // Not used, maybe use for state machine for differen power mode
USHORT usVoltageLevel; // real voltage level
}SET_VOLTAGE_PARAMETERS_V2;
// used by both SetVoltageTable v1.3 and v1.4
typedef struct _SET_VOLTAGE_PARAMETERS_V1_3
{
UCHAR ucVoltageType; // To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Indicate action: Set voltage level
USHORT usVoltageLevel; // real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. )
}SET_VOLTAGE_PARAMETERS_V1_3;
//ucVoltageType
#define VOLTAGE_TYPE_VDDC 1
#define VOLTAGE_TYPE_MVDDC 2
#define VOLTAGE_TYPE_MVDDQ 3
#define VOLTAGE_TYPE_VDDCI 4
#define VOLTAGE_TYPE_VDDGFX 5
#define VOLTAGE_TYPE_PCC 6
#define VOLTAGE_TYPE_MVPP 7
#define VOLTAGE_TYPE_LEDDPM 8
#define VOLTAGE_TYPE_PCC_MVDD 9
#define VOLTAGE_TYPE_PCIE_VDDC 10
#define VOLTAGE_TYPE_PCIE_VDDR 11
#define VOLTAGE_TYPE_GENERIC_I2C_1 0x11
#define VOLTAGE_TYPE_GENERIC_I2C_2 0x12
#define VOLTAGE_TYPE_GENERIC_I2C_3 0x13
#define VOLTAGE_TYPE_GENERIC_I2C_4 0x14
#define VOLTAGE_TYPE_GENERIC_I2C_5 0x15
#define VOLTAGE_TYPE_GENERIC_I2C_6 0x16
#define VOLTAGE_TYPE_GENERIC_I2C_7 0x17
#define VOLTAGE_TYPE_GENERIC_I2C_8 0x18
#define VOLTAGE_TYPE_GENERIC_I2C_9 0x19
#define VOLTAGE_TYPE_GENERIC_I2C_10 0x1A
//SET_VOLTAGE_PARAMETERS_V3.ucVoltageMode
#define ATOM_SET_VOLTAGE 0 //Set voltage Level
#define ATOM_INIT_VOLTAGE_REGULATOR 3 //Init Regulator
#define ATOM_SET_VOLTAGE_PHASE 4 //Set Vregulator Phase, only for SVID/PVID regulator
#define ATOM_GET_MAX_VOLTAGE 6 //Get Max Voltage, not used from SetVoltageTable v1.3
#define ATOM_GET_VOLTAGE_LEVEL 6 //Get Voltage level from vitual voltage ID, not used for SetVoltage v1.4
#define ATOM_GET_LEAKAGE_ID 8 //Get Leakage Voltage Id ( starting from SMU7x IP ), SetVoltage v1.4
// define vitual voltage id in usVoltageLevel
#define ATOM_VIRTUAL_VOLTAGE_ID0 0xff01
#define ATOM_VIRTUAL_VOLTAGE_ID1 0xff02
#define ATOM_VIRTUAL_VOLTAGE_ID2 0xff03
#define ATOM_VIRTUAL_VOLTAGE_ID3 0xff04
#define ATOM_VIRTUAL_VOLTAGE_ID4 0xff05
#define ATOM_VIRTUAL_VOLTAGE_ID5 0xff06
#define ATOM_VIRTUAL_VOLTAGE_ID6 0xff07
#define ATOM_VIRTUAL_VOLTAGE_ID7 0xff08
typedef struct _SET_VOLTAGE_PS_ALLOCATION
{
SET_VOLTAGE_PARAMETERS sASICSetVoltage;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved;
}SET_VOLTAGE_PS_ALLOCATION;
// New Added from SI for GetVoltageInfoTable, input parameter structure
typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulReserved;
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_1;
// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_VID
typedef struct _GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
{
ULONG ulVotlageGpioState;
ULONG ulVoltageGPioMask;
}GET_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
// New Added from SI for GetVoltageInfoTable, output parameter structure when ucVotlageMode == ATOM_GET_VOLTAGE_STATEx_LEAKAGE_VID
typedef struct _GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1
{
USHORT usVoltageLevel;
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
ULONG ulReseved;
}GET_LEAKAGE_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_1;
// GetVoltageInfo v1.1 ucVoltageMode
#define ATOM_GET_VOLTAGE_VID 0x00
#define ATOM_GET_VOTLAGE_INIT_SEQ 0x03
#define ATOM_GET_VOLTTAGE_PHASE_PHASE_VID 0x04
#define ATOM_GET_VOLTAGE_SVID2 0x07 //Get SVI2 Regulator Info
// for SI, this state map to 0xff02 voltage state in Power Play table, which is power boost state
#define ATOM_GET_VOLTAGE_STATE0_LEAKAGE_VID 0x10
// for SI, this state map to 0xff01 voltage state in Power Play table, which is performance state
#define ATOM_GET_VOLTAGE_STATE1_LEAKAGE_VID 0x11
#define ATOM_GET_VOLTAGE_STATE2_LEAKAGE_VID 0x12
#define ATOM_GET_VOLTAGE_STATE3_LEAKAGE_VID 0x13
// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2;
// New in GetVoltageInfo v1.2 ucVoltageMode
#define ATOM_GET_VOLTAGE_EVV_VOLTAGE 0x09
// New Added from CI Hawaii for EVV feature
typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2
{
USHORT usVoltageLevel; // real voltage level in unit of mv
USHORT usVoltageId; // Voltage Id programmed in Voltage Regulator
USHORT usTDP_Current; // TDP_Current in unit of 0.01A
USHORT usTDP_Power; // TDP_Current in unit of 0.1W
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2;
// New Added from CI Hawaii for GetVoltageInfoTable, input parameter structure
typedef struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3
{
UCHAR ucVoltageType; // Input: To tell which voltage to set up, VDDC/MVDDC/MVDDQ/VDDCI
UCHAR ucVoltageMode; // Input: Indicate action: Get voltage info
USHORT usVoltageLevel; // Input: real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) or Leakage Id
ULONG ulSCLKFreq; // Input: when ucVoltageMode= ATOM_GET_VOLTAGE_EVV_VOLTAGE, DPM state SCLK frequency, Define in PPTable SCLK/Voltage dependence table
ULONG ulReserved[3];
}GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_3;
// New Added from CI Hawaii for EVV feature
typedef struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3
{
ULONG ulVoltageLevel; // real voltage level in unit of 0.01mv
ULONG ulReserved[4];
}GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_3;
/****************************************************************************/
// Structures used by GetSMUClockInfo
/****************************************************************************/
typedef struct _GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1
{
ULONG ulDfsPllOutputFreq:24;
ULONG ucDfsDivider:8;
}GET_SMU_CLOCK_INFO_INPUT_PARAMETER_V2_1;
typedef struct _GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1
{
ULONG ulDfsOutputFreq;
}GET_SMU_CLOCK_INFO_OUTPUT_PARAMETER_V2_1;
/****************************************************************************/
// Structures used by TVEncoderControlTable
/****************************************************************************/
typedef struct _TV_ENCODER_CONTROL_PARAMETERS
{
USHORT usPixelClock; // in 10KHz; for bios convenient
UCHAR ucTvStandard; // See definition "ATOM_TV_NTSC ..."
UCHAR ucAction; // 0: turn off encoder
// 1: setup and turn on encoder
}TV_ENCODER_CONTROL_PARAMETERS;
typedef struct _TV_ENCODER_CONTROL_PS_ALLOCATION
{
TV_ENCODER_CONTROL_PARAMETERS sTVEncoder;
WRITE_ONE_BYTE_HW_I2C_DATA_PS_ALLOCATION sReserved; // Don't set this one
}TV_ENCODER_CONTROL_PS_ALLOCATION;
//==============================Data Table Portion====================================
/****************************************************************************/
// Structure used in Data.mtb
/****************************************************************************/
typedef struct _ATOM_MASTER_LIST_OF_DATA_TABLES
{
USHORT UtilityPipeLine; // Offest for the utility to get parser info,Don't change this position!
USHORT MultimediaCapabilityInfo; // Only used by MM Lib,latest version 1.1, not configuable from Bios, need to include the table to build Bios
USHORT MultimediaConfigInfo; // Only used by MM Lib,latest version 2.1, not configuable from Bios, need to include the table to build Bios
USHORT StandardVESA_Timing; // Only used by Bios
USHORT FirmwareInfo; // Shared by various SW components,latest version 1.4
USHORT PaletteData; // Only used by BIOS
USHORT LCD_Info; // Shared by various SW components,latest version 1.3, was called LVDS_Info
USHORT DIGTransmitterInfo; // Internal used by VBIOS only version 3.1
USHORT SMU_Info; // Shared by various SW components,latest version 1.1
USHORT SupportedDevicesInfo; // Will be obsolete from R600
USHORT GPIO_I2C_Info; // Shared by various SW components,latest version 1.2 will be used from R600
USHORT VRAM_UsageByFirmware; // Shared by various SW components,latest version 1.3 will be used from R600
USHORT GPIO_Pin_LUT; // Shared by various SW components,latest version 1.1
USHORT VESA_ToInternalModeLUT; // Only used by Bios
USHORT GFX_Info; // Shared by various SW components,latest version 2.1 will be used from R600
USHORT PowerPlayInfo; // Shared by various SW components,latest version 2.1,new design from R600
USHORT GPUVirtualizationInfo; // Will be obsolete from R600
USHORT SaveRestoreInfo; // Only used by Bios
USHORT PPLL_SS_Info; // Shared by various SW components,latest version 1.2, used to call SS_Info, change to new name because of int ASIC SS info
USHORT OemInfo; // Defined and used by external SW, should be obsolete soon
USHORT XTMDS_Info; // Will be obsolete from R600
USHORT MclkSS_Info; // Shared by various SW components,latest version 1.1, only enabled when ext SS chip is used
USHORT Object_Header; // Shared by various SW components,latest version 1.1
USHORT IndirectIOAccess; // Only used by Bios,this table position can't change at all!!
USHORT MC_InitParameter; // Only used by command table
USHORT ASIC_VDDC_Info; // Will be obsolete from R600
USHORT ASIC_InternalSS_Info; // New tabel name from R600, used to be called "ASIC_MVDDC_Info"
USHORT TV_VideoMode; // Only used by command table
USHORT VRAM_Info; // Only used by command table, latest version 1.3
USHORT MemoryTrainingInfo; // Used for VBIOS and Diag utility for memory training purpose since R600. the new table rev start from 2.1
USHORT IntegratedSystemInfo; // Shared by various SW components
USHORT ASIC_ProfilingInfo; // New table name from R600, used to be called "ASIC_VDDCI_Info" for pre-R600
USHORT VoltageObjectInfo; // Shared by various SW components, latest version 1.1
USHORT PowerSourceInfo; // Shared by various SW components, latest versoin 1.1
USHORT ServiceInfo;
}ATOM_MASTER_LIST_OF_DATA_TABLES;
typedef struct _ATOM_MASTER_DATA_TABLE
{
ATOM_COMMON_TABLE_HEADER sHeader;
ATOM_MASTER_LIST_OF_DATA_TABLES ListOfDataTables;
}ATOM_MASTER_DATA_TABLE;
// For backward compatible
#define LVDS_Info LCD_Info
#define DAC_Info PaletteData
#define TMDS_Info DIGTransmitterInfo
#define CompassionateData GPUVirtualizationInfo
#define AnalogTV_Info SMU_Info
#define ComponentVideoInfo GFX_Info
/****************************************************************************/
// Structure used in MultimediaCapabilityInfoTable
/****************************************************************************/
typedef struct _ATOM_MULTIMEDIA_CAPABILITY_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulSignature; // HW info table signature string "$ATI"
UCHAR ucI2C_Type; // I2C type (normal GP_IO, ImpactTV GP_IO, Dedicated I2C pin, etc)
UCHAR ucTV_OutInfo; // Type of TV out supported (3:0) and video out crystal frequency (6:4) and TV data port (7)
UCHAR ucVideoPortInfo; // Provides the video port capabilities
UCHAR ucHostPortInfo; // Provides host port configuration information
}ATOM_MULTIMEDIA_CAPABILITY_INFO;
/****************************************************************************/
// Structure used in MultimediaConfigInfoTable
/****************************************************************************/
typedef struct _ATOM_MULTIMEDIA_CONFIG_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulSignature; // MM info table signature sting "$MMT"
UCHAR ucTunerInfo; // Type of tuner installed on the adapter (4:0) and video input for tuner (7:5)
UCHAR ucAudioChipInfo; // List the audio chip type (3:0) product type (4) and OEM revision (7:5)
UCHAR ucProductID; // Defines as OEM ID or ATI board ID dependent on product type setting
UCHAR ucMiscInfo1; // Tuner voltage (1:0) HW teletext support (3:2) FM audio decoder (5:4) reserved (6) audio scrambling (7)
UCHAR ucMiscInfo2; // I2S input config (0) I2S output config (1) I2S Audio Chip (4:2) SPDIF Output Config (5) reserved (7:6)
UCHAR ucMiscInfo3; // Video Decoder Type (3:0) Video In Standard/Crystal (7:4)
UCHAR ucMiscInfo4; // Video Decoder Host Config (2:0) reserved (7:3)
UCHAR ucVideoInput0Info;// Video Input 0 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput1Info;// Video Input 1 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput2Info;// Video Input 2 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput3Info;// Video Input 3 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
UCHAR ucVideoInput4Info;// Video Input 4 Type (1:0) F/B setting (2) physical connector ID (5:3) reserved (7:6)
}ATOM_MULTIMEDIA_CONFIG_INFO;
/****************************************************************************/
// Structures used in FirmwareInfoTable
/****************************************************************************/
// usBIOSCapability Defintion:
// Bit 0 = 0: Bios image is not Posted, =1:Bios image is Posted;
// Bit 1 = 0: Dual CRTC is not supported, =1: Dual CRTC is supported;
// Bit 2 = 0: Extended Desktop is not supported, =1: Extended Desktop is supported;
// Others: Reserved
#define ATOM_BIOS_INFO_ATOM_FIRMWARE_POSTED 0x0001
#define ATOM_BIOS_INFO_DUAL_CRTC_SUPPORT 0x0002
#define ATOM_BIOS_INFO_EXTENDED_DESKTOP_SUPPORT 0x0004
#define ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT 0x0008 // (valid from v1.1 ~v1.4):=1: memclk SS enable, =0 memclk SS disable.
#define ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT 0x0010 // (valid from v1.1 ~v1.4):=1: engclk SS enable, =0 engclk SS disable.
#define ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU 0x0020
#define ATOM_BIOS_INFO_WMI_SUPPORT 0x0040
#define ATOM_BIOS_INFO_PPMODE_ASSIGNGED_BY_SYSTEM 0x0080
#define ATOM_BIOS_INFO_HYPERMEMORY_SUPPORT 0x0100
#define ATOM_BIOS_INFO_HYPERMEMORY_SIZE_MASK 0x1E00
#define ATOM_BIOS_INFO_VPOST_WITHOUT_FIRST_MODE_SET 0x2000
#define ATOM_BIOS_INFO_BIOS_SCRATCH6_SCL2_REDEFINE 0x4000
#define ATOM_BIOS_INFO_MEMORY_CLOCK_EXT_SS_SUPPORT 0x0008 // (valid from v2.1 ): =1: memclk ss enable with external ss chip
#define ATOM_BIOS_INFO_ENGINE_CLOCK_EXT_SS_SUPPORT 0x0010 // (valid from v2.1 ): =1: engclk ss enable with external ss chip
#ifndef _H2INC
//Please don't add or expand this bitfield structure below, this one will retire soon.!
typedef struct _ATOM_FIRMWARE_CAPABILITY
{
#if ATOM_BIG_ENDIAN
USHORT Reserved:1;
USHORT SCL2Redefined:1;
USHORT PostWithoutModeSet:1;
USHORT HyperMemory_Size:4;
USHORT HyperMemory_Support:1;
USHORT PPMode_Assigned:1;
USHORT WMI_SUPPORT:1;
USHORT GPUControlsBL:1;
USHORT EngineClockSS_Support:1;
USHORT MemoryClockSS_Support:1;
USHORT ExtendedDesktopSupport:1;
USHORT DualCRTC_Support:1;
USHORT FirmwarePosted:1;
#else
USHORT FirmwarePosted:1;
USHORT DualCRTC_Support:1;
USHORT ExtendedDesktopSupport:1;
USHORT MemoryClockSS_Support:1;
USHORT EngineClockSS_Support:1;
USHORT GPUControlsBL:1;
USHORT WMI_SUPPORT:1;
USHORT PPMode_Assigned:1;
USHORT HyperMemory_Support:1;
USHORT HyperMemory_Size:4;
USHORT PostWithoutModeSet:1;
USHORT SCL2Redefined:1;
USHORT Reserved:1;
#endif
}ATOM_FIRMWARE_CAPABILITY;
typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
{
ATOM_FIRMWARE_CAPABILITY sbfAccess;
USHORT susAccess;
}ATOM_FIRMWARE_CAPABILITY_ACCESS;
#else
typedef union _ATOM_FIRMWARE_CAPABILITY_ACCESS
{
USHORT susAccess;
}ATOM_FIRMWARE_CAPABILITY_ACCESS;
#endif
typedef struct _ATOM_FIRMWARE_INFO
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucPadding[3]; //Don't use them
ULONG aulReservedForBIOS[3]; //Don't use them
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit, the definitions above can't change!!!
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO;
typedef struct _ATOM_FIRMWARE_INFO_V1_2
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
UCHAR ucPadding[2]; //Don't use them
ULONG aulReservedForBIOS[2]; //Don't use them
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_2;
typedef struct _ATOM_FIRMWARE_INFO_V1_3
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
UCHAR ucPadding[2]; //Don't use them
ULONG aulReservedForBIOS; //Don't use them
ULONG ul3DAccelerationEngineClock;//In 10Khz unit
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit
USHORT usMinEngineClockPLL_Input; //In 10Khz unit
USHORT usMaxEngineClockPLL_Input; //In 10Khz unit
USHORT usMinEngineClockPLL_Output; //In 10Khz unit
USHORT usMinMemoryClockPLL_Input; //In 10Khz unit
USHORT usMaxMemoryClockPLL_Input; //In 10Khz unit
USHORT usMinMemoryClockPLL_Output; //In 10Khz unit
USHORT usMaxPixelClock; //In 10Khz unit, Max. Pclk
USHORT usMinPixelClockPLL_Input; //In 10Khz unit
USHORT usMaxPixelClockPLL_Input; //In 10Khz unit
USHORT usMinPixelClockPLL_Output; //In 10Khz unit - lower 16bit of ulMinPixelClockPLL_Output
ATOM_FIRMWARE_CAPABILITY_ACCESS usFirmwareCapability;
USHORT usReferenceClock; //In 10Khz unit
USHORT usPM_RTS_Location; //RTS PM4 starting location in ROM in 1Kb unit
UCHAR ucPM_RTS_StreamSize; //RTS PM4 packets in Kb unit
UCHAR ucDesign_ID; //Indicate what is the board design
UCHAR ucMemoryModule_ID; //Indicate what is the board design
}ATOM_FIRMWARE_INFO_V1_3;
typedef struct _ATOM_FIRMWARE_INFO_V1_4
{
ATOM_COMMON_TABLE_HEADER sHeader;
ULONG ulFirmwareRevision;
ULONG ulDefaultEngineClock; //In 10Khz unit
ULONG ulDefaultMemoryClock; //In 10Khz unit
ULONG ulDriverTargetEngineClock; //In 10Khz unit
ULONG ulDriverTargetMemoryClock; //In 10Khz unit
ULONG ulMaxEngineClockPLL_Output; //In 10Khz unit
ULONG ulMaxMemoryClockPLL_Output; //In 10Khz unit
ULONG ulMaxPixelClockPLL_Output; //In 10Khz unit
ULONG ulASICMaxEngineClock; //In 10Khz unit
ULONG ulASICMaxMemoryClock; //In 10Khz unit
UCHAR ucASICMaxTemperature;
UCHAR ucMinAllowedBL_Level;
USHORT usBootUpVDDCVoltage; //In MV unit
USHORT usLcdMinPixelClockPLL_Output; // In MHz unit
USHORT usLcdMaxPixelClockPLL_Output; // In MHz unit
ULONG ul3DAccelerationEngineClock;//In 10Khz unit
ULONG ulMinPixelClockPLL_Output; //In 10Khz unit