blob: 233eb7f36c1da19e76689d430f83e4cc12e1fc9d [file] [log] [blame]
/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/fb.h>
#include "linux/delay.h"
#include "pp_acpi.h"
#include "hwmgr.h"
#include <atombios.h>
#include "tonga_hwmgr.h"
#include "pptable.h"
#include "processpptables.h"
#include "tonga_processpptables.h"
#include "tonga_pptable.h"
#include "pp_debug.h"
#include "tonga_ppsmc.h"
#include "cgs_common.h"
#include "pppcielanes.h"
#include "tonga_dyn_defaults.h"
#include "smumgr.h"
#include "tonga_smumgr.h"
#include "tonga_clockpowergating.h"
#include "tonga_thermal.h"
#include "smu/smu_7_1_2_d.h"
#include "smu/smu_7_1_2_sh_mask.h"
#include "gmc/gmc_8_1_d.h"
#include "gmc/gmc_8_1_sh_mask.h"
#include "bif/bif_5_0_d.h"
#include "bif/bif_5_0_sh_mask.h"
#include "dce/dce_10_0_d.h"
#include "dce/dce_10_0_sh_mask.h"
#include "cgs_linux.h"
#include "eventmgr.h"
#include "amd_pcie_helpers.h"
#define MC_CG_ARB_FREQ_F0 0x0a
#define MC_CG_ARB_FREQ_F1 0x0b
#define MC_CG_ARB_FREQ_F2 0x0c
#define MC_CG_ARB_FREQ_F3 0x0d
#define MC_CG_SEQ_DRAMCONF_S0 0x05
#define MC_CG_SEQ_DRAMCONF_S1 0x06
#define MC_CG_SEQ_YCLK_SUSPEND 0x04
#define MC_CG_SEQ_YCLK_RESUME 0x0a
#define PCIE_BUS_CLK 10000
#define TCLK (PCIE_BUS_CLK / 10)
#define SMC_RAM_END 0x40000
#define SMC_CG_IND_START 0xc0030000
#define SMC_CG_IND_END 0xc0040000 /* First byte after SMC_CG_IND*/
#define VOLTAGE_SCALE 4
#define VOLTAGE_VID_OFFSET_SCALE1 625
#define VOLTAGE_VID_OFFSET_SCALE2 100
#define VDDC_VDDCI_DELTA 200
#define VDDC_VDDGFX_DELTA 300
#define MC_SEQ_MISC0_GDDR5_SHIFT 28
#define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000
#define MC_SEQ_MISC0_GDDR5_VALUE 5
typedef uint32_t PECI_RegistryValue;
/* [2.5%,~2.5%] Clock stretched is multiple of 2.5% vs not and [Fmin, Fmax, LDO_REFSEL, USE_FOR_LOW_FREQ] */
static const uint16_t PP_ClockStretcherLookupTable[2][4] = {
{600, 1050, 3, 0},
{600, 1050, 6, 1} };
/* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */
static const uint32_t PP_ClockStretcherDDTTable[2][4][4] = {
{ {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} },
{ {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } };
/* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */
static const uint8_t PP_ClockStretchAmountConversion[2][6] = {
{0, 1, 3, 2, 4, 5},
{0, 2, 4, 5, 6, 5} };
/* Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */
enum DPM_EVENT_SRC {
DPM_EVENT_SRC_ANALOG = 0, /* Internal analog trip point */
DPM_EVENT_SRC_EXTERNAL = 1, /* External (GPIO 17) signal */
DPM_EVENT_SRC_DIGITAL = 2, /* Internal digital trip point (DIG_THERM_DPM) */
DPM_EVENT_SRC_ANALOG_OR_EXTERNAL = 3, /* Internal analog or external */
DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 /* Internal digital or external */
};
typedef enum DPM_EVENT_SRC DPM_EVENT_SRC;
static const unsigned long PhwTonga_Magic = (unsigned long)(PHM_VIslands_Magic);
struct tonga_power_state *cast_phw_tonga_power_state(
struct pp_hw_power_state *hw_ps)
{
if (hw_ps == NULL)
return NULL;
PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL);
return (struct tonga_power_state *)hw_ps;
}
const struct tonga_power_state *cast_const_phw_tonga_power_state(
const struct pp_hw_power_state *hw_ps)
{
if (hw_ps == NULL)
return NULL;
PP_ASSERT_WITH_CODE((PhwTonga_Magic == hw_ps->magic),
"Invalid Powerstate Type!",
return NULL);
return (const struct tonga_power_state *)hw_ps;
}
int tonga_add_voltage(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *look_up_table,
phm_ppt_v1_voltage_lookup_record *record)
{
uint32_t i;
PP_ASSERT_WITH_CODE((NULL != look_up_table),
"Lookup Table empty.", return -1;);
PP_ASSERT_WITH_CODE((0 != look_up_table->count),
"Lookup Table empty.", return -1;);
PP_ASSERT_WITH_CODE((SMU72_MAX_LEVELS_VDDGFX >= look_up_table->count),
"Lookup Table is full.", return -1;);
/* This is to avoid entering duplicate calculated records. */
for (i = 0; i < look_up_table->count; i++) {
if (look_up_table->entries[i].us_vdd == record->us_vdd) {
if (look_up_table->entries[i].us_calculated == 1)
return 0;
else
break;
}
}
look_up_table->entries[i].us_calculated = 1;
look_up_table->entries[i].us_vdd = record->us_vdd;
look_up_table->entries[i].us_cac_low = record->us_cac_low;
look_up_table->entries[i].us_cac_mid = record->us_cac_mid;
look_up_table->entries[i].us_cac_high = record->us_cac_high;
/* Only increment the count when we're appending, not replacing duplicate entry. */
if (i == look_up_table->count)
look_up_table->count++;
return 0;
}
int tonga_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display)
{
PPSMC_Msg msg = has_display? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay;
return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1;
}
uint8_t tonga_get_voltage_id(pp_atomctrl_voltage_table *voltage_table,
uint32_t voltage)
{
uint8_t count = (uint8_t) (voltage_table->count);
uint8_t i = 0;
PP_ASSERT_WITH_CODE((NULL != voltage_table),
"Voltage Table empty.", return 0;);
PP_ASSERT_WITH_CODE((0 != count),
"Voltage Table empty.", return 0;);
for (i = 0; i < count; i++) {
/* find first voltage bigger than requested */
if (voltage_table->entries[i].value >= voltage)
return i;
}
/* voltage is bigger than max voltage in the table */
return i - 1;
}
/**
* @brief PhwTonga_GetVoltageOrder
* Returns index of requested voltage record in lookup(table)
* @param hwmgr - pointer to hardware manager
* @param lookupTable - lookup list to search in
* @param voltage - voltage to look for
* @return 0 on success
*/
uint8_t tonga_get_voltage_index(phm_ppt_v1_voltage_lookup_table *look_up_table,
uint16_t voltage)
{
uint8_t count = (uint8_t) (look_up_table->count);
uint8_t i;
PP_ASSERT_WITH_CODE((NULL != look_up_table), "Lookup Table empty.", return 0;);
PP_ASSERT_WITH_CODE((0 != count), "Lookup Table empty.", return 0;);
for (i = 0; i < count; i++) {
/* find first voltage equal or bigger than requested */
if (look_up_table->entries[i].us_vdd >= voltage)
return i;
}
/* voltage is bigger than max voltage in the table */
return i-1;
}
bool tonga_is_dpm_running(struct pp_hwmgr *hwmgr)
{
/*
* We return the status of Voltage Control instead of checking SCLK/MCLK DPM
* because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
* whereas voltage control is a fundemental change that will not be disabled
*/
return (0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC,
FEATURE_STATUS, VOLTAGE_CONTROLLER_ON) ? 1 : 0);
}
/**
* Re-generate the DPM level mask value
* @param hwmgr the address of the hardware manager
*/
static uint32_t tonga_get_dpm_level_enable_mask_value(
struct tonga_single_dpm_table * dpm_table)
{
uint32_t i;
uint32_t mask_value = 0;
for (i = dpm_table->count; i > 0; i--) {
mask_value = mask_value << 1;
if (dpm_table->dpm_levels[i-1].enabled)
mask_value |= 0x1;
else
mask_value &= 0xFFFFFFFE;
}
return mask_value;
}
/**
* Retrieve DPM default values from registry (if available)
*
* @param hwmgr the address of the powerplay hardware manager.
*/
void tonga_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
phw_tonga_ulv_parm *ulv = &(data->ulv);
uint32_t tmp;
ulv->ch_ulv_parameter = PPTONGA_CGULVPARAMETER_DFLT;
data->voting_rights_clients0 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT0;
data->voting_rights_clients1 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT1;
data->voting_rights_clients2 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT2;
data->voting_rights_clients3 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT3;
data->voting_rights_clients4 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT4;
data->voting_rights_clients5 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT5;
data->voting_rights_clients6 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT6;
data->voting_rights_clients7 = PPTONGA_VOTINGRIGHTSCLIENTS_DFLT7;
data->static_screen_threshold_unit = PPTONGA_STATICSCREENTHRESHOLDUNIT_DFLT;
data->static_screen_threshold = PPTONGA_STATICSCREENTHRESHOLD_DFLT;
phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ABM);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_NonABMSupportInPPLib);
tmp = 0;
if (tmp == 0)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicACTiming);
tmp = 0;
if (0 != tmp)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableMemoryTransition);
data->mclk_strobe_mode_threshold = 40000;
data->mclk_stutter_mode_threshold = 30000;
data->mclk_edc_enable_threshold = 40000;
data->mclk_edc_wr_enable_threshold = 40000;
tmp = 0;
if (tmp != 0)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DisableMCLS);
data->pcie_gen_performance.max = PP_PCIEGen1;
data->pcie_gen_performance.min = PP_PCIEGen3;
data->pcie_gen_power_saving.max = PP_PCIEGen1;
data->pcie_gen_power_saving.min = PP_PCIEGen3;
data->pcie_lane_performance.max = 0;
data->pcie_lane_performance.min = 16;
data->pcie_lane_power_saving.max = 0;
data->pcie_lane_power_saving.min = 16;
tmp = 0;
if (tmp)
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification);
phm_cap_set(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_DynamicUVDState);
}
int tonga_update_sclk_threshold(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
int result = 0;
uint32_t low_sclk_interrupt_threshold = 0;
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkThrottleLowNotification)
&& (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold);
result = tonga_copy_bytes_to_smc(
hwmgr->smumgr,
data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable,
LowSclkInterruptThreshold),
(uint8_t *)&low_sclk_interrupt_threshold,
sizeof(uint32_t),
data->sram_end
);
}
return result;
}
/**
* Find SCLK value that is associated with specified virtual_voltage_Id.
*
* @param hwmgr the address of the powerplay hardware manager.
* @param virtual_voltage_Id voltageId to look for.
* @param sclk output value .
* @return always 0 if success and 2 if association not found
*/
static int tonga_get_sclk_for_voltage_evv(struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *lookup_table,
uint16_t virtual_voltage_id, uint32_t *sclk)
{
uint8_t entryId;
uint8_t voltageId;
struct phm_ppt_v1_information *pptable_info =
(struct phm_ppt_v1_information *)(hwmgr->pptable);
PP_ASSERT_WITH_CODE(lookup_table->count != 0, "Lookup table is empty", return -1);
/* search for leakage voltage ID 0xff01 ~ 0xff08 and sckl */
for (entryId = 0; entryId < pptable_info->vdd_dep_on_sclk->count; entryId++) {
voltageId = pptable_info->vdd_dep_on_sclk->entries[entryId].vddInd;
if (lookup_table->entries[voltageId].us_vdd == virtual_voltage_id)
break;
}
PP_ASSERT_WITH_CODE(entryId < pptable_info->vdd_dep_on_sclk->count,
"Can't find requested voltage id in vdd_dep_on_sclk table!",
return -1;
);
*sclk = pptable_info->vdd_dep_on_sclk->entries[entryId].clk;
return 0;
}
/**
* Get Leakage VDDC based on leakage ID.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return 2 if vddgfx returned is greater than 2V or if BIOS
*/
int tonga_get_evv_voltage(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_clock_voltage_dependency_table *sclk_table = pptable_info->vdd_dep_on_sclk;
uint16_t virtual_voltage_id;
uint16_t vddc = 0;
uint16_t vddgfx = 0;
uint16_t i, j;
uint32_t sclk = 0;
/* retrieve voltage for leakage ID (0xff01 + i) */
for (i = 0; i < TONGA_MAX_LEAKAGE_COUNT; i++) {
virtual_voltage_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i;
/* in split mode we should have only vddgfx EVV leakages */
if (data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) {
if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
pptable_info->vddgfx_lookup_table, virtual_voltage_id, &sclk)) {
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_ClockStretcher)) {
for (j = 1; j < sclk_table->count; j++) {
if (sclk_table->entries[j].clk == sclk &&
sclk_table->entries[j].cks_enable == 0) {
sclk += 5000;
break;
}
}
}
if (0 == atomctrl_get_voltage_evv_on_sclk
(hwmgr, VOLTAGE_TYPE_VDDGFX, sclk,
virtual_voltage_id, &vddgfx)) {
/* need to make sure vddgfx is less than 2v or else, it could burn the ASIC. */
PP_ASSERT_WITH_CODE((vddgfx < 2000 && vddgfx != 0), "Invalid VDDGFX value!", return -1);
/* the voltage should not be zero nor equal to leakage ID */
if (vddgfx != 0 && vddgfx != virtual_voltage_id) {
data->vddcgfx_leakage.actual_voltage[data->vddcgfx_leakage.count] = vddgfx;
data->vddcgfx_leakage.leakage_id[data->vddcgfx_leakage.count] = virtual_voltage_id;
data->vddcgfx_leakage.count++;
}
} else {
printk("Error retrieving EVV voltage value!\n");
}
}
} else {
/* in merged mode we have only vddc EVV leakages */
if (0 == tonga_get_sclk_for_voltage_evv(hwmgr,
pptable_info->vddc_lookup_table,
virtual_voltage_id, &sclk)) {
if (0 == atomctrl_get_voltage_evv_on_sclk
(hwmgr, VOLTAGE_TYPE_VDDC, sclk,
virtual_voltage_id, &vddc)) {
/* need to make sure vddc is less than 2v or else, it could burn the ASIC. */
PP_ASSERT_WITH_CODE(vddc < 2000, "Invalid VDDC value!", return -1);
/* the voltage should not be zero nor equal to leakage ID */
if (vddc != 0 && vddc != virtual_voltage_id) {
data->vddc_leakage.actual_voltage[data->vddc_leakage.count] = vddc;
data->vddc_leakage.leakage_id[data->vddc_leakage.count] = virtual_voltage_id;
data->vddc_leakage.count++;
}
} else {
printk("Error retrieving EVV voltage value!\n");
}
}
}
}
return 0;
}
int tonga_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
/* enable SCLK dpm */
if (0 == data->sclk_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_DPM_Enable)),
"Failed to enable SCLK DPM during DPM Start Function!",
return -1);
}
/* enable MCLK dpm */
if (0 == data->mclk_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_Enable)),
"Failed to enable MCLK DPM during DPM Start Function!",
return -1);
PHM_WRITE_FIELD(hwmgr->device, MC_SEQ_CNTL_3, CAC_EN, 0x1);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_MC0_CNTL, 0x05);/* CH0,1 read */
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_MC1_CNTL, 0x05);/* CH2,3 read */
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_CPL_CNTL, 0x100005);/*Read */
udelay(10);
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_MC0_CNTL, 0x400005);/* CH0,1 write */
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_MC1_CNTL, 0x400005);/* CH2,3 write */
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,
ixLCAC_CPL_CNTL, 0x500005);/* write */
}
return 0;
}
int tonga_start_dpm(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
/* enable general power management */
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 1);
/* enable sclk deep sleep */
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 1);
/* prepare for PCIE DPM */
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start +
offsetof(SMU72_SoftRegisters, VoltageChangeTimeout), 0x1000);
PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__PCIE, SWRST_COMMAND_1, RESETLC, 0x0);
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_Voltage_Cntl_Enable)),
"Failed to enable voltage DPM during DPM Start Function!",
return -1);
if (0 != tonga_enable_sclk_mclk_dpm(hwmgr)) {
PP_ASSERT_WITH_CODE(0, "Failed to enable Sclk DPM and Mclk DPM!", return -1);
}
/* enable PCIE dpm */
if (0 == data->pcie_dpm_key_disabled) {
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_Enable)),
"Failed to enable pcie DPM during DPM Start Function!",
return -1
);
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_Falcon_QuickTransition)) {
smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_EnableACDCGPIOInterrupt);
}
return 0;
}
int tonga_disable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
/* disable SCLK dpm */
if (0 == data->sclk_dpm_key_disabled) {
/* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
PP_ASSERT_WITH_CODE(
(0 == tonga_is_dpm_running(hwmgr)),
"Trying to Disable SCLK DPM when DPM is disabled",
return -1
);
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_DPM_Disable)),
"Failed to disable SCLK DPM during DPM stop Function!",
return -1);
}
/* disable MCLK dpm */
if (0 == data->mclk_dpm_key_disabled) {
/* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
PP_ASSERT_WITH_CODE(
(0 == tonga_is_dpm_running(hwmgr)),
"Trying to Disable MCLK DPM when DPM is disabled",
return -1
);
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_MCLKDPM_Disable)),
"Failed to Disable MCLK DPM during DPM stop Function!",
return -1);
}
return 0;
}
int tonga_stop_dpm(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, 0);
/* disable sclk deep sleep*/
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, DYNAMIC_PM_EN, 0);
/* disable PCIE dpm */
if (0 == data->pcie_dpm_key_disabled) {
/* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
PP_ASSERT_WITH_CODE(
(0 == tonga_is_dpm_running(hwmgr)),
"Trying to Disable PCIE DPM when DPM is disabled",
return -1
);
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_PCIeDPM_Disable)),
"Failed to disable pcie DPM during DPM stop Function!",
return -1);
}
if (0 != tonga_disable_sclk_mclk_dpm(hwmgr))
PP_ASSERT_WITH_CODE(0, "Failed to disable Sclk DPM and Mclk DPM!", return -1);
/* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
PP_ASSERT_WITH_CODE(
(0 == tonga_is_dpm_running(hwmgr)),
"Trying to Disable Voltage CNTL when DPM is disabled",
return -1
);
PP_ASSERT_WITH_CODE(
(0 == smum_send_msg_to_smc(hwmgr->smumgr,
PPSMC_MSG_Voltage_Cntl_Disable)),
"Failed to disable voltage DPM during DPM stop Function!",
return -1);
return 0;
}
int tonga_enable_sclk_control(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0);
return 0;
}
/**
* Send a message to the SMC and return a parameter
*
* @param hwmgr: the address of the powerplay hardware manager.
* @param msg: the message to send.
* @param parameter: pointer to the received parameter
* @return The response that came from the SMC.
*/
PPSMC_Result tonga_send_msg_to_smc_return_parameter(
struct pp_hwmgr *hwmgr,
PPSMC_Msg msg,
uint32_t *parameter)
{
int result;
result = smum_send_msg_to_smc(hwmgr->smumgr, msg);
if ((0 == result) && parameter) {
*parameter = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
}
return result;
}
/**
* force DPM power State
*
* @param hwmgr: the address of the powerplay hardware manager.
* @param n : DPM level
* @return The response that came from the SMC.
*/
int tonga_dpm_force_state(struct pp_hwmgr *hwmgr, uint32_t n)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t level_mask = 1 << n;
/* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
"Trying to force SCLK when DPM is disabled", return -1;);
if (0 == data->sclk_dpm_key_disabled)
return (0 == smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
(PPSMC_Msg)(PPSMC_MSG_SCLKDPM_SetEnabledMask),
level_mask) ? 0 : 1);
return 0;
}
/**
* force DPM power State
*
* @param hwmgr: the address of the powerplay hardware manager.
* @param n : DPM level
* @return The response that came from the SMC.
*/
int tonga_dpm_force_state_mclk(struct pp_hwmgr *hwmgr, uint32_t n)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t level_mask = 1 << n;
/* Checking if DPM is running. If we discover hang because of this, we should skip this message. */
PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
"Trying to Force MCLK when DPM is disabled", return -1;);
if (0 == data->mclk_dpm_key_disabled)
return (0 == smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
(PPSMC_Msg)(PPSMC_MSG_MCLKDPM_SetEnabledMask),
level_mask) ? 0 : 1);
return 0;
}
/**
* force DPM power State
*
* @param hwmgr: the address of the powerplay hardware manager.
* @param n : DPM level
* @return The response that came from the SMC.
*/
int tonga_dpm_force_state_pcie(struct pp_hwmgr *hwmgr, uint32_t n)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
/* Checking if DPM is running. If we discover hang because of this, we should skip this message.*/
PP_ASSERT_WITH_CODE(0 == tonga_is_dpm_running(hwmgr),
"Trying to Force PCIE level when DPM is disabled", return -1;);
if (0 == data->pcie_dpm_key_disabled)
return (0 == smum_send_msg_to_smc_with_parameter(
hwmgr->smumgr,
(PPSMC_Msg)(PPSMC_MSG_PCIeDPM_ForceLevel),
n) ? 0 : 1);
return 0;
}
/**
* Set the initial state by calling SMC to switch to this state directly
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_set_boot_state(struct pp_hwmgr *hwmgr)
{
/*
* SMC only stores one state that SW will ask to switch too,
* so we switch the the just uploaded one
*/
return (0 == tonga_disable_sclk_mclk_dpm(hwmgr)) ? 0 : 1;
}
/**
* Get the location of various tables inside the FW image.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_process_firmware_header(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct tonga_smumgr *tonga_smu = (struct tonga_smumgr *)(hwmgr->smumgr->backend);
uint32_t tmp;
int result;
bool error = 0;
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, DpmTable),
&tmp, data->sram_end);
if (0 == result) {
data->dpm_table_start = tmp;
}
error |= (0 != result);
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, SoftRegisters),
&tmp, data->sram_end);
if (0 == result) {
data->soft_regs_start = tmp;
tonga_smu->ulSoftRegsStart = tmp;
}
error |= (0 != result);
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, mcRegisterTable),
&tmp, data->sram_end);
if (0 == result) {
data->mc_reg_table_start = tmp;
}
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, FanTable),
&tmp, data->sram_end);
if (0 == result) {
data->fan_table_start = tmp;
}
error |= (0 != result);
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, mcArbDramTimingTable),
&tmp, data->sram_end);
if (0 == result) {
data->arb_table_start = tmp;
}
error |= (0 != result);
result = tonga_read_smc_sram_dword(hwmgr->smumgr,
SMU72_FIRMWARE_HEADER_LOCATION +
offsetof(SMU72_Firmware_Header, Version),
&tmp, data->sram_end);
if (0 == result) {
hwmgr->microcode_version_info.SMC = tmp;
}
error |= (0 != result);
return error ? 1 : 0;
}
/**
* Read clock related registers.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_read_clock_registers(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
data->clock_registers.vCG_SPLL_FUNC_CNTL =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL);
data->clock_registers.vCG_SPLL_FUNC_CNTL_2 =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_2);
data->clock_registers.vCG_SPLL_FUNC_CNTL_3 =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_3);
data->clock_registers.vCG_SPLL_FUNC_CNTL_4 =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL_4);
data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM);
data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2 =
cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_SPREAD_SPECTRUM_2);
data->clock_registers.vDLL_CNTL =
cgs_read_register(hwmgr->device, mmDLL_CNTL);
data->clock_registers.vMCLK_PWRMGT_CNTL =
cgs_read_register(hwmgr->device, mmMCLK_PWRMGT_CNTL);
data->clock_registers.vMPLL_AD_FUNC_CNTL =
cgs_read_register(hwmgr->device, mmMPLL_AD_FUNC_CNTL);
data->clock_registers.vMPLL_DQ_FUNC_CNTL =
cgs_read_register(hwmgr->device, mmMPLL_DQ_FUNC_CNTL);
data->clock_registers.vMPLL_FUNC_CNTL =
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL);
data->clock_registers.vMPLL_FUNC_CNTL_1 =
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_1);
data->clock_registers.vMPLL_FUNC_CNTL_2 =
cgs_read_register(hwmgr->device, mmMPLL_FUNC_CNTL_2);
data->clock_registers.vMPLL_SS1 =
cgs_read_register(hwmgr->device, mmMPLL_SS1);
data->clock_registers.vMPLL_SS2 =
cgs_read_register(hwmgr->device, mmMPLL_SS2);
return 0;
}
/**
* Find out if memory is GDDR5.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_get_memory_type(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t temp;
temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0);
data->is_memory_GDDR5 = (MC_SEQ_MISC0_GDDR5_VALUE ==
((temp & MC_SEQ_MISC0_GDDR5_MASK) >>
MC_SEQ_MISC0_GDDR5_SHIFT));
return 0;
}
/**
* Enables Dynamic Power Management by SMC
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_enable_acpi_power_management(struct pp_hwmgr *hwmgr)
{
PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1);
return 0;
}
/**
* Initialize PowerGating States for different engines
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_init_power_gate_state(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
data->uvd_power_gated = 0;
data->vce_power_gated = 0;
data->samu_power_gated = 0;
data->acp_power_gated = 0;
data->pg_acp_init = 1;
return 0;
}
/**
* Checks if DPM is enabled
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_check_for_dpm_running(struct pp_hwmgr *hwmgr)
{
/*
* We return the status of Voltage Control instead of checking SCLK/MCLK DPM
* because we may have test scenarios that need us intentionly disable SCLK/MCLK DPM,
* whereas voltage control is a fundemental change that will not be disabled
*/
return (0 == tonga_is_dpm_running(hwmgr) ? 0 : 1);
}
/**
* Checks if DPM is stopped
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_check_for_dpm_stopped(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
if (0 != tonga_is_dpm_running(hwmgr)) {
/* If HW Virtualization is enabled, dpm_table_start will not have a valid value */
if (!data->dpm_table_start) {
return 1;
}
}
return 0;
}
/**
* Remove repeated voltage values and create table with unique values.
*
* @param hwmgr the address of the powerplay hardware manager.
* @param voltage_table the pointer to changing voltage table
* @return 1 in success
*/
static int tonga_trim_voltage_table(struct pp_hwmgr *hwmgr,
pp_atomctrl_voltage_table *voltage_table)
{
uint32_t table_size, i, j;
uint16_t vvalue;
bool bVoltageFound = 0;
pp_atomctrl_voltage_table *table;
PP_ASSERT_WITH_CODE((NULL != voltage_table), "Voltage Table empty.", return -1;);
table_size = sizeof(pp_atomctrl_voltage_table);
table = kzalloc(table_size, GFP_KERNEL);
if (NULL == table)
return -ENOMEM;
memset(table, 0x00, table_size);
table->mask_low = voltage_table->mask_low;
table->phase_delay = voltage_table->phase_delay;
for (i = 0; i < voltage_table->count; i++) {
vvalue = voltage_table->entries[i].value;
bVoltageFound = 0;
for (j = 0; j < table->count; j++) {
if (vvalue == table->entries[j].value) {
bVoltageFound = 1;
break;
}
}
if (!bVoltageFound) {
table->entries[table->count].value = vvalue;
table->entries[table->count].smio_low =
voltage_table->entries[i].smio_low;
table->count++;
}
}
memcpy(table, voltage_table, sizeof(pp_atomctrl_voltage_table));
kfree(table);
return 0;
}
static int tonga_get_svi2_vdd_ci_voltage_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table *voltage_dependency_table)
{
uint32_t i;
int result;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
pp_atomctrl_voltage_table *vddci_voltage_table = &(data->vddci_voltage_table);
PP_ASSERT_WITH_CODE((0 != voltage_dependency_table->count),
"Voltage Dependency Table empty.", return -1;);
vddci_voltage_table->mask_low = 0;
vddci_voltage_table->phase_delay = 0;
vddci_voltage_table->count = voltage_dependency_table->count;
for (i = 0; i < voltage_dependency_table->count; i++) {
vddci_voltage_table->entries[i].value =
voltage_dependency_table->entries[i].vddci;
vddci_voltage_table->entries[i].smio_low = 0;
}
result = tonga_trim_voltage_table(hwmgr, vddci_voltage_table);
PP_ASSERT_WITH_CODE((0 == result),
"Failed to trim VDDCI table.", return result;);
return 0;
}
static int tonga_get_svi2_vdd_voltage_table(
struct pp_hwmgr *hwmgr,
phm_ppt_v1_voltage_lookup_table *look_up_table,
pp_atomctrl_voltage_table *voltage_table)
{
uint8_t i = 0;
PP_ASSERT_WITH_CODE((0 != look_up_table->count),
"Voltage Lookup Table empty.", return -1;);
voltage_table->mask_low = 0;
voltage_table->phase_delay = 0;
voltage_table->count = look_up_table->count;
for (i = 0; i < voltage_table->count; i++) {
voltage_table->entries[i].value = look_up_table->entries[i].us_vdd;
voltage_table->entries[i].smio_low = 0;
}
return 0;
}
/*
* -------------------------------------------------------- Voltage Tables --------------------------------------------------------------------------
* If the voltage table would be bigger than what will fit into the state table on the SMC keep only the higher entries.
*/
static void tonga_trim_voltage_table_to_fit_state_table(
struct pp_hwmgr *hwmgr,
uint32_t max_voltage_steps,
pp_atomctrl_voltage_table *voltage_table)
{
unsigned int i, diff;
if (voltage_table->count <= max_voltage_steps) {
return;
}
diff = voltage_table->count - max_voltage_steps;
for (i = 0; i < max_voltage_steps; i++) {
voltage_table->entries[i] = voltage_table->entries[i + diff];
}
voltage_table->count = max_voltage_steps;
return;
}
/**
* Create Voltage Tables.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_construct_voltage_tables(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
int result;
/* MVDD has only GPIO voltage control */
if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
result = atomctrl_get_voltage_table_v3(hwmgr,
VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve MVDD table.", return result;);
}
if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
/* GPIO voltage */
result = atomctrl_get_voltage_table_v3(hwmgr,
VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve VDDCI table.", return result;);
} else if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
/* SVI2 voltage */
result = tonga_get_svi2_vdd_ci_voltage_table(hwmgr,
pptable_info->vdd_dep_on_mclk);
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve SVI2 VDDCI table from dependancy table.", return result;);
}
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
/* VDDGFX has only SVI2 voltage control */
result = tonga_get_svi2_vdd_voltage_table(hwmgr,
pptable_info->vddgfx_lookup_table, &(data->vddgfx_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve SVI2 VDDGFX table from lookup table.", return result;);
}
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
/* VDDC has only SVI2 voltage control */
result = tonga_get_svi2_vdd_voltage_table(hwmgr,
pptable_info->vddc_lookup_table, &(data->vddc_voltage_table));
PP_ASSERT_WITH_CODE((0 == result),
"Failed to retrieve SVI2 VDDC table from lookup table.", return result;);
}
PP_ASSERT_WITH_CODE(
(data->vddc_voltage_table.count <= (SMU72_MAX_LEVELS_VDDC)),
"Too many voltage values for VDDC. Trimming to fit state table.",
tonga_trim_voltage_table_to_fit_state_table(hwmgr,
SMU72_MAX_LEVELS_VDDC, &(data->vddc_voltage_table));
);
PP_ASSERT_WITH_CODE(
(data->vddgfx_voltage_table.count <= (SMU72_MAX_LEVELS_VDDGFX)),
"Too many voltage values for VDDGFX. Trimming to fit state table.",
tonga_trim_voltage_table_to_fit_state_table(hwmgr,
SMU72_MAX_LEVELS_VDDGFX, &(data->vddgfx_voltage_table));
);
PP_ASSERT_WITH_CODE(
(data->vddci_voltage_table.count <= (SMU72_MAX_LEVELS_VDDCI)),
"Too many voltage values for VDDCI. Trimming to fit state table.",
tonga_trim_voltage_table_to_fit_state_table(hwmgr,
SMU72_MAX_LEVELS_VDDCI, &(data->vddci_voltage_table));
);
PP_ASSERT_WITH_CODE(
(data->mvdd_voltage_table.count <= (SMU72_MAX_LEVELS_MVDD)),
"Too many voltage values for MVDD. Trimming to fit state table.",
tonga_trim_voltage_table_to_fit_state_table(hwmgr,
SMU72_MAX_LEVELS_MVDD, &(data->mvdd_voltage_table));
);
return 0;
}
/**
* Vddc table preparation for SMC.
*
* @param hwmgr the address of the hardware manager
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
static int tonga_populate_smc_vddc_table(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
unsigned int count;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
table->VddcLevelCount = data->vddc_voltage_table.count;
for (count = 0; count < table->VddcLevelCount; count++) {
table->VddcTable[count] =
PP_HOST_TO_SMC_US(data->vddc_voltage_table.entries[count].value * VOLTAGE_SCALE);
}
CONVERT_FROM_HOST_TO_SMC_UL(table->VddcLevelCount);
}
return 0;
}
/**
* VddGfx table preparation for SMC.
*
* @param hwmgr the address of the hardware manager
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
static int tonga_populate_smc_vdd_gfx_table(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
unsigned int count;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
table->VddGfxLevelCount = data->vddgfx_voltage_table.count;
for (count = 0; count < data->vddgfx_voltage_table.count; count++) {
table->VddGfxTable[count] =
PP_HOST_TO_SMC_US(data->vddgfx_voltage_table.entries[count].value * VOLTAGE_SCALE);
}
CONVERT_FROM_HOST_TO_SMC_UL(table->VddGfxLevelCount);
}
return 0;
}
/**
* Vddci table preparation for SMC.
*
* @param *hwmgr The address of the hardware manager.
* @param *table The SMC DPM table structure to be populated.
* @return 0
*/
static int tonga_populate_smc_vdd_ci_table(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t count;
table->VddciLevelCount = data->vddci_voltage_table.count;
for (count = 0; count < table->VddciLevelCount; count++) {
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
table->VddciTable[count] =
PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
} else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
table->SmioTable1.Pattern[count].Voltage =
PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level. */
table->SmioTable1.Pattern[count].Smio =
(uint8_t) count;
table->Smio[count] |=
data->vddci_voltage_table.entries[count].smio_low;
table->VddciTable[count] =
PP_HOST_TO_SMC_US(data->vddci_voltage_table.entries[count].value * VOLTAGE_SCALE);
}
}
table->SmioMask1 = data->vddci_voltage_table.mask_low;
CONVERT_FROM_HOST_TO_SMC_UL(table->VddciLevelCount);
return 0;
}
/**
* Mvdd table preparation for SMC.
*
* @param *hwmgr The address of the hardware manager.
* @param *table The SMC DPM table structure to be populated.
* @return 0
*/
static int tonga_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t count;
if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
table->MvddLevelCount = data->mvdd_voltage_table.count;
for (count = 0; count < table->MvddLevelCount; count++) {
table->SmioTable2.Pattern[count].Voltage =
PP_HOST_TO_SMC_US(data->mvdd_voltage_table.entries[count].value * VOLTAGE_SCALE);
/* Index into DpmTable.Smio. Drive bits from Smio entry to get this voltage level.*/
table->SmioTable2.Pattern[count].Smio =
(uint8_t) count;
table->Smio[count] |=
data->mvdd_voltage_table.entries[count].smio_low;
}
table->SmioMask2 = data->vddci_voltage_table.mask_low;
CONVERT_FROM_HOST_TO_SMC_UL(table->MvddLevelCount);
}
return 0;
}
/**
* Convert a voltage value in mv unit to VID number required by SMU firmware
*/
static uint8_t convert_to_vid(uint16_t vddc)
{
return (uint8_t) ((6200 - (vddc * VOLTAGE_SCALE)) / 25);
}
/**
* Preparation of vddc and vddgfx CAC tables for SMC.
*
* @param hwmgr the address of the hardware manager
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
static int tonga_populate_cac_tables(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
uint32_t count;
uint8_t index;
int result = 0;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
struct phm_ppt_v1_voltage_lookup_table *vddgfx_lookup_table = pptable_info->vddgfx_lookup_table;
struct phm_ppt_v1_voltage_lookup_table *vddc_lookup_table = pptable_info->vddc_lookup_table;
/* pTables is already swapped, so in order to use the value from it, we need to swap it back. */
uint32_t vddcLevelCount = PP_SMC_TO_HOST_UL(table->VddcLevelCount);
uint32_t vddgfxLevelCount = PP_SMC_TO_HOST_UL(table->VddGfxLevelCount);
for (count = 0; count < vddcLevelCount; count++) {
/* We are populating vddc CAC data to BapmVddc table in split and merged mode */
index = tonga_get_voltage_index(vddc_lookup_table,
data->vddc_voltage_table.entries[count].value);
table->BapmVddcVidLoSidd[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
table->BapmVddcVidHiSidd[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
table->BapmVddcVidHiSidd2[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
}
if ((data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2)) {
/* We are populating vddgfx CAC data to BapmVddgfx table in split mode */
for (count = 0; count < vddgfxLevelCount; count++) {
index = tonga_get_voltage_index(vddgfx_lookup_table,
data->vddgfx_voltage_table.entries[count].value);
table->BapmVddGfxVidLoSidd[count] =
convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_low);
table->BapmVddGfxVidHiSidd[count] =
convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_mid);
table->BapmVddGfxVidHiSidd2[count] =
convert_to_vid(vddgfx_lookup_table->entries[index].us_cac_high);
}
} else {
for (count = 0; count < vddcLevelCount; count++) {
index = tonga_get_voltage_index(vddc_lookup_table,
data->vddc_voltage_table.entries[count].value);
table->BapmVddGfxVidLoSidd[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_low);
table->BapmVddGfxVidHiSidd[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_mid);
table->BapmVddGfxVidHiSidd2[count] =
convert_to_vid(vddc_lookup_table->entries[index].us_cac_high);
}
}
return result;
}
/**
* Preparation of voltage tables for SMC.
*
* @param hwmgr the address of the hardware manager
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
int tonga_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result;
result = tonga_populate_smc_vddc_table(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"can not populate VDDC voltage table to SMC", return -1);
result = tonga_populate_smc_vdd_ci_table(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"can not populate VDDCI voltage table to SMC", return -1);
result = tonga_populate_smc_vdd_gfx_table(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"can not populate VDDGFX voltage table to SMC", return -1);
result = tonga_populate_smc_mvdd_table(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"can not populate MVDD voltage table to SMC", return -1);
result = tonga_populate_cac_tables(hwmgr, table);
PP_ASSERT_WITH_CODE(0 == result,
"can not populate CAC voltage tables to SMC", return -1);
return 0;
}
/**
* Populates the SMC VRConfig field in DPM table.
*
* @param hwmgr the address of the hardware manager
* @param table the SMC DPM table structure to be populated
* @return always 0
*/
static int tonga_populate_vr_config(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint16_t config;
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_gfx_control) {
/* Splitted mode */
config = VR_SVI2_PLANE_1;
table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
config = VR_SVI2_PLANE_2;
table->VRConfig |= config;
} else {
printk(KERN_ERR "[ powerplay ] VDDC and VDDGFX should be both on SVI2 control in splitted mode! \n");
}
} else {
/* Merged mode */
config = VR_MERGED_WITH_VDDC;
table->VRConfig |= (config<<VRCONF_VDDGFX_SHIFT);
/* Set Vddc Voltage Controller */
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) {
config = VR_SVI2_PLANE_1;
table->VRConfig |= config;
} else {
printk(KERN_ERR "[ powerplay ] VDDC should be on SVI2 control in merged mode! \n");
}
}
/* Set Vddci Voltage Controller */
if (TONGA_VOLTAGE_CONTROL_BY_SVID2 == data->vdd_ci_control) {
config = VR_SVI2_PLANE_2; /* only in merged mode */
table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
} else if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->vdd_ci_control) {
config = VR_SMIO_PATTERN_1;
table->VRConfig |= (config<<VRCONF_VDDCI_SHIFT);
}
/* Set Mvdd Voltage Controller */
if (TONGA_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) {
config = VR_SMIO_PATTERN_2;
table->VRConfig |= (config<<VRCONF_MVDD_SHIFT);
}
return 0;
}
static int tonga_get_dependecy_volt_by_clk(struct pp_hwmgr *hwmgr,
phm_ppt_v1_clock_voltage_dependency_table *allowed_clock_voltage_table,
uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd)
{
uint32_t i = 0;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
/* clock - voltage dependency table is empty table */
if (allowed_clock_voltage_table->count == 0)
return -1;
for (i = 0; i < allowed_clock_voltage_table->count; i++) {
/* find first sclk bigger than request */
if (allowed_clock_voltage_table->entries[i].clk >= clock) {
voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
allowed_clock_voltage_table->entries[i].vddgfx);
voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
allowed_clock_voltage_table->entries[i].vddc);
if (allowed_clock_voltage_table->entries[i].vddci) {
voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
allowed_clock_voltage_table->entries[i].vddci);
} else {
voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
allowed_clock_voltage_table->entries[i].vddc - data->vddc_vddci_delta);
}
if (allowed_clock_voltage_table->entries[i].mvdd) {
*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i].mvdd;
}
voltage->Phases = 1;
return 0;
}
}
/* sclk is bigger than max sclk in the dependence table */
voltage->VddGfx = tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
allowed_clock_voltage_table->entries[i-1].vddgfx);
voltage->Vddc = tonga_get_voltage_index(pptable_info->vddc_lookup_table,
allowed_clock_voltage_table->entries[i-1].vddc);
if (allowed_clock_voltage_table->entries[i-1].vddci) {
voltage->Vddci = tonga_get_voltage_id(&data->vddci_voltage_table,
allowed_clock_voltage_table->entries[i-1].vddci);
}
if (allowed_clock_voltage_table->entries[i-1].mvdd) {
*mvdd = (uint32_t) allowed_clock_voltage_table->entries[i-1].mvdd;
}
return 0;
}
/**
* Call SMC to reset S0/S1 to S1 and Reset SMIO to initial value
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
*/
int tonga_reset_to_default(struct pp_hwmgr *hwmgr)
{
return (smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_ResetToDefaults) == 0) ? 0 : 1;
}
int tonga_populate_memory_timing_parameters(
struct pp_hwmgr *hwmgr,
uint32_t engine_clock,
uint32_t memory_clock,
struct SMU72_Discrete_MCArbDramTimingTableEntry *arb_regs
)
{
uint32_t dramTiming;
uint32_t dramTiming2;
uint32_t burstTime;
int result;
result = atomctrl_set_engine_dram_timings_rv770(hwmgr,
engine_clock, memory_clock);
PP_ASSERT_WITH_CODE(result == 0,
"Error calling VBIOS to set DRAM_TIMING.", return result);
dramTiming = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING);
dramTiming2 = cgs_read_register(hwmgr->device, mmMC_ARB_DRAM_TIMING2);
burstTime = PHM_READ_FIELD(hwmgr->device, MC_ARB_BURST_TIME, STATE0);
arb_regs->McArbDramTiming = PP_HOST_TO_SMC_UL(dramTiming);
arb_regs->McArbDramTiming2 = PP_HOST_TO_SMC_UL(dramTiming2);
arb_regs->McArbBurstTime = (uint8_t)burstTime;
return 0;
}
/**
* Setup parameters for the MC ARB.
*
* @param hwmgr the address of the powerplay hardware manager.
* @return always 0
* This function is to be called from the SetPowerState table.
*/
int tonga_program_memory_timing_parameters(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
int result = 0;
SMU72_Discrete_MCArbDramTimingTable arb_regs;
uint32_t i, j;
memset(&arb_regs, 0x00, sizeof(SMU72_Discrete_MCArbDramTimingTable));
for (i = 0; i < data->dpm_table.sclk_table.count; i++) {
for (j = 0; j < data->dpm_table.mclk_table.count; j++) {
result = tonga_populate_memory_timing_parameters
(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value,
data->dpm_table.mclk_table.dpm_levels[j].value,
&arb_regs.entries[i][j]);
if (0 != result) {
break;
}
}
}
if (0 == result) {
result = tonga_copy_bytes_to_smc(
hwmgr->smumgr,
data->arb_table_start,
(uint8_t *)&arb_regs,
sizeof(SMU72_Discrete_MCArbDramTimingTable),
data->sram_end
);
}
return result;
}
static int tonga_populate_smc_link_level(struct pp_hwmgr *hwmgr, SMU72_Discrete_DpmTable *table)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct tonga_dpm_table *dpm_table = &data->dpm_table;
uint32_t i;
/* Index (dpm_table->pcie_speed_table.count) is reserved for PCIE boot level. */
for (i = 0; i <= dpm_table->pcie_speed_table.count; i++) {
table->LinkLevel[i].PcieGenSpeed =
(uint8_t)dpm_table->pcie_speed_table.dpm_levels[i].value;
table->LinkLevel[i].PcieLaneCount =
(uint8_t)encode_pcie_lane_width(dpm_table->pcie_speed_table.dpm_levels[i].param1);
table->LinkLevel[i].EnabledForActivity =
1;
table->LinkLevel[i].SPC =
(uint8_t)(data->pcie_spc_cap & 0xff);
table->LinkLevel[i].DownThreshold =
PP_HOST_TO_SMC_UL(5);
table->LinkLevel[i].UpThreshold =
PP_HOST_TO_SMC_UL(30);
}
data->smc_state_table.LinkLevelCount =
(uint8_t)dpm_table->pcie_speed_table.count;
data->dpm_level_enable_mask.pcie_dpm_enable_mask =
tonga_get_dpm_level_enable_mask_value(&dpm_table->pcie_speed_table);
return 0;
}
static int tonga_populate_smc_uvd_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
uint8_t count;
pp_atomctrl_clock_dividers_vi dividers;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
table->UvdLevelCount = (uint8_t) (mm_table->count);
table->UvdBootLevel = 0;
for (count = 0; count < table->UvdLevelCount; count++) {
table->UvdLevel[count].VclkFrequency = mm_table->entries[count].vclk;
table->UvdLevel[count].DclkFrequency = mm_table->entries[count].dclk;
table->UvdLevel[count].MinVoltage.Vddc =
tonga_get_voltage_index(pptable_info->vddc_lookup_table,
mm_table->entries[count].vddc);
table->UvdLevel[count].MinVoltage.VddGfx =
(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
mm_table->entries[count].vddgfx) : 0;
table->UvdLevel[count].MinVoltage.Vddci =
tonga_get_voltage_id(&data->vddci_voltage_table,
mm_table->entries[count].vddc - data->vddc_vddci_delta);
table->UvdLevel[count].MinVoltage.Phases = 1;
/* retrieve divider value for VBIOS */
result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
table->UvdLevel[count].VclkFrequency, &dividers);
PP_ASSERT_WITH_CODE((0 == result),
"can not find divide id for Vclk clock", return result);
table->UvdLevel[count].VclkDivider = (uint8_t)dividers.pll_post_divider;
result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
table->UvdLevel[count].DclkFrequency, &dividers);
PP_ASSERT_WITH_CODE((0 == result),
"can not find divide id for Dclk clock", return result);
table->UvdLevel[count].DclkDivider = (uint8_t)dividers.pll_post_divider;
CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].VclkFrequency);
CONVERT_FROM_HOST_TO_SMC_UL(table->UvdLevel[count].DclkFrequency);
//CONVERT_FROM_HOST_TO_SMC_UL((uint32_t)table->UvdLevel[count].MinVoltage);
}
return result;
}
static int tonga_populate_smc_vce_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
uint8_t count;
pp_atomctrl_clock_dividers_vi dividers;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
table->VceLevelCount = (uint8_t) (mm_table->count);
table->VceBootLevel = 0;
for (count = 0; count < table->VceLevelCount; count++) {
table->VceLevel[count].Frequency =
mm_table->entries[count].eclk;
table->VceLevel[count].MinVoltage.Vddc =
tonga_get_voltage_index(pptable_info->vddc_lookup_table,
mm_table->entries[count].vddc);
table->VceLevel[count].MinVoltage.VddGfx =
(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
mm_table->entries[count].vddgfx) : 0;
table->VceLevel[count].MinVoltage.Vddci =
tonga_get_voltage_id(&data->vddci_voltage_table,
mm_table->entries[count].vddc - data->vddc_vddci_delta);
table->VceLevel[count].MinVoltage.Phases = 1;
/* retrieve divider value for VBIOS */
result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
table->VceLevel[count].Frequency, &dividers);
PP_ASSERT_WITH_CODE((0 == result),
"can not find divide id for VCE engine clock", return result);
table->VceLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
CONVERT_FROM_HOST_TO_SMC_UL(table->VceLevel[count].Frequency);
}
return result;
}
static int tonga_populate_smc_acp_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
uint8_t count;
pp_atomctrl_clock_dividers_vi dividers;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
table->AcpLevelCount = (uint8_t) (mm_table->count);
table->AcpBootLevel = 0;
for (count = 0; count < table->AcpLevelCount; count++) {
table->AcpLevel[count].Frequency =
pptable_info->mm_dep_table->entries[count].aclk;
table->AcpLevel[count].MinVoltage.Vddc =
tonga_get_voltage_index(pptable_info->vddc_lookup_table,
mm_table->entries[count].vddc);
table->AcpLevel[count].MinVoltage.VddGfx =
(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
mm_table->entries[count].vddgfx) : 0;
table->AcpLevel[count].MinVoltage.Vddci =
tonga_get_voltage_id(&data->vddci_voltage_table,
mm_table->entries[count].vddc - data->vddc_vddci_delta);
table->AcpLevel[count].MinVoltage.Phases = 1;
/* retrieve divider value for VBIOS */
result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
table->AcpLevel[count].Frequency, &dividers);
PP_ASSERT_WITH_CODE((0 == result),
"can not find divide id for engine clock", return result);
table->AcpLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
CONVERT_FROM_HOST_TO_SMC_UL(table->AcpLevel[count].Frequency);
}
return result;
}
static int tonga_populate_smc_samu_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
uint8_t count;
pp_atomctrl_clock_dividers_vi dividers;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = pptable_info->mm_dep_table;
table->SamuBootLevel = 0;
table->SamuLevelCount = (uint8_t) (mm_table->count);
for (count = 0; count < table->SamuLevelCount; count++) {
/* not sure whether we need evclk or not */
table->SamuLevel[count].Frequency =
pptable_info->mm_dep_table->entries[count].samclock;
table->SamuLevel[count].MinVoltage.Vddc =
tonga_get_voltage_index(pptable_info->vddc_lookup_table,
mm_table->entries[count].vddc);
table->SamuLevel[count].MinVoltage.VddGfx =
(data->vdd_gfx_control == TONGA_VOLTAGE_CONTROL_BY_SVID2) ?
tonga_get_voltage_index(pptable_info->vddgfx_lookup_table,
mm_table->entries[count].vddgfx) : 0;
table->SamuLevel[count].MinVoltage.Vddci =
tonga_get_voltage_id(&data->vddci_voltage_table,
mm_table->entries[count].vddc - data->vddc_vddci_delta);
table->SamuLevel[count].MinVoltage.Phases = 1;
/* retrieve divider value for VBIOS */
result = atomctrl_get_dfs_pll_dividers_vi(hwmgr,
table->SamuLevel[count].Frequency, &dividers);
PP_ASSERT_WITH_CODE((0 == result),
"can not find divide id for samu clock", return result);
table->SamuLevel[count].Divider = (uint8_t)dividers.pll_post_divider;
CONVERT_FROM_HOST_TO_SMC_UL(table->SamuLevel[count].Frequency);
}
return result;
}
/**
* Populates the SMC MCLK structure using the provided memory clock
*
* @param hwmgr the address of the hardware manager
* @param memory_clock the memory clock to use to populate the structure
* @param sclk the SMC SCLK structure to be populated
*/
static int tonga_calculate_mclk_params(
struct pp_hwmgr *hwmgr,
uint32_t memory_clock,
SMU72_Discrete_MemoryLevel *mclk,
bool strobe_mode,
bool dllStateOn
)
{
const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
uint32_t mpll_ad_func_cntl = data->clock_registers.vMPLL_AD_FUNC_CNTL;
uint32_t mpll_dq_func_cntl = data->clock_registers.vMPLL_DQ_FUNC_CNTL;
uint32_t mpll_func_cntl = data->clock_registers.vMPLL_FUNC_CNTL;
uint32_t mpll_func_cntl_1 = data->clock_registers.vMPLL_FUNC_CNTL_1;
uint32_t mpll_func_cntl_2 = data->clock_registers.vMPLL_FUNC_CNTL_2;
uint32_t mpll_ss1 = data->clock_registers.vMPLL_SS1;
uint32_t mpll_ss2 = data->clock_registers.vMPLL_SS2;
pp_atomctrl_memory_clock_param mpll_param;
int result;
result = atomctrl_get_memory_pll_dividers_si(hwmgr,
memory_clock, &mpll_param, strobe_mode);
PP_ASSERT_WITH_CODE(0 == result,
"Error retrieving Memory Clock Parameters from VBIOS.", return result);
/* MPLL_FUNC_CNTL setup*/
mpll_func_cntl = PHM_SET_FIELD(mpll_func_cntl, MPLL_FUNC_CNTL, BWCTRL, mpll_param.bw_ctrl);
/* MPLL_FUNC_CNTL_1 setup*/
mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
MPLL_FUNC_CNTL_1, CLKF, mpll_param.mpll_fb_divider.cl_kf);
mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
MPLL_FUNC_CNTL_1, CLKFRAC, mpll_param.mpll_fb_divider.clk_frac);
mpll_func_cntl_1 = PHM_SET_FIELD(mpll_func_cntl_1,
MPLL_FUNC_CNTL_1, VCO_MODE, mpll_param.vco_mode);
/* MPLL_AD_FUNC_CNTL setup*/
mpll_ad_func_cntl = PHM_SET_FIELD(mpll_ad_func_cntl,
MPLL_AD_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
if (data->is_memory_GDDR5) {
/* MPLL_DQ_FUNC_CNTL setup*/
mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
MPLL_DQ_FUNC_CNTL, YCLK_SEL, mpll_param.yclk_sel);
mpll_dq_func_cntl = PHM_SET_FIELD(mpll_dq_func_cntl,
MPLL_DQ_FUNC_CNTL, YCLK_POST_DIV, mpll_param.mpll_post_divider);
}
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_MemorySpreadSpectrumSupport)) {
/*
************************************
Fref = Reference Frequency
NF = Feedback divider ratio
NR = Reference divider ratio
Fnom = Nominal VCO output frequency = Fref * NF / NR
Fs = Spreading Rate
D = Percentage down-spread / 2
Fint = Reference input frequency to PFD = Fref / NR
NS = Spreading rate divider ratio = int(Fint / (2 * Fs))
CLKS = NS - 1 = ISS_STEP_NUM[11:0]
NV = D * Fs / Fnom * 4 * ((Fnom/Fref * NR) ^ 2)
CLKV = 65536 * NV = ISS_STEP_SIZE[25:0]
*************************************
*/
pp_atomctrl_internal_ss_info ss_info;
uint32_t freq_nom;
uint32_t tmp;
uint32_t reference_clock = atomctrl_get_mpll_reference_clock(hwmgr);
/* for GDDR5 for all modes and DDR3 */
if (1 == mpll_param.qdr)
freq_nom = memory_clock * 4 * (1 << mpll_param.mpll_post_divider);
else
freq_nom = memory_clock * 2 * (1 << mpll_param.mpll_post_divider);
/* tmp = (freq_nom / reference_clock * reference_divider) ^ 2 Note: S.I. reference_divider = 1*/
tmp = (freq_nom / reference_clock);
tmp = tmp * tmp;
if (0 == atomctrl_get_memory_clock_spread_spectrum(hwmgr, freq_nom, &ss_info)) {
/* ss_info.speed_spectrum_percentage -- in unit of 0.01% */
/* ss.Info.speed_spectrum_rate -- in unit of khz */
/* CLKS = reference_clock / (2 * speed_spectrum_rate * reference_divider) * 10 */
/* = reference_clock * 5 / speed_spectrum_rate */
uint32_t clks = reference_clock * 5 / ss_info.speed_spectrum_rate;
/* CLKV = 65536 * speed_spectrum_percentage / 2 * spreadSpecrumRate / freq_nom * 4 / 100000 * ((freq_nom / reference_clock) ^ 2) */
/* = 131 * speed_spectrum_percentage * speed_spectrum_rate / 100 * ((freq_nom / reference_clock) ^ 2) / freq_nom */
uint32_t clkv =
(uint32_t)((((131 * ss_info.speed_spectrum_percentage *
ss_info.speed_spectrum_rate) / 100) * tmp) / freq_nom);
mpll_ss1 = PHM_SET_FIELD(mpll_ss1, MPLL_SS1, CLKV, clkv);
mpll_ss2 = PHM_SET_FIELD(mpll_ss2, MPLL_SS2, CLKS, clks);
}
}
/* MCLK_PWRMGT_CNTL setup */
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, DLL_SPEED, mpll_param.dll_speed);
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK0_PDNB, dllStateOn);
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK1_PDNB, dllStateOn);
/* Save the result data to outpupt memory level structure */
mclk->MclkFrequency = memory_clock;
mclk->MpllFuncCntl = mpll_func_cntl;
mclk->MpllFuncCntl_1 = mpll_func_cntl_1;
mclk->MpllFuncCntl_2 = mpll_func_cntl_2;
mclk->MpllAdFuncCntl = mpll_ad_func_cntl;
mclk->MpllDqFuncCntl = mpll_dq_func_cntl;
mclk->MclkPwrmgtCntl = mclk_pwrmgt_cntl;
mclk->DllCntl = dll_cntl;
mclk->MpllSs1 = mpll_ss1;
mclk->MpllSs2 = mpll_ss2;
return 0;
}
static uint8_t tonga_get_mclk_frequency_ratio(uint32_t memory_clock,
bool strobe_mode)
{
uint8_t mc_para_index;
if (strobe_mode) {
if (memory_clock < 12500) {
mc_para_index = 0x00;
} else if (memory_clock > 47500) {
mc_para_index = 0x0f;
} else {
mc_para_index = (uint8_t)((memory_clock - 10000) / 2500);
}
} else {
if (memory_clock < 65000) {
mc_para_index = 0x00;
} else if (memory_clock > 135000) {
mc_para_index = 0x0f;
} else {
mc_para_index = (uint8_t)((memory_clock - 60000) / 5000);
}
}
return mc_para_index;
}
static uint8_t tonga_get_ddr3_mclk_frequency_ratio(uint32_t memory_clock)
{
uint8_t mc_para_index;
if (memory_clock < 10000) {
mc_para_index = 0;
} else if (memory_clock >= 80000) {
mc_para_index = 0x0f;
} else {
mc_para_index = (uint8_t)((memory_clock - 10000) / 5000 + 1);
}
return mc_para_index;
}
static int tonga_populate_single_memory_level(
struct pp_hwmgr *hwmgr,
uint32_t memory_clock,
SMU72_Discrete_MemoryLevel *memory_level
)
{
uint32_t minMvdd = 0;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
int result = 0;
bool dllStateOn;
struct cgs_display_info info = {0};
if (NULL != pptable_info->vdd_dep_on_mclk) {
result = tonga_get_dependecy_volt_by_clk(hwmgr,
pptable_info->vdd_dep_on_mclk, memory_clock, &memory_level->MinVoltage, &minMvdd);
PP_ASSERT_WITH_CODE((0 == result),
"can not find MinVddc voltage value from memory VDDC voltage dependency table", return result);
}
if (data->mvdd_control == TONGA_VOLTAGE_CONTROL_NONE) {
memory_level->MinMvdd = data->vbios_boot_state.mvdd_bootup_value;
} else {
memory_level->MinMvdd = minMvdd;
}
memory_level->EnabledForThrottle = 1;
memory_level->EnabledForActivity = 0;
memory_level->UpHyst = 0;
memory_level->DownHyst = 100;
memory_level->VoltageDownHyst = 0;
/* Indicates maximum activity level for this performance level.*/
memory_level->ActivityLevel = (uint16_t)data->mclk_activity_target;
memory_level->StutterEnable = 0;
memory_level->StrobeEnable = 0;
memory_level->EdcReadEnable = 0;
memory_level->EdcWriteEnable = 0;
memory_level->RttEnable = 0;
/* default set to low watermark. Highest level will be set to high later.*/
memory_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
cgs_get_active_displays_info(hwmgr->device, &info);
data->display_timing.num_existing_displays = info.display_count;
if ((data->mclk_stutter_mode_threshold != 0) &&
(memory_clock <= data->mclk_stutter_mode_threshold) &&
(data->is_uvd_enabled == 0)
&& (PHM_READ_FIELD(hwmgr->device, DPG_PIPE_STUTTER_CONTROL, STUTTER_ENABLE) & 0x1)
&& (data->display_timing.num_existing_displays <= 2)
&& (data->display_timing.num_existing_displays != 0))
memory_level->StutterEnable = 1;
/* decide strobe mode*/
memory_level->StrobeEnable = (data->mclk_strobe_mode_threshold != 0) &&
(memory_clock <= data->mclk_strobe_mode_threshold);
/* decide EDC mode and memory clock ratio*/
if (data->is_memory_GDDR5) {
memory_level->StrobeRatio = tonga_get_mclk_frequency_ratio(memory_clock,
memory_level->StrobeEnable);
if ((data->mclk_edc_enable_threshold != 0) &&
(memory_clock > data->mclk_edc_enable_threshold)) {
memory_level->EdcReadEnable = 1;
}
if ((data->mclk_edc_wr_enable_threshold != 0) &&
(memory_clock > data->mclk_edc_wr_enable_threshold)) {
memory_level->EdcWriteEnable = 1;
}
if (memory_level->StrobeEnable) {
if (tonga_get_mclk_frequency_ratio(memory_clock, 1) >=
((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC7) >> 16) & 0xf)) {
dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
} else {
dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC6) >> 1) & 0x1) ? 1 : 0;
}
} else {
dllStateOn = data->dll_defaule_on;
}
} else {
memory_level->StrobeRatio =
tonga_get_ddr3_mclk_frequency_ratio(memory_clock);
dllStateOn = ((cgs_read_register(hwmgr->device, mmMC_SEQ_MISC5) >> 1) & 0x1) ? 1 : 0;
}
result = tonga_calculate_mclk_params(hwmgr,
memory_clock, memory_level, memory_level->StrobeEnable, dllStateOn);
if (0 == result) {
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MinMvdd);
/* MCLK frequency in units of 10KHz*/
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkFrequency);
/* Indicates maximum activity level for this performance level.*/
CONVERT_FROM_HOST_TO_SMC_US(memory_level->ActivityLevel);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_1);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllFuncCntl_2);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllAdFuncCntl);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllDqFuncCntl);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MclkPwrmgtCntl);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->DllCntl);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs1);
CONVERT_FROM_HOST_TO_SMC_UL(memory_level->MpllSs2);
}
return result;
}
/**
* Populates the SMC MVDD structure using the provided memory clock.
*
* @param hwmgr the address of the hardware manager
* @param mclk the MCLK value to be used in the decision if MVDD should be high or low.
* @param voltage the SMC VOLTAGE structure to be populated
*/
int tonga_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pattern)
{
const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
uint32_t i = 0;
if (TONGA_VOLTAGE_CONTROL_NONE != data->mvdd_control) {
/* find mvdd value which clock is more than request */
for (i = 0; i < pptable_info->vdd_dep_on_mclk->count; i++) {
if (mclk <= pptable_info->vdd_dep_on_mclk->entries[i].clk) {
/* Always round to higher voltage. */
smio_pattern->Voltage = data->mvdd_voltage_table.entries[i].value;
break;
}
}
PP_ASSERT_WITH_CODE(i < pptable_info->vdd_dep_on_mclk->count,
"MVDD Voltage is outside the supported range.", return -1);
} else {
return -1;
}
return 0;
}
static int tonga_populate_smv_acpi_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
pp_atomctrl_clock_dividers_vi dividers;
SMIO_Pattern voltage_level;
uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
uint32_t spll_func_cntl_2 = data->clock_registers.vCG_SPLL_FUNC_CNTL_2;
uint32_t dll_cntl = data->clock_registers.vDLL_CNTL;
uint32_t mclk_pwrmgt_cntl = data->clock_registers.vMCLK_PWRMGT_CNTL;
/* The ACPI state should not do DPM on DC (or ever).*/
table->ACPILevel.Flags &= ~PPSMC_SWSTATE_FLAG_DC;
table->ACPILevel.MinVoltage = data->smc_state_table.GraphicsLevel[0].MinVoltage;
/* assign zero for now*/
table->ACPILevel.SclkFrequency = atomctrl_get_reference_clock(hwmgr);
/* get the engine clock dividers for this clock value*/
result = atomctrl_get_engine_pll_dividers_vi(hwmgr,
table->ACPILevel.SclkFrequency, &dividers);
PP_ASSERT_WITH_CODE(result == 0,
"Error retrieving Engine Clock dividers from VBIOS.", return result);
/* divider ID for required SCLK*/
table->ACPILevel.SclkDid = (uint8_t)dividers.pll_post_divider;
table->ACPILevel.DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
table->ACPILevel.DeepSleepDivId = 0;
spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
CG_SPLL_FUNC_CNTL, SPLL_PWRON, 0);
spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
CG_SPLL_FUNC_CNTL, SPLL_RESET, 1);
spll_func_cntl_2 = PHM_SET_FIELD(spll_func_cntl_2,
CG_SPLL_FUNC_CNTL_2, SCLK_MUX_SEL, 4);
table->ACPILevel.CgSpllFuncCntl = spll_func_cntl;
table->ACPILevel.CgSpllFuncCntl2 = spll_func_cntl_2;
table->ACPILevel.CgSpllFuncCntl3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
table->ACPILevel.CgSpllFuncCntl4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
table->ACPILevel.SpllSpreadSpectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
table->ACPILevel.SpllSpreadSpectrum2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
table->ACPILevel.CcPwrDynRm = 0;
table->ACPILevel.CcPwrDynRm1 = 0;
/* For various features to be enabled/disabled while this level is active.*/
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.Flags);
/* SCLK frequency in units of 10KHz*/
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SclkFrequency);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl2);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl3);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CgSpllFuncCntl4);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.SpllSpreadSpectrum2);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm);
CONVERT_FROM_HOST_TO_SMC_UL(table->ACPILevel.CcPwrDynRm1);
/* table->MemoryACPILevel.MinVddcPhases = table->ACPILevel.MinVddcPhases;*/
table->MemoryACPILevel.MinVoltage = data->smc_state_table.MemoryLevel[0].MinVoltage;
/* CONVERT_FROM_HOST_TO_SMC_UL(table->MemoryACPILevel.MinVoltage);*/
if (0 == tonga_populate_mvdd_value(hwmgr, 0, &voltage_level))
table->MemoryACPILevel.MinMvdd =
PP_HOST_TO_SMC_UL(voltage_level.Voltage * VOLTAGE_SCALE);
else
table->MemoryACPILevel.MinMvdd = 0;
/* Force reset on DLL*/
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK0_RESET, 0x1);
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK1_RESET, 0x1);
/* Disable DLL in ACPIState*/
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK0_PDNB, 0);
mclk_pwrmgt_cntl = PHM_SET_FIELD(mclk_pwrmgt_cntl,
MCLK_PWRMGT_CNTL, MRDCK1_PDNB, 0);
/* Enable DLL bypass signal*/
dll_cntl = PHM_SET_FIELD(dll_cntl,
DLL_CNTL, MRDCK0_BYPASS, 0);
dll_cntl = PHM_SET_FIELD(dll_cntl,
DLL_CNTL, MRDCK1_BYPASS, 0);
table->MemoryACPILevel.DllCntl =
PP_HOST_TO_SMC_UL(dll_cntl);
table->MemoryACPILevel.MclkPwrmgtCntl =
PP_HOST_TO_SMC_UL(mclk_pwrmgt_cntl);
table->MemoryACPILevel.MpllAdFuncCntl =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_AD_FUNC_CNTL);
table->MemoryACPILevel.MpllDqFuncCntl =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_DQ_FUNC_CNTL);
table->MemoryACPILevel.MpllFuncCntl =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL);
table->MemoryACPILevel.MpllFuncCntl_1 =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_1);
table->MemoryACPILevel.MpllFuncCntl_2 =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_FUNC_CNTL_2);
table->MemoryACPILevel.MpllSs1 =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS1);
table->MemoryACPILevel.MpllSs2 =
PP_HOST_TO_SMC_UL(data->clock_registers.vMPLL_SS2);
table->MemoryACPILevel.EnabledForThrottle = 0;
table->MemoryACPILevel.EnabledForActivity = 0;
table->MemoryACPILevel.UpHyst = 0;
table->MemoryACPILevel.DownHyst = 100;
table->MemoryACPILevel.VoltageDownHyst = 0;
/* Indicates maximum activity level for this performance level.*/
table->MemoryACPILevel.ActivityLevel = PP_HOST_TO_SMC_US((uint16_t)data->mclk_activity_target);
table->MemoryACPILevel.StutterEnable = 0;
table->MemoryACPILevel.StrobeEnable = 0;
table->MemoryACPILevel.EdcReadEnable = 0;
table->MemoryACPILevel.EdcWriteEnable = 0;
table->MemoryACPILevel.RttEnable = 0;
return result;
}
static int tonga_find_boot_level(struct tonga_single_dpm_table *table, uint32_t value, uint32_t *boot_level)
{
int result = 0;
uint32_t i;
for (i = 0; i < table->count; i++) {
if (value == table->dpm_levels[i].value) {
*boot_level = i;
result = 0;
}
}
return result;
}
static int tonga_populate_smc_boot_level(struct pp_hwmgr *hwmgr,
SMU72_Discrete_DpmTable *table)
{
int result = 0;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
table->GraphicsBootLevel = 0; /* 0 == DPM[0] (low), etc. */
table->MemoryBootLevel = 0; /* 0 == DPM[0] (low), etc. */
/* find boot level from dpm table*/
result = tonga_find_boot_level(&(data->dpm_table.sclk_table),
data->vbios_boot_state.sclk_bootup_value,
(uint32_t *)&(data->smc_state_table.GraphicsBootLevel));
if (0 != result) {
data->smc_state_table.GraphicsBootLevel = 0;
printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
in dependency table. Using Graphics DPM level 0!");
result = 0;
}
result = tonga_find_boot_level(&(data->dpm_table.mclk_table),
data->vbios_boot_state.mclk_bootup_value,
(uint32_t *)&(data->smc_state_table.MemoryBootLevel));
if (0 != result) {
data->smc_state_table.MemoryBootLevel = 0;
printk(KERN_ERR "[ powerplay ] VBIOS did not find boot engine clock value \
in dependency table. Using Memory DPM level 0!");
result = 0;
}
table->BootVoltage.Vddc =
tonga_get_voltage_id(&(data->vddc_voltage_table),
data->vbios_boot_state.vddc_bootup_value);
table->BootVoltage.VddGfx =
tonga_get_voltage_id(&(data->vddgfx_voltage_table),
data->vbios_boot_state.vddgfx_bootup_value);
table->BootVoltage.Vddci =
tonga_get_voltage_id(&(data->vddci_voltage_table),
data->vbios_boot_state.vddci_bootup_value);
table->BootMVdd = data->vbios_boot_state.mvdd_bootup_value;
CONVERT_FROM_HOST_TO_SMC_US(table->BootMVdd);
return result;
}
/**
* Calculates the SCLK dividers using the provided engine clock
*
* @param hwmgr the address of the hardware manager
* @param engine_clock the engine clock to use to populate the structure
* @param sclk the SMC SCLK structure to be populated
*/
int tonga_calculate_sclk_params(struct pp_hwmgr *hwmgr,
uint32_t engine_clock, SMU72_Discrete_GraphicsLevel *sclk)
{
const tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
pp_atomctrl_clock_dividers_vi dividers;
uint32_t spll_func_cntl = data->clock_registers.vCG_SPLL_FUNC_CNTL;
uint32_t spll_func_cntl_3 = data->clock_registers.vCG_SPLL_FUNC_CNTL_3;
uint32_t spll_func_cntl_4 = data->clock_registers.vCG_SPLL_FUNC_CNTL_4;
uint32_t cg_spll_spread_spectrum = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM;
uint32_t cg_spll_spread_spectrum_2 = data->clock_registers.vCG_SPLL_SPREAD_SPECTRUM_2;
uint32_t reference_clock;
uint32_t reference_divider;
uint32_t fbdiv;
int result;
/* get the engine clock dividers for this clock value*/
result = atomctrl_get_engine_pll_dividers_vi(hwmgr, engine_clock, &dividers);
PP_ASSERT_WITH_CODE(result == 0,
"Error retrieving Engine Clock dividers from VBIOS.", return result);
/* To get FBDIV we need to multiply this by 16384 and divide it by Fref.*/
reference_clock = atomctrl_get_reference_clock(hwmgr);
reference_divider = 1 + dividers.uc_pll_ref_div;
/* low 14 bits is fraction and high 12 bits is divider*/
fbdiv = dividers.ul_fb_div.ul_fb_divider & 0x3FFFFFF;
/* SPLL_FUNC_CNTL setup*/
spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
CG_SPLL_FUNC_CNTL, SPLL_REF_DIV, dividers.uc_pll_ref_div);
spll_func_cntl = PHM_SET_FIELD(spll_func_cntl,
CG_SPLL_FUNC_CNTL, SPLL_PDIV_A, dividers.uc_pll_post_div);
/* SPLL_FUNC_CNTL_3 setup*/
spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
CG_SPLL_FUNC_CNTL_3, SPLL_FB_DIV, fbdiv);
/* set to use fractional accumulation*/
spll_func_cntl_3 = PHM_SET_FIELD(spll_func_cntl_3,
CG_SPLL_FUNC_CNTL_3, SPLL_DITHEN, 1);
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_EngineSpreadSpectrumSupport)) {
pp_atomctrl_internal_ss_info ss_info;
uint32_t vcoFreq = engine_clock * dividers.uc_pll_post_div;
if (0 == atomctrl_get_engine_clock_spread_spectrum(hwmgr, vcoFreq, &ss_info)) {
/*
* ss_info.speed_spectrum_percentage -- in unit of 0.01%
* ss_info.speed_spectrum_rate -- in unit of khz
*/
/* clks = reference_clock * 10 / (REFDIV + 1) / speed_spectrum_rate / 2 */
uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate);
/* clkv = 2 * D * fbdiv / NS */
uint32_t clkV = 4 * ss_info.speed_spectrum_percentage * fbdiv / (clkS * 10000);
cg_spll_spread_spectrum =
PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, CLKS, clkS);
cg_spll_spread_spectrum =
PHM_SET_FIELD(cg_spll_spread_spectrum, CG_SPLL_SPREAD_SPECTRUM, SSEN, 1);
cg_spll_spread_spectrum_2 =
PHM_SET_FIELD(cg_spll_spread_spectrum_2, CG_SPLL_SPREAD_SPECTRUM_2, CLKV, clkV);
}
}
sclk->SclkFrequency = engine_clock;
sclk->CgSpllFuncCntl3 = spll_func_cntl_3;
sclk->CgSpllFuncCntl4 = spll_func_cntl_4;
sclk->SpllSpreadSpectrum = cg_spll_spread_spectrum;
sclk->SpllSpreadSpectrum2 = cg_spll_spread_spectrum_2;
sclk->SclkDid = (uint8_t)dividers.pll_post_divider;
return 0;
}
static uint8_t tonga_get_sleep_divider_id_from_clock(uint32_t engine_clock,
uint32_t min_engine_clock_in_sr)
{
uint32_t i, temp;
uint32_t min = max(min_engine_clock_in_sr, (uint32_t)TONGA_MINIMUM_ENGINE_CLOCK);
PP_ASSERT_WITH_CODE((engine_clock >= min),
"Engine clock can't satisfy stutter requirement!", return 0);
for (i = TONGA_MAX_DEEPSLEEP_DIVIDER_ID;; i--) {
temp = engine_clock >> i;
if(temp >= min || i == 0)
break;
}
return (uint8_t)i;
}
/**
* Populates single SMC SCLK structure using the provided engine clock
*
* @param hwmgr the address of the hardware manager
* @param engine_clock the engine clock to use to populate the structure
* @param sclk the SMC SCLK structure to be populated
*/
static int tonga_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t engine_clock, uint16_t sclk_activity_level_threshold, SMU72_Discrete_GraphicsLevel *graphic_level)
{
int result;
uint32_t threshold;
uint32_t mvdd;
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
result = tonga_calculate_sclk_params(hwmgr, engine_clock, graphic_level);
/* populate graphics levels*/
result = tonga_get_dependecy_volt_by_clk(hwmgr,
pptable_info->vdd_dep_on_sclk, engine_clock,
&graphic_level->MinVoltage, &mvdd);
PP_ASSERT_WITH_CODE((0 == result),
"can not find VDDC voltage value for VDDC \
engine clock dependency table", return result);
/* SCLK frequency in units of 10KHz*/
graphic_level->SclkFrequency = engine_clock;
/* Indicates maximum activity level for this performance level. 50% for now*/
graphic_level->ActivityLevel = sclk_activity_level_threshold;
graphic_level->CcPwrDynRm = 0;
graphic_level->CcPwrDynRm1 = 0;
/* this level can be used if activity is high enough.*/
graphic_level->EnabledForActivity = 0;
/* this level can be used for throttling.*/
graphic_level->EnabledForThrottle = 1;
graphic_level->UpHyst = 0;
graphic_level->DownHyst = 0;
graphic_level->VoltageDownHyst = 0;
graphic_level->PowerThrottle = 0;
threshold = engine_clock * data->fast_watemark_threshold / 100;
/*
*get the DAL clock. do it in funture.
PECI_GetMinClockSettings(hwmgr->peci, &minClocks);
data->display_timing.min_clock_insr = minClocks.engineClockInSR;
*/
if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,
PHM_PlatformCaps_SclkDeepSleep))
graphic_level->DeepSleepDivId =
tonga_get_sleep_divider_id_from_clock(engine_clock,
data->display_timing.min_clock_insr);
/* Default to slow, highest DPM level will be set to PPSMC_DISPLAY_WATERMARK_LOW later.*/
graphic_level->DisplayWatermark = PPSMC_DISPLAY_WATERMARK_LOW;
if (0 == result) {
/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVoltage);*/
/* CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->MinVddcPhases);*/
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SclkFrequency);
CONVERT_FROM_HOST_TO_SMC_US(graphic_level->ActivityLevel);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl3);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CgSpllFuncCntl4);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->SpllSpreadSpectrum2);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm);
CONVERT_FROM_HOST_TO_SMC_UL(graphic_level->CcPwrDynRm1);
}
return result;
}
/**
* Populates all SMC SCLK levels' structure based on the trimmed allowed dpm engine clock states
*
* @param hwmgr the address of the hardware manager
*/
static int tonga_populate_all_graphic_levels(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
struct tonga_dpm_table *dpm_table = &data->dpm_table;
phm_ppt_v1_pcie_table *pcie_table = pptable_info->pcie_table;
uint8_t pcie_entry_count = (uint8_t) data->dpm_table.pcie_speed_table.count;
int result = 0;
uint32_t level_array_adress = data->dpm_table_start +
offsetof(SMU72_Discrete_DpmTable, GraphicsLevel);
uint32_t level_array_size = sizeof(SMU72_Discrete_GraphicsLevel) *
SMU72_MAX_LEVELS_GRAPHICS; /* 64 -> long; 32 -> int*/
SMU72_Discrete_GraphicsLevel *levels = data->smc_state_table.GraphicsLevel;
uint32_t i, maxEntry;
uint8_t highest_pcie_level_enabled = 0, lowest_pcie_level_enabled = 0, mid_pcie_level_enabled = 0, count = 0;
PECI_RegistryValue reg_value;
memset(levels, 0x00, level_array_size);
for (i = 0; i < dpm_table->sclk_table.count; i++) {
result = tonga_populate_single_graphic_level(hwmgr,
dpm_table->sclk_table.dpm_levels[i].value,
(uint16_t)data->activity_target[i],
&(data->smc_state_table.GraphicsLevel[i]));
if (0 != result)
return result;
/* Making sure only DPM level 0-1 have Deep Sleep Div ID populated. */
if (i > 1)
data->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0;
if (0 == i) {
reg_value = 0;
if (reg_value != 0)
data->smc_state_table.GraphicsLevel[0].UpHyst = (uint8_t)reg_value;
}
if (1 == i) {
reg_value = 0;
if (reg_value != 0)
data->smc_state_table.GraphicsLevel[1].UpHyst = (uint8_t)reg_value;
}
}
/* Only enable level 0 for now. */
data->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1;
/* set highest level watermark to high */
if (dpm_table->sclk_table.count > 1)
data->smc_state_table.GraphicsLevel[dpm_table->sclk_table.count-1].DisplayWatermark =
PPSMC_DISPLAY_WATERMARK_HIGH;
data->smc_state_table.GraphicsDpmLevelCount =
(uint8_t)dpm_table->sclk_table.count;
data->dpm_level_enable_mask.sclk_dpm_enable_mask =
tonga_get_dpm_level_enable_mask_value(&dpm_table->sclk_table);
if (pcie_table != NULL) {
PP_ASSERT_WITH_CODE((pcie_entry_count >= 1),
"There must be 1 or more PCIE levels defined in PPTable.", return -1);
maxEntry = pcie_entry_count - 1; /* for indexing, we need to decrement by 1.*/
for (i = 0; i < dpm_table->sclk_table.count; i++) {
data->smc_state_table.GraphicsLevel[i].pcieDpmLevel =
(uint8_t) ((i < maxEntry) ? i : maxEntry);
}
} else {
if (0 == data->dpm_level_enable_mask.pcie_dpm_enable_mask)
printk(KERN_ERR "[ powerplay ] Pcie Dpm Enablemask is 0!");
while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
(1<<(highest_pcie_level_enabled+1))) != 0)) {
highest_pcie_level_enabled++;
}
while (data->dpm_level_enable_mask.pcie_dpm_enable_mask &&
((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
(1<<lowest_pcie_level_enabled)) == 0)) {
lowest_pcie_level_enabled++;
}
while ((count < highest_pcie_level_enabled) &&
((data->dpm_level_enable_mask.pcie_dpm_enable_mask &
(1<<(lowest_pcie_level_enabled+1+count))) == 0)) {
count++;
}
mid_pcie_level_enabled = (lowest_pcie_level_enabled+1+count) < highest_pcie_level_enabled ?
(lowest_pcie_level_enabled+1+count) : highest_pcie_level_enabled;
/* set pcieDpmLevel to highest_pcie_level_enabled*/
for (i = 2; i < dpm_table->sclk_table.count; i++) {
data->smc_state_table.GraphicsLevel[i].pcieDpmLevel = highest_pcie_level_enabled;
}
/* set pcieDpmLevel to lowest_pcie_level_enabled*/
data->smc_state_table.GraphicsLevel[0].pcieDpmLevel = lowest_pcie_level_enabled;
/* set pcieDpmLevel to mid_pcie_level_enabled*/
data->smc_state_table.GraphicsLevel[1].pcieDpmLevel = mid_pcie_level_enabled;
}
/* level count will send to smc once at init smc table and never change*/
result = tonga_copy_bytes_to_smc(hwmgr->smumgr, level_array_adress, (uint8_t *)levels, (uint32_t)level_array_size, data->sram_end);
if (0 != result)
return result;
return 0;
}
/**
* Populates all SMC MCLK levels' structure based on the trimmed allowed dpm memory clock states
*
* @param hwmgr the address of the hardware manager
*/
static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
tonga_hwmgr *data = (tonga_hwmgr *)(hwmgr->backend);
struct tonga_dpm_table *dpm_table = &data->dpm_table;
int result;
/* populate MCLK dpm table to SMU7 */
uint32_t level_array_adress = data->dpm_table_start + offsetof(SMU72_Discrete_DpmTable, MemoryLevel);
uint32_t level_array_size = sizeof(SMU72_Discrete_MemoryLevel) * SMU72_MAX_LEVELS_MEMORY;
SMU72_Discrete_MemoryLevel *levels = data->smc_state_table.MemoryLevel;
uint32_t i;
memset(levels, 0x00, level_array_size);
for (i = 0; i < dpm_table->mclk_table.count; i++) {
PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value),
"can not populate memory level as memory clock is zero", return -1);
result = tonga_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value,
&(data->smc_state_table.MemoryLevel[i]));
if