| commit | 4ba9d48cc6799a8d2801f97ae9f4dd59b1d04d11 | [log] [tgz] |
|---|---|---|
| author | Yanchang Li <yl22@csr.com> | Wed Jan 07 20:58:07 2015 +0800 |
| committer | Barry Song <Barry.Song@csr.com> | Thu Jan 08 20:16:33 2015 +0800 |
| tree | e8c28a21580de9225f9aabc219a9ab043c58e096 | |
| parent | f5f489bc3789c8da37d2084e19142fb5128550a7 [diff] |
atlas7: ddr: enable DDR 2T timing enable DDR "2T timing" configuration Change-Id: I392a276f21c839034412ffb2f1548b56588160ae Signed-off-by: Yanchang Li <yl22@csr.com>