blob: 654029fc8d96ffccb785cde10295509564b137a7 [file] [log] [blame]
// SPDX-License-Identifier: GPL-2.0
/*
* sh73a0 processor support - PFC hardware block
*
* Copyright (C) 2010 Renesas Solutions Corp.
* Copyright (C) 2010 NISHIMOTO Hiroki
*/
#include <linux/io.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/regulator/driver.h>
#include <linux/regulator/machine.h>
#include <linux/slab.h>
#include "core.h"
#include "sh_pfc.h"
#define CPU_ALL_PORT(fn, pfx, sfx) \
PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
PORT_10(100, fn, pfx##10, sfx), \
PORT_1(110, fn, pfx##110, sfx), PORT_1(111, fn, pfx##111, sfx), \
PORT_1(112, fn, pfx##112, sfx), PORT_1(113, fn, pfx##113, sfx), \
PORT_1(114, fn, pfx##114, sfx), PORT_1(115, fn, pfx##115, sfx), \
PORT_1(116, fn, pfx##116, sfx), PORT_1(117, fn, pfx##117, sfx), \
PORT_1(118, fn, pfx##118, sfx), \
PORT_1(128, fn, pfx##128, sfx), PORT_1(129, fn, pfx##129, sfx), \
PORT_10(130, fn, pfx##13, sfx), PORT_10(140, fn, pfx##14, sfx), \
PORT_10(150, fn, pfx##15, sfx), \
PORT_1(160, fn, pfx##160, sfx), PORT_1(161, fn, pfx##161, sfx), \
PORT_1(162, fn, pfx##162, sfx), PORT_1(163, fn, pfx##163, sfx), \
PORT_1(164, fn, pfx##164, sfx), \
PORT_1(192, fn, pfx##192, sfx), PORT_1(193, fn, pfx##193, sfx), \
PORT_1(194, fn, pfx##194, sfx), PORT_1(195, fn, pfx##195, sfx), \
PORT_1(196, fn, pfx##196, sfx), PORT_1(197, fn, pfx##197, sfx), \
PORT_1(198, fn, pfx##198, sfx), PORT_1(199, fn, pfx##199, sfx), \
PORT_10(200, fn, pfx##20, sfx), PORT_10(210, fn, pfx##21, sfx), \
PORT_10(220, fn, pfx##22, sfx), PORT_10(230, fn, pfx##23, sfx), \
PORT_10(240, fn, pfx##24, sfx), PORT_10(250, fn, pfx##25, sfx), \
PORT_10(260, fn, pfx##26, sfx), PORT_10(270, fn, pfx##27, sfx), \
PORT_1(280, fn, pfx##280, sfx), PORT_1(281, fn, pfx##281, sfx), \
PORT_1(282, fn, pfx##282, sfx), \
PORT_1(288, fn, pfx##288, sfx), PORT_1(289, fn, pfx##289, sfx), \
PORT_10(290, fn, pfx##29, sfx), PORT_10(300, fn, pfx##30, sfx)
enum {
PINMUX_RESERVED = 0,
PINMUX_DATA_BEGIN,
PORT_ALL(DATA), /* PORT0_DATA -> PORT309_DATA */
PINMUX_DATA_END,
PINMUX_INPUT_BEGIN,
PORT_ALL(IN), /* PORT0_IN -> PORT309_IN */
PINMUX_INPUT_END,
PINMUX_OUTPUT_BEGIN,
PORT_ALL(OUT), /* PORT0_OUT -> PORT309_OUT */
PINMUX_OUTPUT_END,
PINMUX_FUNCTION_BEGIN,
PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT309_FN_IN */
PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT309_FN_OUT */
PORT_ALL(FN0), /* PORT0_FN0 -> PORT309_FN0 */
PORT_ALL(FN1), /* PORT0_FN1 -> PORT309_FN1 */
PORT_ALL(FN2), /* PORT0_FN2 -> PORT309_FN2 */
PORT_ALL(FN3), /* PORT0_FN3 -> PORT309_FN3 */
PORT_ALL(FN4), /* PORT0_FN4 -> PORT309_FN4 */
PORT_ALL(FN5), /* PORT0_FN5 -> PORT309_FN5 */
PORT_ALL(FN6), /* PORT0_FN6 -> PORT309_FN6 */
PORT_ALL(FN7), /* PORT0_FN7 -> PORT309_FN7 */
MSEL2CR_MSEL19_0, MSEL2CR_MSEL19_1,
MSEL2CR_MSEL18_0, MSEL2CR_MSEL18_1,
MSEL2CR_MSEL17_0, MSEL2CR_MSEL17_1,
MSEL2CR_MSEL16_0, MSEL2CR_MSEL16_1,
MSEL2CR_MSEL14_0, MSEL2CR_MSEL14_1,
MSEL2CR_MSEL13_0, MSEL2CR_MSEL13_1,
MSEL2CR_MSEL12_0, MSEL2CR_MSEL12_1,
MSEL2CR_MSEL11_0, MSEL2CR_MSEL11_1,
MSEL2CR_MSEL10_0, MSEL2CR_MSEL10_1,
MSEL2CR_MSEL9_0, MSEL2CR_MSEL9_1,
MSEL2CR_MSEL8_0, MSEL2CR_MSEL8_1,
MSEL2CR_MSEL7_0, MSEL2CR_MSEL7_1,
MSEL2CR_MSEL6_0, MSEL2CR_MSEL6_1,
MSEL2CR_MSEL4_0, MSEL2CR_MSEL4_1,
MSEL2CR_MSEL5_0, MSEL2CR_MSEL5_1,
MSEL2CR_MSEL3_0, MSEL2CR_MSEL3_1,
MSEL2CR_MSEL2_0, MSEL2CR_MSEL2_1,
MSEL2CR_MSEL1_0, MSEL2CR_MSEL1_1,
MSEL2CR_MSEL0_0, MSEL2CR_MSEL0_1,
MSEL3CR_MSEL28_0, MSEL3CR_MSEL28_1,
MSEL3CR_MSEL15_0, MSEL3CR_MSEL15_1,
MSEL3CR_MSEL11_0, MSEL3CR_MSEL11_1,
MSEL3CR_MSEL9_0, MSEL3CR_MSEL9_1,
MSEL3CR_MSEL6_0, MSEL3CR_MSEL6_1,
MSEL3CR_MSEL2_0, MSEL3CR_MSEL2_1,
MSEL4CR_MSEL29_0, MSEL4CR_MSEL29_1,
MSEL4CR_MSEL27_0, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0, MSEL4CR_MSEL26_1,
MSEL4CR_MSEL22_0, MSEL4CR_MSEL22_1,
MSEL4CR_MSEL21_0, MSEL4CR_MSEL21_1,
MSEL4CR_MSEL20_0, MSEL4CR_MSEL20_1,
MSEL4CR_MSEL19_0, MSEL4CR_MSEL19_1,
MSEL4CR_MSEL15_0, MSEL4CR_MSEL15_1,
MSEL4CR_MSEL13_0, MSEL4CR_MSEL13_1,
MSEL4CR_MSEL12_0, MSEL4CR_MSEL12_1,
MSEL4CR_MSEL11_0, MSEL4CR_MSEL11_1,
MSEL4CR_MSEL10_0, MSEL4CR_MSEL10_1,
MSEL4CR_MSEL9_0, MSEL4CR_MSEL9_1,
MSEL4CR_MSEL8_0, MSEL4CR_MSEL8_1,
MSEL4CR_MSEL7_0, MSEL4CR_MSEL7_1,
MSEL4CR_MSEL4_0, MSEL4CR_MSEL4_1,
MSEL4CR_MSEL1_0, MSEL4CR_MSEL1_1,
PINMUX_FUNCTION_END,
PINMUX_MARK_BEGIN,
/* Hardware manual Table 25-1 (Function 0-7) */
VBUS_0_MARK,
GPI0_MARK,
GPI1_MARK,
GPI2_MARK,
GPI3_MARK,
GPI4_MARK,
GPI5_MARK,
GPI6_MARK,
GPI7_MARK,
SCIFA7_RXD_MARK,
SCIFA7_CTS__MARK,
GPO7_MARK, MFG0_OUT2_MARK,
GPO6_MARK, MFG1_OUT2_MARK,
GPO5_MARK, SCIFA0_SCK_MARK, FSICOSLDT3_MARK, PORT16_VIO_CKOR_MARK,
SCIFA0_TXD_MARK,
SCIFA7_TXD_MARK,
SCIFA7_RTS__MARK, PORT19_VIO_CKO2_MARK,
GPO0_MARK,
GPO1_MARK,
GPO2_MARK, STATUS0_MARK,
GPO3_MARK, STATUS1_MARK,
GPO4_MARK, STATUS2_MARK,
VINT_MARK,
TCKON_MARK,
XDVFS1_MARK, PORT27_I2C_SCL2_MARK, PORT27_I2C_SCL3_MARK, \
MFG0_OUT1_MARK, PORT27_IROUT_MARK,
XDVFS2_MARK, PORT28_I2C_SDA2_MARK, PORT28_I2C_SDA3_MARK, \
PORT28_TPU1TO1_MARK,
SIM_RST_MARK, PORT29_TPU1TO1_MARK,
SIM_CLK_MARK, PORT30_VIO_CKOR_MARK,
SIM_D_MARK, PORT31_IROUT_MARK,
SCIFA4_TXD_MARK,
SCIFA4_RXD_MARK, XWUP_MARK,
SCIFA4_RTS__MARK,
SCIFA4_CTS__MARK,
FSIBOBT_MARK, FSIBIBT_MARK,
FSIBOLR_MARK, FSIBILR_MARK,
FSIBOSLD_MARK,
FSIBISLD_MARK,
VACK_MARK,
XTAL1L_MARK,
SCIFA0_RTS__MARK, FSICOSLDT2_MARK,
SCIFA0_RXD_MARK,
SCIFA0_CTS__MARK, FSICOSLDT1_MARK,
FSICOBT_MARK, FSICIBT_MARK, FSIDOBT_MARK, FSIDIBT_MARK,
FSICOLR_MARK, FSICILR_MARK, FSIDOLR_MARK, FSIDILR_MARK,
FSICOSLD_MARK, PORT47_FSICSPDIF_MARK,
FSICISLD_MARK, FSIDISLD_MARK,
FSIACK_MARK, PORT49_IRDA_OUT_MARK, PORT49_IROUT_MARK, FSIAOMC_MARK,
FSIAOLR_MARK, BBIF2_TSYNC2_MARK, TPU2TO2_MARK, FSIAILR_MARK,
FSIAOBT_MARK, BBIF2_TSCK2_MARK, TPU2TO3_MARK, FSIAIBT_MARK,
FSIAOSLD_MARK, BBIF2_TXD2_MARK,
FSIASPDIF_MARK, PORT53_IRDA_IN_MARK, TPU3TO3_MARK, FSIBSPDIF_MARK, \
PORT53_FSICSPDIF_MARK,
FSIBCK_MARK, PORT54_IRDA_FIRSEL_MARK, TPU3TO2_MARK, FSIBOMC_MARK, \
FSICCK_MARK, FSICOMC_MARK,
FSIAISLD_MARK, TPU0TO0_MARK,
A0_MARK, BS__MARK,
A12_MARK, PORT58_KEYOUT7_MARK, TPU4TO2_MARK,
A13_MARK, PORT59_KEYOUT6_MARK, TPU0TO1_MARK,
A14_MARK, KEYOUT5_MARK,
A15_MARK, KEYOUT4_MARK,
A16_MARK, KEYOUT3_MARK, MSIOF0_SS1_MARK,
A17_MARK, KEYOUT2_MARK, MSIOF0_TSYNC_MARK,
A18_MARK, KEYOUT1_MARK, MSIOF0_TSCK_MARK,
A19_MARK, KEYOUT0_MARK, MSIOF0_TXD_MARK,
A20_MARK, KEYIN0_MARK, MSIOF0_RSCK_MARK,
A21_MARK, KEYIN1_MARK, MSIOF0_RSYNC_MARK,
A22_MARK, KEYIN2_MARK, MSIOF0_MCK0_MARK,
A23_MARK, KEYIN3_MARK, MSIOF0_MCK1_MARK,
A24_MARK, KEYIN4_MARK, MSIOF0_RXD_MARK,
A25_MARK, KEYIN5_MARK, MSIOF0_SS2_MARK,
A26_MARK, KEYIN6_MARK,
KEYIN7_MARK,
D0_NAF0_MARK,
D1_NAF1_MARK,
D2_NAF2_MARK,
D3_NAF3_MARK,
D4_NAF4_MARK,
D5_NAF5_MARK,
D6_NAF6_MARK,
D7_NAF7_MARK,
D8_NAF8_MARK,
D9_NAF9_MARK,
D10_NAF10_MARK,
D11_NAF11_MARK,
D12_NAF12_MARK,
D13_NAF13_MARK,
D14_NAF14_MARK,
D15_NAF15_MARK,
CS4__MARK,
CS5A__MARK, PORT91_RDWR_MARK,
CS5B__MARK, FCE1__MARK,
CS6B__MARK, DACK0_MARK,
FCE0__MARK, CS6A__MARK,
WAIT__MARK, DREQ0_MARK,
RD__FSC_MARK,
WE0__FWE_MARK, RDWR_FWE_MARK,
WE1__MARK,
FRB_MARK,
CKO_MARK,
NBRSTOUT__MARK,
NBRST__MARK,
BBIF2_TXD_MARK,
BBIF2_RXD_MARK,
BBIF2_SYNC_MARK,
BBIF2_SCK_MARK,
SCIFA3_CTS__MARK, MFG3_IN2_MARK,
SCIFA3_RXD_MARK, MFG3_IN1_MARK,
BBIF1_SS2_MARK, SCIFA3_RTS__MARK, MFG3_OUT1_MARK,
SCIFA3_TXD_MARK,
HSI_RX_DATA_MARK, BBIF1_RXD_MARK,
HSI_TX_WAKE_MARK, BBIF1_TSCK_MARK,
HSI_TX_DATA_MARK, BBIF1_TSYNC_MARK,
HSI_TX_READY_MARK, BBIF1_TXD_MARK,
HSI_RX_READY_MARK, BBIF1_RSCK_MARK, PORT115_I2C_SCL2_MARK, \
PORT115_I2C_SCL3_MARK,
HSI_RX_WAKE_MARK, BBIF1_RSYNC_MARK, PORT116_I2C_SDA2_MARK, \
PORT116_I2C_SDA3_MARK,
HSI_RX_FLAG_MARK, BBIF1_SS1_MARK, BBIF1_FLOW_MARK,
HSI_TX_FLAG_MARK,
VIO_VD_MARK, PORT128_LCD2VSYN_MARK, VIO2_VD_MARK, LCD2D0_MARK,
VIO_HD_MARK, PORT129_LCD2HSYN_MARK, PORT129_LCD2CS__MARK, \
VIO2_HD_MARK, LCD2D1_MARK,
VIO_D0_MARK, PORT130_MSIOF2_RXD_MARK, LCD2D10_MARK,
VIO_D1_MARK, PORT131_KEYOUT6_MARK, PORT131_MSIOF2_SS1_MARK, \
PORT131_KEYOUT11_MARK, LCD2D11_MARK,
VIO_D2_MARK, PORT132_KEYOUT7_MARK, PORT132_MSIOF2_SS2_MARK, \
PORT132_KEYOUT10_MARK, LCD2D12_MARK,
VIO_D3_MARK, MSIOF2_TSYNC_MARK, LCD2D13_MARK,
VIO_D4_MARK, MSIOF2_TXD_MARK, LCD2D14_MARK,
VIO_D5_MARK, MSIOF2_TSCK_MARK, LCD2D15_MARK,
VIO_D6_MARK, PORT136_KEYOUT8_MARK, LCD2D16_MARK,
VIO_D7_MARK, PORT137_KEYOUT9_MARK, LCD2D17_MARK,
VIO_D8_MARK, PORT138_KEYOUT8_MARK, VIO2_D0_MARK, LCD2D6_MARK,
VIO_D9_MARK, PORT139_KEYOUT9_MARK, VIO2_D1_MARK, LCD2D7_MARK,
VIO_D10_MARK, TPU0TO2_MARK, VIO2_D2_MARK, LCD2D8_MARK,
VIO_D11_MARK, TPU0TO3_MARK, VIO2_D3_MARK, LCD2D9_MARK,
VIO_D12_MARK, PORT142_KEYOUT10_MARK, VIO2_D4_MARK, LCD2D2_MARK,
VIO_D13_MARK, PORT143_KEYOUT11_MARK, PORT143_KEYOUT6_MARK, \
VIO2_D5_MARK, LCD2D3_MARK,
VIO_D14_MARK, PORT144_KEYOUT7_MARK, VIO2_D6_MARK, LCD2D4_MARK,
VIO_D15_MARK, TPU1TO3_MARK, PORT145_LCD2DISP_MARK, \
PORT145_LCD2RS_MARK, VIO2_D7_MARK, LCD2D5_MARK,
VIO_CLK_MARK, LCD2DCK_MARK, PORT146_LCD2WR__MARK, VIO2_CLK_MARK, \
LCD2D18_MARK,
VIO_FIELD_MARK, LCD2RD__MARK, VIO2_FIELD_MARK, LCD2D19_MARK,
VIO_CKO_MARK,
A27_MARK, PORT149_RDWR_MARK, MFG0_IN1_MARK, PORT149_KEYOUT9_MARK,
MFG0_IN2_MARK,
TS_SPSYNC3_MARK, MSIOF2_RSCK_MARK,
TS_SDAT3_MARK, MSIOF2_RSYNC_MARK,
TPU1TO2_MARK, TS_SDEN3_MARK, PORT153_MSIOF2_SS1_MARK,
SCIFA2_TXD1_MARK, MSIOF2_MCK0_MARK,
SCIFA2_RXD1_MARK, MSIOF2_MCK1_MARK,
SCIFA2_RTS1__MARK, PORT156_MSIOF2_SS2_MARK,
SCIFA2_CTS1__MARK, PORT157_MSIOF2_RXD_MARK,
DINT__MARK, SCIFA2_SCK1_MARK, TS_SCK3_MARK,
PORT159_SCIFB_SCK_MARK, PORT159_SCIFA5_SCK_MARK, NMI_MARK,
PORT160_SCIFB_TXD_MARK, PORT160_SCIFA5_TXD_MARK,
PORT161_SCIFB_CTS__MARK, PORT161_SCIFA5_CTS__MARK,
PORT162_SCIFB_RXD_MARK, PORT162_SCIFA5_RXD_MARK,
PORT163_SCIFB_RTS__MARK, PORT163_SCIFA5_RTS__MARK, TPU3TO0_MARK,
LCDD0_MARK,
LCDD1_MARK, PORT193_SCIFA5_CTS__MARK, BBIF2_TSYNC1_MARK,
LCDD2_MARK, PORT194_SCIFA5_RTS__MARK, BBIF2_TSCK1_MARK,
LCDD3_MARK, PORT195_SCIFA5_RXD_MARK, BBIF2_TXD1_MARK,
LCDD4_MARK, PORT196_SCIFA5_TXD_MARK,
LCDD5_MARK, PORT197_SCIFA5_SCK_MARK, MFG2_OUT2_MARK, TPU2TO1_MARK,
LCDD6_MARK,
LCDD7_MARK, TPU4TO1_MARK, MFG4_OUT2_MARK,
LCDD8_MARK, D16_MARK,
LCDD9_MARK, D17_MARK,
LCDD10_MARK, D18_MARK,
LCDD11_MARK, D19_MARK,
LCDD12_MARK, D20_MARK,
LCDD13_MARK, D21_MARK,
LCDD14_MARK, D22_MARK,
LCDD15_MARK, PORT207_MSIOF0L_SS1_MARK, D23_MARK,
LCDD16_MARK, PORT208_MSIOF0L_SS2_MARK, D24_MARK,
LCDD17_MARK, D25_MARK,
LCDD18_MARK, DREQ2_MARK, PORT210_MSIOF0L_SS1_MARK, D26_MARK,
LCDD19_MARK, PORT211_MSIOF0L_SS2_MARK, D27_MARK,
LCDD20_MARK, TS_SPSYNC1_MARK, MSIOF0L_MCK0_MARK, D28_MARK,
LCDD21_MARK, TS_SDAT1_MARK, MSIOF0L_MCK1_MARK, D29_MARK,
LCDD22_MARK, TS_SDEN1_MARK, MSIOF0L_RSCK_MARK, D30_MARK,
LCDD23_MARK, TS_SCK1_MARK, MSIOF0L_RSYNC_MARK, D31_MARK,
LCDDCK_MARK, LCDWR__MARK,
LCDRD__MARK, DACK2_MARK, PORT217_LCD2RS_MARK, MSIOF0L_TSYNC_MARK, \
VIO2_FIELD3_MARK, PORT217_LCD2DISP_MARK,
LCDHSYN_MARK, LCDCS__MARK, LCDCS2__MARK, DACK3_MARK, \
PORT218_VIO_CKOR_MARK,
LCDDISP_MARK, LCDRS_MARK, PORT219_LCD2WR__MARK, DREQ3_MARK, \
MSIOF0L_TSCK_MARK, VIO2_CLK3_MARK, LCD2DCK_2_MARK,
LCDVSYN_MARK, LCDVSYN2_MARK,
LCDLCLK_MARK, DREQ1_MARK, PORT221_LCD2CS__MARK, PWEN_MARK, \
MSIOF0L_RXD_MARK, VIO2_HD3_MARK, PORT221_LCD2HSYN_MARK,
LCDDON_MARK, LCDDON2_MARK, DACK1_MARK, OVCN_MARK, MSIOF0L_TXD_MARK, \
VIO2_VD3_MARK, PORT222_LCD2VSYN_MARK,
SCIFA1_TXD_MARK, OVCN2_MARK,
EXTLP_MARK, SCIFA1_SCK_MARK, PORT226_VIO_CKO2_MARK,
SCIFA1_RTS__MARK, IDIN_MARK,
SCIFA1_RXD_MARK,
SCIFA1_CTS__MARK, MFG1_IN1_MARK,
MSIOF1_TXD_MARK, SCIFA2_TXD2_MARK,
MSIOF1_TSYNC_MARK, SCIFA2_CTS2__MARK,
MSIOF1_TSCK_MARK, SCIFA2_SCK2_MARK,
MSIOF1_RXD_MARK, SCIFA2_RXD2_MARK,
MSIOF1_RSCK_MARK, SCIFA2_RTS2__MARK, VIO2_CLK2_MARK, LCD2D20_MARK,
MSIOF1_RSYNC_MARK, MFG1_IN2_MARK, VIO2_VD2_MARK, LCD2D21_MARK,
MSIOF1_MCK0_MARK, PORT236_I2C_SDA2_MARK,
MSIOF1_MCK1_MARK, PORT237_I2C_SCL2_MARK,
MSIOF1_SS1_MARK, VIO2_FIELD2_MARK, LCD2D22_MARK,
MSIOF1_SS2_MARK, VIO2_HD2_MARK, LCD2D23_MARK,
SCIFA6_TXD_MARK,
PORT241_IRDA_OUT_MARK, PORT241_IROUT_MARK, MFG4_OUT1_MARK, TPU4TO0_MARK,
PORT242_IRDA_IN_MARK, MFG4_IN2_MARK,
PORT243_IRDA_FIRSEL_MARK, PORT243_VIO_CKO2_MARK,
PORT244_SCIFA5_CTS__MARK, MFG2_IN1_MARK, PORT244_SCIFB_CTS__MARK, \
MSIOF2R_RXD_MARK,
PORT245_SCIFA5_RTS__MARK, MFG2_IN2_MARK, PORT245_SCIFB_RTS__MARK, \
MSIOF2R_TXD_MARK,
PORT246_SCIFA5_RXD_MARK, MFG1_OUT1_MARK, PORT246_SCIFB_RXD_MARK, \
TPU1TO0_MARK,
PORT247_SCIFA5_TXD_MARK, MFG3_OUT2_MARK, PORT247_SCIFB_TXD_MARK, \
TPU3TO1_MARK,
PORT248_SCIFA5_SCK_MARK, MFG2_OUT1_MARK, PORT248_SCIFB_SCK_MARK, \
TPU2TO0_MARK, PORT248_I2C_SCL3_MARK, MSIOF2R_TSCK_MARK,
PORT249_IROUT_MARK, MFG4_IN1_MARK, PORT249_I2C_SDA3_MARK, \
MSIOF2R_TSYNC_MARK,
SDHICLK0_MARK,
SDHICD0_MARK,
SDHID0_0_MARK,
SDHID0_1_MARK,
SDHID0_2_MARK,
SDHID0_3_MARK,
SDHICMD0_MARK,
SDHIWP0_MARK,
SDHICLK1_MARK,
SDHID1_0_MARK, TS_SPSYNC2_MARK,
SDHID1_1_MARK, TS_SDAT2_MARK,
SDHID1_2_MARK, TS_SDEN2_MARK,
SDHID1_3_MARK, TS_SCK2_MARK,
SDHICMD1_MARK,
SDHICLK2_MARK,
SDHID2_0_MARK, TS_SPSYNC4_MARK,
SDHID2_1_MARK, TS_SDAT4_MARK,
SDHID2_2_MARK, TS_SDEN4_MARK,
SDHID2_3_MARK, TS_SCK4_MARK,
SDHICMD2_MARK,
MMCCLK0_MARK,
MMCD0_0_MARK,
MMCD0_1_MARK,
MMCD0_2_MARK,
MMCD0_3_MARK,
MMCD0_4_MARK, TS_SPSYNC5_MARK,
MMCD0_5_MARK, TS_SDAT5_MARK,
MMCD0_6_MARK, TS_SDEN5_MARK,
MMCD0_7_MARK, TS_SCK5_MARK,
MMCCMD0_MARK,
RESETOUTS__MARK, EXTAL2OUT_MARK,
MCP_WAIT__MCP_FRB_MARK,
MCP_CKO_MARK, MMCCLK1_MARK,
MCP_D15_MCP_NAF15_MARK,
MCP_D14_MCP_NAF14_MARK,
MCP_D13_MCP_NAF13_MARK,
MCP_D12_MCP_NAF12_MARK,
MCP_D11_MCP_NAF11_MARK,
MCP_D10_MCP_NAF10_MARK,
MCP_D9_MCP_NAF9_MARK,
MCP_D8_MCP_NAF8_MARK, MMCCMD1_MARK,
MCP_D7_MCP_NAF7_MARK, MMCD1_7_MARK,
MCP_D6_MCP_NAF6_MARK, MMCD1_6_MARK,
MCP_D5_MCP_NAF5_MARK, MMCD1_5_MARK,
MCP_D4_MCP_NAF4_MARK, MMCD1_4_MARK,
MCP_D3_MCP_NAF3_MARK, MMCD1_3_MARK,
MCP_D2_MCP_NAF2_MARK, MMCD1_2_MARK,
MCP_D1_MCP_NAF1_MARK, MMCD1_1_MARK,
MCP_D0_MCP_NAF0_MARK, MMCD1_0_MARK,
MCP_NBRSTOUT__MARK,
MCP_WE0__MCP_FWE_MARK, MCP_RDWR_MCP_FWE_MARK,
/* MSEL2 special cases */
TSIF2_TS_XX1_MARK,
TSIF2_TS_XX2_MARK,
TSIF2_TS_XX3_MARK,
TSIF2_TS_XX4_MARK,
TSIF2_TS_XX5_MARK,
TSIF1_TS_XX1_MARK,
TSIF1_TS_XX2_MARK,
TSIF1_TS_XX3_MARK,
TSIF1_TS_XX4_MARK,
TSIF1_TS_XX5_MARK,
TSIF0_TS_XX1_MARK,
TSIF0_TS_XX2_MARK,
TSIF0_TS_XX3_MARK,
TSIF0_TS_XX4_MARK,
TSIF0_TS_XX5_MARK,
MST1_TS_XX1_MARK,
MST1_TS_XX2_MARK,
MST1_TS_XX3_MARK,
MST1_TS_XX4_MARK,
MST1_TS_XX5_MARK,
MST0_TS_XX1_MARK,
MST0_TS_XX2_MARK,
MST0_TS_XX3_MARK,
MST0_TS_XX4_MARK,
MST0_TS_XX5_MARK,
/* MSEL3 special cases */
SDHI0_VCCQ_MC0_ON_MARK,
SDHI0_VCCQ_MC0_OFF_MARK,
DEBUG_MON_VIO_MARK,
DEBUG_MON_LCDD_MARK,
LCDC_LCDC0_MARK,
LCDC_LCDC1_MARK,
/* MSEL4 special cases */
IRQ9_MEM_INT_MARK,
IRQ9_MCP_INT_MARK,
A11_MARK,
KEYOUT8_MARK,
TPU4TO3_MARK,
RESETA_N_PU_ON_MARK,
RESETA_N_PU_OFF_MARK,
EDBGREQ_PD_MARK,
EDBGREQ_PU_MARK,
PINMUX_MARK_END,
};
static const u16 pinmux_data[] = {
/* specify valid pin states for each pin in GPIO mode */
PINMUX_DATA_ALL(),
/* Table 25-1 (Function 0-7) */
PINMUX_DATA(VBUS_0_MARK, PORT0_FN1),
PINMUX_DATA(GPI0_MARK, PORT1_FN1),
PINMUX_DATA(GPI1_MARK, PORT2_FN1),
PINMUX_DATA(GPI2_MARK, PORT3_FN1),
PINMUX_DATA(GPI3_MARK, PORT4_FN1),
PINMUX_DATA(GPI4_MARK, PORT5_FN1),
PINMUX_DATA(GPI5_MARK, PORT6_FN1),
PINMUX_DATA(GPI6_MARK, PORT7_FN1),
PINMUX_DATA(GPI7_MARK, PORT8_FN1),
PINMUX_DATA(SCIFA7_RXD_MARK, PORT12_FN2),
PINMUX_DATA(SCIFA7_CTS__MARK, PORT13_FN2),
PINMUX_DATA(GPO7_MARK, PORT14_FN1), \
PINMUX_DATA(MFG0_OUT2_MARK, PORT14_FN4),
PINMUX_DATA(GPO6_MARK, PORT15_FN1), \
PINMUX_DATA(MFG1_OUT2_MARK, PORT15_FN4),
PINMUX_DATA(GPO5_MARK, PORT16_FN1), \
PINMUX_DATA(SCIFA0_SCK_MARK, PORT16_FN2), \
PINMUX_DATA(FSICOSLDT3_MARK, PORT16_FN3), \
PINMUX_DATA(PORT16_VIO_CKOR_MARK, PORT16_FN4),
PINMUX_DATA(SCIFA0_TXD_MARK, PORT17_FN2),
PINMUX_DATA(SCIFA7_TXD_MARK, PORT18_FN2),
PINMUX_DATA(SCIFA7_RTS__MARK, PORT19_FN2), \
PINMUX_DATA(PORT19_VIO_CKO2_MARK, PORT19_FN3),
PINMUX_DATA(GPO0_MARK, PORT20_FN1),
PINMUX_DATA(GPO1_MARK, PORT21_FN1),
PINMUX_DATA(GPO2_MARK, PORT22_FN1), \
PINMUX_DATA(STATUS0_MARK, PORT22_FN2),
PINMUX_DATA(GPO3_MARK, PORT23_FN1), \
PINMUX_DATA(STATUS1_MARK, PORT23_FN2),
PINMUX_DATA(GPO4_MARK, PORT24_FN1), \
PINMUX_DATA(STATUS2_MARK, PORT24_FN2),
PINMUX_DATA(VINT_MARK, PORT25_FN1),
PINMUX_DATA(TCKON_MARK, PORT26_FN1),
PINMUX_DATA(XDVFS1_MARK, PORT27_FN1), \
PINMUX_DATA(PORT27_I2C_SCL2_MARK, PORT27_FN2, MSEL2CR_MSEL17_0,
MSEL2CR_MSEL16_1), \
PINMUX_DATA(PORT27_I2C_SCL3_MARK, PORT27_FN3, MSEL2CR_MSEL19_0,
MSEL2CR_MSEL18_1), \
PINMUX_DATA(MFG0_OUT1_MARK, PORT27_FN4), \
PINMUX_DATA(PORT27_IROUT_MARK, PORT27_FN7),
PINMUX_DATA(XDVFS2_MARK, PORT28_FN1), \
PINMUX_DATA(PORT28_I2C_SDA2_MARK, PORT28_FN2, MSEL2CR_MSEL17_0,
MSEL2CR_MSEL16_1), \
PINMUX_DATA(PORT28_I2C_SDA3_MARK, PORT28_FN3, MSEL2CR_MSEL19_0,
MSEL2CR_MSEL18_1), \
PINMUX_DATA(PORT28_TPU1TO1_MARK, PORT28_FN7),
PINMUX_DATA(SIM_RST_MARK, PORT29_FN1), \
PINMUX_DATA(PORT29_TPU1TO1_MARK, PORT29_FN4),
PINMUX_DATA(SIM_CLK_MARK, PORT30_FN1), \
PINMUX_DATA(PORT30_VIO_CKOR_MARK, PORT30_FN4),
PINMUX_DATA(SIM_D_MARK, PORT31_FN1), \
PINMUX_DATA(PORT31_IROUT_MARK, PORT31_FN4),
PINMUX_DATA(SCIFA4_TXD_MARK, PORT32_FN2),
PINMUX_DATA(SCIFA4_RXD_MARK, PORT33_FN2), \
PINMUX_DATA(XWUP_MARK, PORT33_FN3),
PINMUX_DATA(SCIFA4_RTS__MARK, PORT34_FN2),
PINMUX_DATA(SCIFA4_CTS__MARK, PORT35_FN2),
PINMUX_DATA(FSIBOBT_MARK, PORT36_FN1), \
PINMUX_DATA(FSIBIBT_MARK, PORT36_FN2),
PINMUX_DATA(FSIBOLR_MARK, PORT37_FN1), \
PINMUX_DATA(FSIBILR_MARK, PORT37_FN2),
PINMUX_DATA(FSIBOSLD_MARK, PORT38_FN1),
PINMUX_DATA(FSIBISLD_MARK, PORT39_FN1),
PINMUX_DATA(VACK_MARK, PORT40_FN1),
PINMUX_DATA(XTAL1L_MARK, PORT41_FN1),
PINMUX_DATA(SCIFA0_RTS__MARK, PORT42_FN2), \
PINMUX_DATA(FSICOSLDT2_MARK, PORT42_FN3),
PINMUX_DATA(SCIFA0_RXD_MARK, PORT43_FN2),
PINMUX_DATA(SCIFA0_CTS__MARK, PORT44_FN2), \
PINMUX_DATA(FSICOSLDT1_MARK, PORT44_FN3),
PINMUX_DATA(FSICOBT_MARK, PORT45_FN1), \
PINMUX_DATA(FSICIBT_MARK, PORT45_FN2), \
PINMUX_DATA(FSIDOBT_MARK, PORT45_FN3), \
PINMUX_DATA(FSIDIBT_MARK, PORT45_FN4),
PINMUX_DATA(FSICOLR_MARK, PORT46_FN1), \
PINMUX_DATA(FSICILR_MARK, PORT46_FN2), \
PINMUX_DATA(FSIDOLR_MARK, PORT46_FN3), \
PINMUX_DATA(FSIDILR_MARK, PORT46_FN4),
PINMUX_DATA(FSICOSLD_MARK, PORT47_FN1), \
PINMUX_DATA(PORT47_FSICSPDIF_MARK, PORT47_FN2),
PINMUX_DATA(FSICISLD_MARK, PORT48_FN1), \
PINMUX_DATA(FSIDISLD_MARK, PORT48_FN3),
PINMUX_DATA(FSIACK_MARK, PORT49_FN1), \
PINMUX_DATA(PORT49_IRDA_OUT_MARK, PORT49_FN2, MSEL4CR_MSEL19_1), \
PINMUX_DATA(PORT49_IROUT_MARK, PORT49_FN4), \
PINMUX_DATA(FSIAOMC_MARK, PORT49_FN5),
PINMUX_DATA(FSIAOLR_MARK, PORT50_FN1), \
PINMUX_DATA(BBIF2_TSYNC2_MARK, PORT50_FN2), \
PINMUX_DATA(TPU2TO2_MARK, PORT50_FN3), \
PINMUX_DATA(FSIAILR_MARK, PORT50_FN5),
PINMUX_DATA(FSIAOBT_MARK, PORT51_FN1), \
PINMUX_DATA(BBIF2_TSCK2_MARK, PORT51_FN2), \
PINMUX_DATA(TPU2TO3_MARK, PORT51_FN3), \
PINMUX_DATA(FSIAIBT_MARK, PORT51_FN5),
PINMUX_DATA(FSIAOSLD_MARK, PORT52_FN1), \
PINMUX_DATA(BBIF2_TXD2_MARK, PORT52_FN2),
PINMUX_DATA(FSIASPDIF_MARK, PORT53_FN1), \
PINMUX_DATA(PORT53_IRDA_IN_MARK, PORT53_FN2, MSEL4CR_MSEL19_1), \
PINMUX_DATA(TPU3TO3_MARK, PORT53_FN3), \
PINMUX_DATA(FSIBSPDIF_MARK, PORT53_FN5), \
PINMUX_DATA(PORT53_FSICSPDIF_MARK, PORT53_FN6),
PINMUX_DATA(FSIBCK_MARK, PORT54_FN1), \
PINMUX_DATA(PORT54_IRDA_FIRSEL_MARK, PORT54_FN2, MSEL4CR_MSEL19_1), \
PINMUX_DATA(TPU3TO2_MARK, PORT54_FN3), \
PINMUX_DATA(FSIBOMC_MARK, PORT54_FN5), \
PINMUX_DATA(FSICCK_MARK, PORT54_FN6), \
PINMUX_DATA(FSICOMC_MARK, PORT54_FN7),
PINMUX_DATA(FSIAISLD_MARK, PORT55_FN1), \
PINMUX_DATA(TPU0TO0_MARK, PORT55_FN3),
PINMUX_DATA(A0_MARK, PORT57_FN1), \
PINMUX_DATA(BS__MARK, PORT57_FN2),
PINMUX_DATA(A12_MARK, PORT58_FN1), \
PINMUX_DATA(PORT58_KEYOUT7_MARK, PORT58_FN2), \
PINMUX_DATA(TPU4TO2_MARK, PORT58_FN4),
PINMUX_DATA(A13_MARK, PORT59_FN1), \
PINMUX_DATA(PORT59_KEYOUT6_MARK, PORT59_FN2), \
PINMUX_DATA(TPU0TO1_MARK, PORT59_FN4),
PINMUX_DATA(A14_MARK, PORT60_FN1), \
PINMUX_DATA(KEYOUT5_MARK, PORT60_FN2),
PINMUX_DATA(A15_MARK, PORT61_FN1), \
PINMUX_DATA(KEYOUT4_MARK, PORT61_FN2),
PINMUX_DATA(A16_MARK, PORT62_FN1), \
PINMUX_DATA(KEYOUT3_MARK, PORT62_FN2), \
PINMUX_DATA(MSIOF0_SS1_MARK, PORT62_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A17_MARK, PORT63_FN1), \
PINMUX_DATA(KEYOUT2_MARK, PORT63_FN2), \
PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT63_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A18_MARK, PORT64_FN1), \
PINMUX_DATA(KEYOUT1_MARK, PORT64_FN2), \
PINMUX_DATA(MSIOF0_TSCK_MARK, PORT64_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A19_MARK, PORT65_FN1), \
PINMUX_DATA(KEYOUT0_MARK, PORT65_FN2), \
PINMUX_DATA(MSIOF0_TXD_MARK, PORT65_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A20_MARK, PORT66_FN1), \
PINMUX_DATA(KEYIN0_MARK, PORT66_FN2), \
PINMUX_DATA(MSIOF0_RSCK_MARK, PORT66_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A21_MARK, PORT67_FN1), \
PINMUX_DATA(KEYIN1_MARK, PORT67_FN2), \
PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT67_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A22_MARK, PORT68_FN1), \
PINMUX_DATA(KEYIN2_MARK, PORT68_FN2), \
PINMUX_DATA(MSIOF0_MCK0_MARK, PORT68_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A23_MARK, PORT69_FN1), \
PINMUX_DATA(KEYIN3_MARK, PORT69_FN2), \
PINMUX_DATA(MSIOF0_MCK1_MARK, PORT69_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A24_MARK, PORT70_FN1), \
PINMUX_DATA(KEYIN4_MARK, PORT70_FN2), \
PINMUX_DATA(MSIOF0_RXD_MARK, PORT70_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A25_MARK, PORT71_FN1), \
PINMUX_DATA(KEYIN5_MARK, PORT71_FN2), \
PINMUX_DATA(MSIOF0_SS2_MARK, PORT71_FN4, MSEL3CR_MSEL11_0),
PINMUX_DATA(A26_MARK, PORT72_FN1), \
PINMUX_DATA(KEYIN6_MARK, PORT72_FN2),
PINMUX_DATA(KEYIN7_MARK, PORT73_FN2),
PINMUX_DATA(D0_NAF0_MARK, PORT74_FN1),
PINMUX_DATA(D1_NAF1_MARK, PORT75_FN1),
PINMUX_DATA(D2_NAF2_MARK, PORT76_FN1),
PINMUX_DATA(D3_NAF3_MARK, PORT77_FN1),
PINMUX_DATA(D4_NAF4_MARK, PORT78_FN1),
PINMUX_DATA(D5_NAF5_MARK, PORT79_FN1),
PINMUX_DATA(D6_NAF6_MARK, PORT80_FN1),
PINMUX_DATA(D7_NAF7_MARK, PORT81_FN1),
PINMUX_DATA(D8_NAF8_MARK, PORT82_FN1),
PINMUX_DATA(D9_NAF9_MARK, PORT83_FN1),
PINMUX_DATA(D10_NAF10_MARK, PORT84_FN1),
PINMUX_DATA(D11_NAF11_MARK, PORT85_FN1),
PINMUX_DATA(D12_NAF12_MARK, PORT86_FN1),
PINMUX_DATA(D13_NAF13_MARK, PORT87_FN1),
PINMUX_DATA(D14_NAF14_MARK, PORT88_FN1),
PINMUX_DATA(D15_NAF15_MARK, PORT89_FN1),
PINMUX_DATA(CS4__MARK, PORT90_FN1),
PINMUX_DATA(CS5A__MARK, PORT91_FN1), \
PINMUX_DATA(PORT91_RDWR_MARK, PORT91_FN2),
PINMUX_DATA(CS5B__MARK, PORT92_FN1), \
PINMUX_DATA(FCE1__MARK, PORT92_FN2),
PINMUX_DATA(CS6B__MARK, PORT93_FN1), \
PINMUX_DATA(DACK0_MARK, PORT93_FN4),
PINMUX_DATA(FCE0__MARK, PORT94_FN1), \
PINMUX_DATA(CS6A__MARK, PORT94_FN2),
PINMUX_DATA(WAIT__MARK, PORT95_FN1), \
PINMUX_DATA(DREQ0_MARK, PORT95_FN2),
PINMUX_DATA(RD__FSC_MARK, PORT96_FN1),
PINMUX_DATA(WE0__FWE_MARK, PORT97_FN1), \
PINMUX_DATA(RDWR_FWE_MARK, PORT97_FN2),
PINMUX_DATA(WE1__MARK, PORT98_FN1),
PINMUX_DATA(FRB_MARK, PORT99_FN1),
PINMUX_DATA(CKO_MARK, PORT100_FN1),
PINMUX_DATA(NBRSTOUT__MARK, PORT101_FN1),
PINMUX_DATA(NBRST__MARK, PORT102_FN1),
PINMUX_DATA(BBIF2_TXD_MARK, PORT103_FN3),
PINMUX_DATA(BBIF2_RXD_MARK, PORT104_FN3),
PINMUX_DATA(BBIF2_SYNC_MARK, PORT105_FN3),
PINMUX_DATA(BBIF2_SCK_MARK, PORT106_FN3),
PINMUX_DATA(SCIFA3_CTS__MARK, PORT107_FN3), \
PINMUX_DATA(MFG3_IN2_MARK, PORT107_FN4),
PINMUX_DATA(SCIFA3_RXD_MARK, PORT108_FN3), \
PINMUX_DATA(MFG3_IN1_MARK, PORT108_FN4),
PINMUX_DATA(BBIF1_SS2_MARK, PORT109_FN2), \
PINMUX_DATA(SCIFA3_RTS__MARK, PORT109_FN3), \
PINMUX_DATA(MFG3_OUT1_MARK, PORT109_FN4),
PINMUX_DATA(SCIFA3_TXD_MARK, PORT110_FN3),
PINMUX_DATA(HSI_RX_DATA_MARK, PORT111_FN1), \
PINMUX_DATA(BBIF1_RXD_MARK, PORT111_FN3),
PINMUX_DATA(HSI_TX_WAKE_MARK, PORT112_FN1), \
PINMUX_DATA(BBIF1_TSCK_MARK, PORT112_FN3),
PINMUX_DATA(HSI_TX_DATA_MARK, PORT113_FN1), \
PINMUX_DATA(BBIF1_TSYNC_MARK, PORT113_FN3),
PINMUX_DATA(HSI_TX_READY_MARK, PORT114_FN1), \
PINMUX_DATA(BBIF1_TXD_MARK, PORT114_FN3),
PINMUX_DATA(HSI_RX_READY_MARK, PORT115_FN1), \
PINMUX_DATA(BBIF1_RSCK_MARK, PORT115_FN3), \
PINMUX_DATA(PORT115_I2C_SCL2_MARK, PORT115_FN5, MSEL2CR_MSEL17_1), \
PINMUX_DATA(PORT115_I2C_SCL3_MARK, PORT115_FN6, MSEL2CR_MSEL19_1),
PINMUX_DATA(HSI_RX_WAKE_MARK, PORT116_FN1), \
PINMUX_DATA(BBIF1_RSYNC_MARK, PORT116_FN3), \
PINMUX_DATA(PORT116_I2C_SDA2_MARK, PORT116_FN5, MSEL2CR_MSEL17_1), \
PINMUX_DATA(PORT116_I2C_SDA3_MARK, PORT116_FN6, MSEL2CR_MSEL19_1),
PINMUX_DATA(HSI_RX_FLAG_MARK, PORT117_FN1), \
PINMUX_DATA(BBIF1_SS1_MARK, PORT117_FN2), \
PINMUX_DATA(BBIF1_FLOW_MARK, PORT117_FN3),
PINMUX_DATA(HSI_TX_FLAG_MARK, PORT118_FN1),
PINMUX_DATA(VIO_VD_MARK, PORT128_FN1), \
PINMUX_DATA(PORT128_LCD2VSYN_MARK, PORT128_FN4, MSEL3CR_MSEL2_0), \
PINMUX_DATA(VIO2_VD_MARK, PORT128_FN6, MSEL4CR_MSEL27_0), \
PINMUX_DATA(LCD2D0_MARK, PORT128_FN7),
PINMUX_DATA(VIO_HD_MARK, PORT129_FN1), \
PINMUX_DATA(PORT129_LCD2HSYN_MARK, PORT129_FN4), \
PINMUX_DATA(PORT129_LCD2CS__MARK, PORT129_FN5), \
PINMUX_DATA(VIO2_HD_MARK, PORT129_FN6, MSEL4CR_MSEL27_0), \
PINMUX_DATA(LCD2D1_MARK, PORT129_FN7),
PINMUX_DATA(VIO_D0_MARK, PORT130_FN1), \
PINMUX_DATA(PORT130_MSIOF2_RXD_MARK, PORT130_FN3, MSEL4CR_MSEL11_0,
MSEL4CR_MSEL10_1), \
PINMUX_DATA(LCD2D10_MARK, PORT130_FN7),
PINMUX_DATA(VIO_D1_MARK, PORT131_FN1), \
PINMUX_DATA(PORT131_KEYOUT6_MARK, PORT131_FN2), \
PINMUX_DATA(PORT131_MSIOF2_SS1_MARK, PORT131_FN3), \
PINMUX_DATA(PORT131_KEYOUT11_MARK, PORT131_FN4), \
PINMUX_DATA(LCD2D11_MARK, PORT131_FN7),
PINMUX_DATA(VIO_D2_MARK, PORT132_FN1), \
PINMUX_DATA(PORT132_KEYOUT7_MARK, PORT132_FN2), \
PINMUX_DATA(PORT132_MSIOF2_SS2_MARK, PORT132_FN3), \
PINMUX_DATA(PORT132_KEYOUT10_MARK, PORT132_FN4), \
PINMUX_DATA(LCD2D12_MARK, PORT132_FN7),
PINMUX_DATA(VIO_D3_MARK, PORT133_FN1), \
PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT133_FN3, MSEL4CR_MSEL11_0), \
PINMUX_DATA(LCD2D13_MARK, PORT133_FN7),
PINMUX_DATA(VIO_D4_MARK, PORT134_FN1), \
PINMUX_DATA(MSIOF2_TXD_MARK, PORT134_FN3, MSEL4CR_MSEL11_0), \
PINMUX_DATA(LCD2D14_MARK, PORT134_FN7),
PINMUX_DATA(VIO_D5_MARK, PORT135_FN1), \
PINMUX_DATA(MSIOF2_TSCK_MARK, PORT135_FN3, MSEL4CR_MSEL11_0), \
PINMUX_DATA(LCD2D15_MARK, PORT135_FN7),
PINMUX_DATA(VIO_D6_MARK, PORT136_FN1), \
PINMUX_DATA(PORT136_KEYOUT8_MARK, PORT136_FN2), \
PINMUX_DATA(LCD2D16_MARK, PORT136_FN7),
PINMUX_DATA(VIO_D7_MARK, PORT137_FN1), \
PINMUX_DATA(PORT137_KEYOUT9_MARK, PORT137_FN2), \
PINMUX_DATA(LCD2D17_MARK, PORT137_FN7),
PINMUX_DATA(VIO_D8_MARK, PORT138_FN1), \
PINMUX_DATA(PORT138_KEYOUT8_MARK, PORT138_FN2), \
PINMUX_DATA(VIO2_D0_MARK, PORT138_FN6), \
PINMUX_DATA(LCD2D6_MARK, PORT138_FN7),
PINMUX_DATA(VIO_D9_MARK, PORT139_FN1), \
PINMUX_DATA(PORT139_KEYOUT9_MARK, PORT139_FN2), \
PINMUX_DATA(VIO2_D1_MARK, PORT139_FN6), \
PINMUX_DATA(LCD2D7_MARK, PORT139_FN7),
PINMUX_DATA(VIO_D10_MARK, PORT140_FN1), \
PINMUX_DATA(TPU0TO2_MARK, PORT140_FN4), \
PINMUX_DATA(VIO2_D2_MARK, PORT140_FN6), \
PINMUX_DATA(LCD2D8_MARK, PORT140_FN7),
PINMUX_DATA(VIO_D11_MARK, PORT141_FN1), \
PINMUX_DATA(TPU0TO3_MARK, PORT141_FN4), \
PINMUX_DATA(VIO2_D3_MARK, PORT141_FN6), \
PINMUX_DATA(LCD2D9_MARK, PORT141_FN7),
PINMUX_DATA(VIO_D12_MARK, PORT142_FN1), \
PINMUX_DATA(PORT142_KEYOUT10_MARK, PORT142_FN2), \
PINMUX_DATA(VIO2_D4_MARK, PORT142_FN6), \
PINMUX_DATA(LCD2D2_MARK, PORT142_FN7),
PINMUX_DATA(VIO_D13_MARK, PORT143_FN1), \
PINMUX_DATA(PORT143_KEYOUT11_MARK, PORT143_FN2), \
PINMUX_DATA(PORT143_KEYOUT6_MARK, PORT143_FN3), \
PINMUX_DATA(VIO2_D5_MARK, PORT143_FN6), \
PINMUX_DATA(LCD2D3_MARK, PORT143_FN7),
PINMUX_DATA(VIO_D14_MARK, PORT144_FN1), \
PINMUX_DATA(PORT144_KEYOUT7_MARK, PORT144_FN2), \
PINMUX_DATA(VIO2_D6_MARK, PORT144_FN6), \
PINMUX_DATA(LCD2D4_MARK, PORT144_FN7),
PINMUX_DATA(VIO_D15_MARK, PORT145_FN1), \
PINMUX_DATA(TPU1TO3_MARK, PORT145_FN3), \
PINMUX_DATA(PORT145_LCD2DISP_MARK, PORT145_FN4), \
PINMUX_DATA(PORT145_LCD2RS_MARK, PORT145_FN5), \
PINMUX_DATA(VIO2_D7_MARK, PORT145_FN6), \
PINMUX_DATA(LCD2D5_MARK, PORT145_FN7),
PINMUX_DATA(VIO_CLK_MARK, PORT146_FN1), \
PINMUX_DATA(LCD2DCK_MARK, PORT146_FN4), \
PINMUX_DATA(PORT146_LCD2WR__MARK, PORT146_FN5), \
PINMUX_DATA(VIO2_CLK_MARK, PORT146_FN6, MSEL4CR_MSEL27_0), \
PINMUX_DATA(LCD2D18_MARK, PORT146_FN7),
PINMUX_DATA(VIO_FIELD_MARK, PORT147_FN1), \
PINMUX_DATA(LCD2RD__MARK, PORT147_FN4), \
PINMUX_DATA(VIO2_FIELD_MARK, PORT147_FN6, MSEL4CR_MSEL27_0), \
PINMUX_DATA(LCD2D19_MARK, PORT147_FN7),
PINMUX_DATA(VIO_CKO_MARK, PORT148_FN1),
PINMUX_DATA(A27_MARK, PORT149_FN1), \
PINMUX_DATA(PORT149_RDWR_MARK, PORT149_FN2), \
PINMUX_DATA(MFG0_IN1_MARK, PORT149_FN3), \
PINMUX_DATA(PORT149_KEYOUT9_MARK, PORT149_FN4),
PINMUX_DATA(MFG0_IN2_MARK, PORT150_FN3),
PINMUX_DATA(TS_SPSYNC3_MARK, PORT151_FN4), \
PINMUX_DATA(MSIOF2_RSCK_MARK, PORT151_FN5),
PINMUX_DATA(TS_SDAT3_MARK, PORT152_FN4), \
PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT152_FN5),
PINMUX_DATA(TPU1TO2_MARK, PORT153_FN3), \
PINMUX_DATA(TS_SDEN3_MARK, PORT153_FN4), \
PINMUX_DATA(PORT153_MSIOF2_SS1_MARK, PORT153_FN5),
PINMUX_DATA(SCIFA2_TXD1_MARK, PORT154_FN2, MSEL3CR_MSEL9_0), \
PINMUX_DATA(MSIOF2_MCK0_MARK, PORT154_FN5),
PINMUX_DATA(SCIFA2_RXD1_MARK, PORT155_FN2, MSEL3CR_MSEL9_0), \
PINMUX_DATA(MSIOF2_MCK1_MARK, PORT155_FN5),
PINMUX_DATA(SCIFA2_RTS1__MARK, PORT156_FN2, MSEL3CR_MSEL9_0), \
PINMUX_DATA(PORT156_MSIOF2_SS2_MARK, PORT156_FN5),
PINMUX_DATA(SCIFA2_CTS1__MARK, PORT157_FN2, MSEL3CR_MSEL9_0), \
PINMUX_DATA(PORT157_MSIOF2_RXD_MARK, PORT157_FN5, MSEL4CR_MSEL11_0,
MSEL4CR_MSEL10_0),
PINMUX_DATA(DINT__MARK, PORT158_FN1), \
PINMUX_DATA(SCIFA2_SCK1_MARK, PORT158_FN2, MSEL3CR_MSEL9_0), \
PINMUX_DATA(TS_SCK3_MARK, PORT158_FN4),
PINMUX_DATA(PORT159_SCIFB_SCK_MARK, PORT159_FN1, MSEL4CR_MSEL22_0), \
PINMUX_DATA(PORT159_SCIFA5_SCK_MARK, PORT159_FN2, MSEL4CR_MSEL21_1), \
PINMUX_DATA(NMI_MARK, PORT159_FN3),
PINMUX_DATA(PORT160_SCIFB_TXD_MARK, PORT160_FN1, MSEL4CR_MSEL22_0), \
PINMUX_DATA(PORT160_SCIFA5_TXD_MARK, PORT160_FN2, MSEL4CR_MSEL21_1),
PINMUX_DATA(PORT161_SCIFB_CTS__MARK, PORT161_FN1, MSEL4CR_MSEL22_0), \
PINMUX_DATA(PORT161_SCIFA5_CTS__MARK, PORT161_FN2, MSEL4CR_MSEL21_1),
PINMUX_DATA(PORT162_SCIFB_RXD_MARK, PORT162_FN1, MSEL4CR_MSEL22_0), \
PINMUX_DATA(PORT162_SCIFA5_RXD_MARK, PORT162_FN2, MSEL4CR_MSEL21_1),
PINMUX_DATA(PORT163_SCIFB_RTS__MARK, PORT163_FN1, MSEL4CR_MSEL22_0), \
PINMUX_DATA(PORT163_SCIFA5_RTS__MARK, PORT163_FN2, MSEL4CR_MSEL21_1), \
PINMUX_DATA(TPU3TO0_MARK, PORT163_FN5),
PINMUX_DATA(LCDD0_MARK, PORT192_FN1),
PINMUX_DATA(LCDD1_MARK, PORT193_FN1), \
PINMUX_DATA(PORT193_SCIFA5_CTS__MARK, PORT193_FN3, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_1), \
PINMUX_DATA(BBIF2_TSYNC1_MARK, PORT193_FN5),
PINMUX_DATA(LCDD2_MARK, PORT194_FN1), \
PINMUX_DATA(PORT194_SCIFA5_RTS__MARK, PORT194_FN3, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_1), \
PINMUX_DATA(BBIF2_TSCK1_MARK, PORT194_FN5),
PINMUX_DATA(LCDD3_MARK, PORT195_FN1), \
PINMUX_DATA(PORT195_SCIFA5_RXD_MARK, PORT195_FN3, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_1), \
PINMUX_DATA(BBIF2_TXD1_MARK, PORT195_FN5),
PINMUX_DATA(LCDD4_MARK, PORT196_FN1), \
PINMUX_DATA(PORT196_SCIFA5_TXD_MARK, PORT196_FN3, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_1),
PINMUX_DATA(LCDD5_MARK, PORT197_FN1), \
PINMUX_DATA(PORT197_SCIFA5_SCK_MARK, PORT197_FN3, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_1), \
PINMUX_DATA(MFG2_OUT2_MARK, PORT197_FN5), \
PINMUX_DATA(TPU2TO1_MARK, PORT197_FN7),
PINMUX_DATA(LCDD6_MARK, PORT198_FN1),
PINMUX_DATA(LCDD7_MARK, PORT199_FN1), \
PINMUX_DATA(TPU4TO1_MARK, PORT199_FN2), \
PINMUX_DATA(MFG4_OUT2_MARK, PORT199_FN5),
PINMUX_DATA(LCDD8_MARK, PORT200_FN1), \
PINMUX_DATA(D16_MARK, PORT200_FN6),
PINMUX_DATA(LCDD9_MARK, PORT201_FN1), \
PINMUX_DATA(D17_MARK, PORT201_FN6),
PINMUX_DATA(LCDD10_MARK, PORT202_FN1), \
PINMUX_DATA(D18_MARK, PORT202_FN6),
PINMUX_DATA(LCDD11_MARK, PORT203_FN1), \
PINMUX_DATA(D19_MARK, PORT203_FN6),
PINMUX_DATA(LCDD12_MARK, PORT204_FN1), \
PINMUX_DATA(D20_MARK, PORT204_FN6),
PINMUX_DATA(LCDD13_MARK, PORT205_FN1), \
PINMUX_DATA(D21_MARK, PORT205_FN6),
PINMUX_DATA(LCDD14_MARK, PORT206_FN1), \
PINMUX_DATA(D22_MARK, PORT206_FN6),
PINMUX_DATA(LCDD15_MARK, PORT207_FN1), \
PINMUX_DATA(PORT207_MSIOF0L_SS1_MARK, PORT207_FN2, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D23_MARK, PORT207_FN6),
PINMUX_DATA(LCDD16_MARK, PORT208_FN1), \
PINMUX_DATA(PORT208_MSIOF0L_SS2_MARK, PORT208_FN2, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D24_MARK, PORT208_FN6),
PINMUX_DATA(LCDD17_MARK, PORT209_FN1), \
PINMUX_DATA(D25_MARK, PORT209_FN6),
PINMUX_DATA(LCDD18_MARK, PORT210_FN1), \
PINMUX_DATA(DREQ2_MARK, PORT210_FN2), \
PINMUX_DATA(PORT210_MSIOF0L_SS1_MARK, PORT210_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D26_MARK, PORT210_FN6),
PINMUX_DATA(LCDD19_MARK, PORT211_FN1), \
PINMUX_DATA(PORT211_MSIOF0L_SS2_MARK, PORT211_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D27_MARK, PORT211_FN6),
PINMUX_DATA(LCDD20_MARK, PORT212_FN1), \
PINMUX_DATA(TS_SPSYNC1_MARK, PORT212_FN2), \
PINMUX_DATA(MSIOF0L_MCK0_MARK, PORT212_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D28_MARK, PORT212_FN6),
PINMUX_DATA(LCDD21_MARK, PORT213_FN1), \
PINMUX_DATA(TS_SDAT1_MARK, PORT213_FN2), \
PINMUX_DATA(MSIOF0L_MCK1_MARK, PORT213_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D29_MARK, PORT213_FN6),
PINMUX_DATA(LCDD22_MARK, PORT214_FN1), \
PINMUX_DATA(TS_SDEN1_MARK, PORT214_FN2), \
PINMUX_DATA(MSIOF0L_RSCK_MARK, PORT214_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D30_MARK, PORT214_FN6),
PINMUX_DATA(LCDD23_MARK, PORT215_FN1), \
PINMUX_DATA(TS_SCK1_MARK, PORT215_FN2), \
PINMUX_DATA(MSIOF0L_RSYNC_MARK, PORT215_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(D31_MARK, PORT215_FN6),
PINMUX_DATA(LCDDCK_MARK, PORT216_FN1), \
PINMUX_DATA(LCDWR__MARK, PORT216_FN2),
PINMUX_DATA(LCDRD__MARK, PORT217_FN1), \
PINMUX_DATA(DACK2_MARK, PORT217_FN2), \
PINMUX_DATA(PORT217_LCD2RS_MARK, PORT217_FN3), \
PINMUX_DATA(MSIOF0L_TSYNC_MARK, PORT217_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(VIO2_FIELD3_MARK, PORT217_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_1), \
PINMUX_DATA(PORT217_LCD2DISP_MARK, PORT217_FN7),
PINMUX_DATA(LCDHSYN_MARK, PORT218_FN1), \
PINMUX_DATA(LCDCS__MARK, PORT218_FN2), \
PINMUX_DATA(LCDCS2__MARK, PORT218_FN3), \
PINMUX_DATA(DACK3_MARK, PORT218_FN4), \
PINMUX_DATA(PORT218_VIO_CKOR_MARK, PORT218_FN5),
PINMUX_DATA(LCDDISP_MARK, PORT219_FN1), \
PINMUX_DATA(LCDRS_MARK, PORT219_FN2), \
PINMUX_DATA(PORT219_LCD2WR__MARK, PORT219_FN3), \
PINMUX_DATA(DREQ3_MARK, PORT219_FN4), \
PINMUX_DATA(MSIOF0L_TSCK_MARK, PORT219_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(VIO2_CLK3_MARK, PORT219_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_1), \
PINMUX_DATA(LCD2DCK_2_MARK, PORT219_FN7),
PINMUX_DATA(LCDVSYN_MARK, PORT220_FN1), \
PINMUX_DATA(LCDVSYN2_MARK, PORT220_FN2),
PINMUX_DATA(LCDLCLK_MARK, PORT221_FN1), \
PINMUX_DATA(DREQ1_MARK, PORT221_FN2), \
PINMUX_DATA(PORT221_LCD2CS__MARK, PORT221_FN3), \
PINMUX_DATA(PWEN_MARK, PORT221_FN4), \
PINMUX_DATA(MSIOF0L_RXD_MARK, PORT221_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(VIO2_HD3_MARK, PORT221_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_1), \
PINMUX_DATA(PORT221_LCD2HSYN_MARK, PORT221_FN7),
PINMUX_DATA(LCDDON_MARK, PORT222_FN1), \
PINMUX_DATA(LCDDON2_MARK, PORT222_FN2), \
PINMUX_DATA(DACK1_MARK, PORT222_FN3), \
PINMUX_DATA(OVCN_MARK, PORT222_FN4), \
PINMUX_DATA(MSIOF0L_TXD_MARK, PORT222_FN5, MSEL3CR_MSEL11_1), \
PINMUX_DATA(VIO2_VD3_MARK, PORT222_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_1), \
PINMUX_DATA(PORT222_LCD2VSYN_MARK, PORT222_FN7, MSEL3CR_MSEL2_1),
PINMUX_DATA(SCIFA1_TXD_MARK, PORT225_FN2), \
PINMUX_DATA(OVCN2_MARK, PORT225_FN4),
PINMUX_DATA(EXTLP_MARK, PORT226_FN1), \
PINMUX_DATA(SCIFA1_SCK_MARK, PORT226_FN2), \
PINMUX_DATA(PORT226_VIO_CKO2_MARK, PORT226_FN5),
PINMUX_DATA(SCIFA1_RTS__MARK, PORT227_FN2), \
PINMUX_DATA(IDIN_MARK, PORT227_FN4),
PINMUX_DATA(SCIFA1_RXD_MARK, PORT228_FN2),
PINMUX_DATA(SCIFA1_CTS__MARK, PORT229_FN2), \
PINMUX_DATA(MFG1_IN1_MARK, PORT229_FN3),
PINMUX_DATA(MSIOF1_TXD_MARK, PORT230_FN1), \
PINMUX_DATA(SCIFA2_TXD2_MARK, PORT230_FN2, MSEL3CR_MSEL9_1),
PINMUX_DATA(MSIOF1_TSYNC_MARK, PORT231_FN1), \
PINMUX_DATA(SCIFA2_CTS2__MARK, PORT231_FN2, MSEL3CR_MSEL9_1),
PINMUX_DATA(MSIOF1_TSCK_MARK, PORT232_FN1), \
PINMUX_DATA(SCIFA2_SCK2_MARK, PORT232_FN2, MSEL3CR_MSEL9_1),
PINMUX_DATA(MSIOF1_RXD_MARK, PORT233_FN1), \
PINMUX_DATA(SCIFA2_RXD2_MARK, PORT233_FN2, MSEL3CR_MSEL9_1),
PINMUX_DATA(MSIOF1_RSCK_MARK, PORT234_FN1), \
PINMUX_DATA(SCIFA2_RTS2__MARK, PORT234_FN2, MSEL3CR_MSEL9_1), \
PINMUX_DATA(VIO2_CLK2_MARK, PORT234_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0), \
PINMUX_DATA(LCD2D20_MARK, PORT234_FN7),
PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT235_FN1), \
PINMUX_DATA(MFG1_IN2_MARK, PORT235_FN3), \
PINMUX_DATA(VIO2_VD2_MARK, PORT235_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0), \
PINMUX_DATA(LCD2D21_MARK, PORT235_FN7),
PINMUX_DATA(MSIOF1_MCK0_MARK, PORT236_FN1), \
PINMUX_DATA(PORT236_I2C_SDA2_MARK, PORT236_FN2, MSEL2CR_MSEL17_0,
MSEL2CR_MSEL16_0),
PINMUX_DATA(MSIOF1_MCK1_MARK, PORT237_FN1), \
PINMUX_DATA(PORT237_I2C_SCL2_MARK, PORT237_FN2, MSEL2CR_MSEL17_0,
MSEL2CR_MSEL16_0),
PINMUX_DATA(MSIOF1_SS1_MARK, PORT238_FN1), \
PINMUX_DATA(VIO2_FIELD2_MARK, PORT238_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0), \
PINMUX_DATA(LCD2D22_MARK, PORT238_FN7),
PINMUX_DATA(MSIOF1_SS2_MARK, PORT239_FN1), \
PINMUX_DATA(VIO2_HD2_MARK, PORT239_FN6, MSEL4CR_MSEL27_1,
MSEL4CR_MSEL26_0), \
PINMUX_DATA(LCD2D23_MARK, PORT239_FN7),
PINMUX_DATA(SCIFA6_TXD_MARK, PORT240_FN1),
PINMUX_DATA(PORT241_IRDA_OUT_MARK, PORT241_FN1, MSEL4CR_MSEL19_0), \
PINMUX_DATA(PORT241_IROUT_MARK, PORT241_FN2), \
PINMUX_DATA(MFG4_OUT1_MARK, PORT241_FN3), \
PINMUX_DATA(TPU4TO0_MARK, PORT241_FN4),
PINMUX_DATA(PORT242_IRDA_IN_MARK, PORT242_FN1, MSEL4CR_MSEL19_0), \
PINMUX_DATA(MFG4_IN2_MARK, PORT242_FN3),
PINMUX_DATA(PORT243_IRDA_FIRSEL_MARK, PORT243_FN1, MSEL4CR_MSEL19_0), \
PINMUX_DATA(PORT243_VIO_CKO2_MARK, PORT243_FN2),
PINMUX_DATA(PORT244_SCIFA5_CTS__MARK, PORT244_FN1, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_0), \
PINMUX_DATA(MFG2_IN1_MARK, PORT244_FN2), \
PINMUX_DATA(PORT244_SCIFB_CTS__MARK, PORT244_FN3, MSEL4CR_MSEL22_1), \
PINMUX_DATA(MSIOF2R_RXD_MARK, PORT244_FN7, MSEL4CR_MSEL11_1),
PINMUX_DATA(PORT245_SCIFA5_RTS__MARK, PORT245_FN1, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_0), \
PINMUX_DATA(MFG2_IN2_MARK, PORT245_FN2), \
PINMUX_DATA(PORT245_SCIFB_RTS__MARK, PORT245_FN3, MSEL4CR_MSEL22_1), \
PINMUX_DATA(MSIOF2R_TXD_MARK, PORT245_FN7, MSEL4CR_MSEL11_1),
PINMUX_DATA(PORT246_SCIFA5_RXD_MARK, PORT246_FN1, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_0), \
PINMUX_DATA(MFG1_OUT1_MARK, PORT246_FN2), \
PINMUX_DATA(PORT246_SCIFB_RXD_MARK, PORT246_FN3, MSEL4CR_MSEL22_1), \
PINMUX_DATA(TPU1TO0_MARK, PORT246_FN4),
PINMUX_DATA(PORT247_SCIFA5_TXD_MARK, PORT247_FN1, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_0), \
PINMUX_DATA(MFG3_OUT2_MARK, PORT247_FN2), \
PINMUX_DATA(PORT247_SCIFB_TXD_MARK, PORT247_FN3, MSEL4CR_MSEL22_1), \
PINMUX_DATA(TPU3TO1_MARK, PORT247_FN4),
PINMUX_DATA(PORT248_SCIFA5_SCK_MARK, PORT248_FN1, MSEL4CR_MSEL21_0,
MSEL4CR_MSEL20_0), \
PINMUX_DATA(MFG2_OUT1_MARK, PORT248_FN2), \
PINMUX_DATA(PORT248_SCIFB_SCK_MARK, PORT248_FN3, MSEL4CR_MSEL22_1), \
PINMUX_DATA(TPU2TO0_MARK, PORT248_FN4), \
PINMUX_DATA(PORT248_I2C_SCL3_MARK, PORT248_FN5, MSEL2CR_MSEL19_0,
MSEL2CR_MSEL18_0), \
PINMUX_DATA(MSIOF2R_TSCK_MARK, PORT248_FN7, MSEL4CR_MSEL11_1),
PINMUX_DATA(PORT249_IROUT_MARK, PORT249_FN1), \
PINMUX_DATA(MFG4_IN1_MARK, PORT249_FN2), \
PINMUX_DATA(PORT249_I2C_SDA3_MARK, PORT249_FN5, MSEL2CR_MSEL19_0,
MSEL2CR_MSEL18_0), \
PINMUX_DATA(MSIOF2R_TSYNC_MARK, PORT249_FN7, MSEL4CR_MSEL11_1),
PINMUX_DATA(SDHICLK0_MARK, PORT250_FN1),
PINMUX_DATA(SDHICD0_MARK, PORT251_FN1),
PINMUX_DATA(SDHID0_0_MARK, PORT252_FN1),
PINMUX_DATA(SDHID0_1_MARK, PORT253_FN1),
PINMUX_DATA(SDHID0_2_MARK, PORT254_FN1),
PINMUX_DATA(SDHID0_3_MARK, PORT255_FN1),
PINMUX_DATA(SDHICMD0_MARK, PORT256_FN1),
PINMUX_DATA(SDHIWP0_MARK, PORT257_FN1),
PINMUX_DATA(SDHICLK1_MARK, PORT258_FN1),
PINMUX_DATA(SDHID1_0_MARK, PORT259_FN1), \
PINMUX_DATA(TS_SPSYNC2_MARK, PORT259_FN3),
PINMUX_DATA(SDHID1_1_MARK, PORT260_FN1), \
PINMUX_DATA(TS_SDAT2_MARK, PORT260_FN3),
PINMUX_DATA(SDHID1_2_MARK, PORT261_FN1), \
PINMUX_DATA(TS_SDEN2_MARK, PORT261_FN3),
PINMUX_DATA(SDHID1_3_MARK, PORT262_FN1), \
PINMUX_DATA(TS_SCK2_MARK, PORT262_FN3),
PINMUX_DATA(SDHICMD1_MARK, PORT263_FN1),
PINMUX_DATA(SDHICLK2_MARK, PORT264_FN1),
PINMUX_DATA(SDHID2_0_MARK, PORT265_FN1), \
PINMUX_DATA(TS_SPSYNC4_MARK, PORT265_FN3),
PINMUX_DATA(SDHID2_1_MARK, PORT266_FN1), \
PINMUX_DATA(TS_SDAT4_MARK, PORT266_FN3),
PINMUX_DATA(SDHID2_2_MARK, PORT267_FN1), \
PINMUX_DATA(TS_SDEN4_MARK, PORT267_FN3),
PINMUX_DATA(SDHID2_3_MARK, PORT268_FN1), \
PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3),
PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1),
PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3),
PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3),
PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3),
PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3),
PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0),
PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \
PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2),
PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1),
PINMUX_DATA(MCP_CKO_MARK, PORT289_FN1), \
PINMUX_DATA(MMCCLK1_MARK, PORT289_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D15_MCP_NAF15_MARK, PORT290_FN1),
PINMUX_DATA(MCP_D14_MCP_NAF14_MARK, PORT291_FN1),
PINMUX_DATA(MCP_D13_MCP_NAF13_MARK, PORT292_FN1),
PINMUX_DATA(MCP_D12_MCP_NAF12_MARK, PORT293_FN1),
PINMUX_DATA(MCP_D11_MCP_NAF11_MARK, PORT294_FN1),
PINMUX_DATA(MCP_D10_MCP_NAF10_MARK, PORT295_FN1),
PINMUX_DATA(MCP_D9_MCP_NAF9_MARK, PORT296_FN1),
PINMUX_DATA(MCP_D8_MCP_NAF8_MARK, PORT297_FN1), \
PINMUX_DATA(MMCCMD1_MARK, PORT297_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D7_MCP_NAF7_MARK, PORT298_FN1), \
PINMUX_DATA(MMCD1_7_MARK, PORT298_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D6_MCP_NAF6_MARK, PORT299_FN1), \
PINMUX_DATA(MMCD1_6_MARK, PORT299_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D5_MCP_NAF5_MARK, PORT300_FN1), \
PINMUX_DATA(MMCD1_5_MARK, PORT300_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D4_MCP_NAF4_MARK, PORT301_FN1), \
PINMUX_DATA(MMCD1_4_MARK, PORT301_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D3_MCP_NAF3_MARK, PORT302_FN1), \
PINMUX_DATA(MMCD1_3_MARK, PORT302_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D2_MCP_NAF2_MARK, PORT303_FN1), \
PINMUX_DATA(MMCD1_2_MARK, PORT303_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D1_MCP_NAF1_MARK, PORT304_FN1), \
PINMUX_DATA(MMCD1_1_MARK, PORT304_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_D0_MCP_NAF0_MARK, PORT305_FN1), \
PINMUX_DATA(MMCD1_0_MARK, PORT305_FN2, MSEL4CR_MSEL15_1),
PINMUX_DATA(MCP_NBRSTOUT__MARK, PORT306_FN1),
PINMUX_DATA(MCP_WE0__MCP_FWE_MARK, PORT309_FN1), \
PINMUX_DATA(MCP_RDWR_MCP_FWE_MARK, PORT309_FN2),
/* MSEL2 special cases */
PINMUX_DATA(TSIF2_TS_XX1_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
MSEL2CR_MSEL12_0),
PINMUX_DATA(TSIF2_TS_XX2_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_0,
MSEL2CR_MSEL12_1),
PINMUX_DATA(TSIF2_TS_XX3_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
MSEL2CR_MSEL12_0),
PINMUX_DATA(TSIF2_TS_XX4_MARK, MSEL2CR_MSEL14_0, MSEL2CR_MSEL13_1,
MSEL2CR_MSEL12_1),
PINMUX_DATA(TSIF2_TS_XX5_MARK, MSEL2CR_MSEL14_1, MSEL2CR_MSEL13_0,
MSEL2CR_MSEL12_0),
PINMUX_DATA(TSIF1_TS_XX1_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
MSEL2CR_MSEL9_0),
PINMUX_DATA(TSIF1_TS_XX2_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_0,
MSEL2CR_MSEL9_1),
PINMUX_DATA(TSIF1_TS_XX3_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
MSEL2CR_MSEL9_0),
PINMUX_DATA(TSIF1_TS_XX4_MARK, MSEL2CR_MSEL11_0, MSEL2CR_MSEL10_1,
MSEL2CR_MSEL9_1),
PINMUX_DATA(TSIF1_TS_XX5_MARK, MSEL2CR_MSEL11_1, MSEL2CR_MSEL10_0,
MSEL2CR_MSEL9_0),
PINMUX_DATA(TSIF0_TS_XX1_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
MSEL2CR_MSEL6_0),
PINMUX_DATA(TSIF0_TS_XX2_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_0,
MSEL2CR_MSEL6_1),
PINMUX_DATA(TSIF0_TS_XX3_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
MSEL2CR_MSEL6_0),
PINMUX_DATA(TSIF0_TS_XX4_MARK, MSEL2CR_MSEL8_0, MSEL2CR_MSEL7_1,
MSEL2CR_MSEL6_1),
PINMUX_DATA(TSIF0_TS_XX5_MARK, MSEL2CR_MSEL8_1, MSEL2CR_MSEL7_0,
MSEL2CR_MSEL6_0),
PINMUX_DATA(MST1_TS_XX1_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
MSEL2CR_MSEL3_0),
PINMUX_DATA(MST1_TS_XX2_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_0,
MSEL2CR_MSEL3_1),
PINMUX_DATA(MST1_TS_XX3_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
MSEL2CR_MSEL3_0),
PINMUX_DATA(MST1_TS_XX4_MARK, MSEL2CR_MSEL5_0, MSEL2CR_MSEL4_1,
MSEL2CR_MSEL3_1),
PINMUX_DATA(MST1_TS_XX5_MARK, MSEL2CR_MSEL5_1, MSEL2CR_MSEL4_0,
MSEL2CR_MSEL3_0),
PINMUX_DATA(MST0_TS_XX1_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
MSEL2CR_MSEL0_0),
PINMUX_DATA(MST0_TS_XX2_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_0,
MSEL2CR_MSEL0_1),
PINMUX_DATA(MST0_TS_XX3_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
MSEL2CR_MSEL0_0),
PINMUX_DATA(MST0_TS_XX4_MARK, MSEL2CR_MSEL2_0, MSEL2CR_MSEL1_1,
MSEL2CR_MSEL0_1),
PINMUX_DATA(MST0_TS_XX5_MARK, MSEL2CR_MSEL2_1, MSEL2CR_MSEL1_0,
MSEL2CR_MSEL0_0),
/* MSEL3 special cases */
PINMUX_DATA(SDHI0_VCCQ_MC0_ON_MARK, MSEL3CR_MSEL28_1),
PINMUX_DATA(SDHI0_VCCQ_MC0_OFF_MARK, MSEL3CR_MSEL28_0),
PINMUX_DATA(DEBUG_MON_VIO_MARK, MSEL3CR_MSEL15_0),
PINMUX_DATA(DEBUG_MON_LCDD_MARK, MSEL3CR_MSEL15_1),
PINMUX_DATA(LCDC_LCDC0_MARK, MSEL3CR_MSEL6_0),
PINMUX_DATA(LCDC_LCDC1_MARK, MSEL3CR_MSEL6_1),
/* MSEL4 special cases */
PINMUX_DATA(IRQ9_MEM_INT_MARK, MSEL4CR_MSEL29_0),
PINMUX_DATA(IRQ9_MCP_INT_MARK, MSEL4CR_MSEL29_1),
PINMUX_DATA(A11_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_0),
PINMUX_DATA(KEYOUT8_MARK, MSEL4CR_MSEL13_0, MSEL4CR_MSEL12_1),
PINMUX_DATA(TPU4TO3_MARK, MSEL4CR_MSEL13_1, MSEL4CR_MSEL12_0),
PINMUX_DATA(RESETA_N_PU_ON_MARK, MSEL4CR_MSEL4_0),
PINMUX_DATA(RESETA_N_PU_OFF_MARK, MSEL4CR_MSEL4_1),
PINMUX_DATA(EDBGREQ_PD_MARK, MSEL4CR_MSEL1_0),
PINMUX_DATA(EDBGREQ_PU_MARK, MSEL4CR_MSEL1_1),
};
#define __I (SH_PFC_PIN_CFG_INPUT)
#define __O (SH_PFC_PIN_CFG_OUTPUT)
#define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
#define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
#define __PU (SH_PFC_PIN_CFG_PULL_UP)
#define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
#define SH73A0_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
#define SH73A0_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
#define SH73A0_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
#define SH73A0_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
#define SH73A0_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
#define SH73A0_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
#define SH73A0_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
#define SH73A0_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
/* Pin numbers for pins without a corresponding GPIO port number are computed
* from the row and column numbers with a 1000 offset to avoid collisions with
* GPIO port numbers.
*/
#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
static const struct sh_pfc_pin pinmux_pins[] = {
/* Table 25-1 (I/O and Pull U/D) */
SH73A0_PIN_I_PD(0),
SH73A0_PIN_I_PU(1),
SH73A0_PIN_I_PU(2),
SH73A0_PIN_I_PU(3),
SH73A0_PIN_I_PU(4),
SH73A0_PIN_I_PU(5),
SH73A0_PIN_I_PU(6),
SH73A0_PIN_I_PU(7),
SH73A0_PIN_I_PU(8),
SH73A0_PIN_I_PD(9),
SH73A0_PIN_I_PD(10),
SH73A0_PIN_I_PU_PD(11),
SH73A0_PIN_IO_PU_PD(12),
SH73A0_PIN_IO_PU_PD(13),
SH73A0_PIN_IO_PU_PD(14),
SH73A0_PIN_IO_PU_PD(15),
SH73A0_PIN_IO_PD(16),
SH73A0_PIN_IO_PD(17),
SH73A0_PIN_IO_PU(18),
SH73A0_PIN_IO_PU(19),
SH73A0_PIN_O(20),
SH73A0_PIN_O(21),
SH73A0_PIN_O(22),
SH73A0_PIN_O(23),
SH73A0_PIN_O(24),
SH73A0_PIN_I_PD(25),
SH73A0_PIN_I_PD(26),
SH73A0_PIN_IO_PU(27),
SH73A0_PIN_IO_PU(28),
SH73A0_PIN_IO_PD(29),
SH73A0_PIN_IO_PD(30),
SH73A0_PIN_IO_PU(31),
SH73A0_PIN_IO_PD(32),
SH73A0_PIN_I_PU_PD(33),
SH73A0_PIN_IO_PD(34),
SH73A0_PIN_I_PU_PD(35),
SH73A0_PIN_IO_PD(36),
SH73A0_PIN_IO(37),
SH73A0_PIN_O(38),
SH73A0_PIN_I_PU(39),
SH73A0_PIN_I_PU_PD(40),
SH73A0_PIN_O(41),
SH73A0_PIN_IO_PD(42),
SH73A0_PIN_IO_PU_PD(43),
SH73A0_PIN_IO_PU_PD(44),
SH73A0_PIN_IO_PD(45),
SH73A0_PIN_IO_PD(46),
SH73A0_PIN_IO_PD(47),
SH73A0_PIN_I_PD(48),
SH73A0_PIN_IO_PU_PD(49),
SH73A0_PIN_IO_PD(50),
SH73A0_PIN_IO_PD(51),
SH73A0_PIN_O(52),
SH73A0_PIN_IO_PU_PD(53),
SH73A0_PIN_IO_PU_PD(54),
SH73A0_PIN_IO_PD(55),
SH73A0_PIN_I_PU_PD(56),
SH73A0_PIN_IO(57),
SH73A0_PIN_IO(58),
SH73A0_PIN_IO(59),
SH73A0_PIN_IO(60),
SH73A0_PIN_IO(61),
SH73A0_PIN_IO_PD(62),
SH73A0_PIN_IO_PD(63),
SH73A0_PIN_IO_PU_PD(64),
SH73A0_PIN_IO_PD(65),
SH73A0_PIN_IO_PU_PD(66),
SH73A0_PIN_IO_PU_PD(67),
SH73A0_PIN_IO_PU_PD(68),
SH73A0_PIN_IO_PU_PD(69),
SH73A0_PIN_IO_PU_PD(70),
SH73A0_PIN_IO_PU_PD(71),
SH73A0_PIN_IO_PU_PD(72),
SH73A0_PIN_I_PU_PD(73),
SH73A0_PIN_IO_PU(74),
SH73A0_PIN_IO_PU(75),
SH73A0_PIN_IO_PU(76),
SH73A0_PIN_IO_PU(77),
SH73A0_PIN_IO_PU(78),
SH73A0_PIN_IO_PU(79),
SH73A0_PIN_IO_PU(80),
SH73A0_PIN_IO_PU(81),
SH73A0_PIN_IO_PU(82),
SH73A0_PIN_IO_PU(83),
SH73A0_PIN_IO_PU(84),
SH73A0_PIN_IO_PU(85),
SH73A0_PIN_IO_PU(86),
SH73A0_PIN_IO_PU(87),
SH73A0_PIN_IO_PU(88),
SH73A0_PIN_IO_PU(89),
SH73A0_PIN_O(90),
SH73A0_PIN_IO_PU(91),
SH73A0_PIN_O(92),
SH73A0_PIN_IO_PU(93),
SH73A0_PIN_O(94),
SH73A0_PIN_I_PU_PD(95),
SH73A0_PIN_IO(96),
SH73A0_PIN_IO(97),
SH73A0_PIN_IO(98),
SH73A0_PIN_I_PU(99),
SH73A0_PIN_O(100),
SH73A0_PIN_O(101),
SH73A0_PIN_I_PU(102),
SH73A0_PIN_IO_PD(103),
SH73A0_PIN_I_PU_PD(104),
SH73A0_PIN_I_PD(105),
SH73A0_PIN_I_PD(106),
SH73A0_PIN_I_PU_PD(107),
SH73A0_PIN_I_PU_PD(108),
SH73A0_PIN_IO_PD(109),
SH73A0_PIN_IO_PD(110),
SH73A0_PIN_IO_PU_PD(111),
SH73A0_PIN_IO_PU_PD(112),
SH73A0_PIN_IO_PU_PD(113),
SH73A0_PIN_IO_PD(114),
SH73A0_PIN_IO_PU(115),
SH73A0_PIN_IO_PU(116),
SH73A0_PIN_IO_PU_PD(117),
SH73A0_PIN_IO_PU_PD(118),
SH73A0_PIN_IO_PD(128),
SH73A0_PIN_IO_PD(129),
SH73A0_PIN_IO_PU_PD(130),
SH73A0_PIN_IO_PD(131),
SH73A0_PIN_IO_PD(132),
SH73A0_PIN_IO_PD(133),
SH73A0_PIN_IO_PU_PD(134),
SH73A0_PIN_IO_PU_PD(135),
SH73A0_PIN_IO_PU_PD(136),
SH73A0_PIN_IO_PU_PD(137),
SH73A0_PIN_IO_PD(138),
SH73A0_PIN_IO_PD(139),
SH73A0_PIN_IO_PD(140),
SH73A0_PIN_IO_PD(141),
SH73A0_PIN_IO_PD(142),
SH73A0_PIN_IO_PD(143),
SH73A0_PIN_IO_PU_PD(144),
SH73A0_PIN_IO_PD(145),
SH73A0_PIN_IO_PU_PD(146),
SH73A0_PIN_IO_PU_PD(147),
SH73A0_PIN_IO_PU_PD(148),
SH73A0_PIN_IO_PU_PD(149),
SH73A0_PIN_I_PU_PD(150),
SH73A0_PIN_IO_PU_PD(151),
SH73A0_PIN_IO_PU_PD(152),
SH73A0_PIN_IO_PD(153),
SH73A0_PIN_IO_PD(154),
SH73A0_PIN_I_PU_PD(155),
SH73A0_PIN_IO_PU_PD(156),
SH73A0_PIN_I_PD(157),
SH73A0_PIN_IO_PD(158),
SH73A0_PIN_IO_PU_PD(159),
SH73A0_PIN_IO_PU_PD(160),
SH73A0_PIN_I_PU_PD(161),
SH73A0_PIN_I_PU_PD(162),
SH73A0_PIN_IO_PU_PD(163),
SH73A0_PIN_I_PU_PD(164),
SH73A0_PIN_IO_PD(192),
SH73A0_PIN_IO_PU_PD(193),
SH73A0_PIN_IO_PD(194),
SH73A0_PIN_IO_PU_PD(195),
SH73A0_PIN_IO_PD(196),
SH73A0_PIN_IO_PD(197),
SH73A0_PIN_IO_PD(198),
SH73A0_PIN_IO_PD(199),
SH73A0_PIN_IO_PU_PD(200),
SH73A0_PIN_IO_PU_PD(201),
SH73A0_PIN_IO_PU_PD(202),
SH73A0_PIN_IO_PU_PD(203),
SH73A0_PIN_IO_PU_PD(204),
SH73A0_PIN_IO_PU_PD(205),
SH73A0_PIN_IO_PU_PD(206),
SH73A0_PIN_IO_PD(207),
SH73A0_PIN_IO_PD(208),
SH73A0_PIN_IO_PD(209),
SH73A0_PIN_IO_PD(210),
SH73A0_PIN_IO_PD(211),
SH73A0_PIN_IO_PD(212),
SH73A0_PIN_IO_PD(213),
SH73A0_PIN_IO_PU_PD(214),
SH73A0_PIN_IO_PU_PD(215),
SH73A0_PIN_IO_PD(216),
SH73A0_PIN_IO_PD(217),
SH73A0_PIN_O(218),
SH73A0_PIN_IO_PD(219),
SH73A0_PIN_IO_PD(220),
SH73A0_PIN_IO_PU_PD(221),
SH73A0_PIN_IO_PU_PD(222),
SH73A0_PIN_I_PU_PD(223),
SH73A0_PIN_I_PU_PD(224),
SH73A0_PIN_IO_PU_PD(225),
SH73A0_PIN_O(226),
SH73A0_PIN_IO_PU_PD(227),
SH73A0_PIN_I_PU_PD(228),
SH73A0_PIN_I_PD(229),
SH73A0_PIN_IO(230),
SH73A0_PIN_IO_PU_PD(231),
SH73A0_PIN_IO_PU_PD(232),
SH73A0_PIN_I_PU_PD(233),
SH73A0_PIN_IO_PU_PD(234),
SH73A0_PIN_IO_PU_PD(235),
SH73A0_PIN_IO_PU_PD(236),
SH73A0_PIN_IO_PD(237),
SH73A0_PIN_IO_PU_PD(238),
SH73A0_PIN_IO_PU_PD(239),
SH73A0_PIN_IO_PU_PD(240),
SH73A0_PIN_O(241),
SH73A0_PIN_I_PD(242),
SH73A0_PIN_IO_PU_PD(243),
SH73A0_PIN_IO_PU_PD(244),
SH73A0_PIN_IO_PU_PD(245),
SH73A0_PIN_IO_PU_PD(246),
SH73A0_PIN_IO_PU_PD(247),
SH73A0_PIN_IO_PU_PD(248),
SH73A0_PIN_IO_PU_PD(249),
SH73A0_PIN_IO_PU_PD(250),
SH73A0_PIN_IO_PU_PD(251),
SH73A0_PIN_IO_PU_PD(252),
SH73A0_PIN_IO_PU_PD(253),
SH73A0_PIN_IO_PU_PD(254),
SH73A0_PIN_IO_PU_PD(255),
SH73A0_PIN_IO_PU_PD(256),
SH73A0_PIN_IO_PU_PD(257),
SH73A0_PIN_IO_PU_PD(258),
SH73A0_PIN_IO_PU_PD(259),
SH73A0_PIN_IO_PU_PD(260),
SH73A0_PIN_IO_PU_PD(261),
SH73A0_PIN_IO_PU_PD(262),
SH73A0_PIN_IO_PU_PD(263),
SH73A0_PIN_IO_PU_PD(264),
SH73A0_PIN_IO_PU_PD(265),
SH73A0_PIN_IO_PU_PD(266),
SH73A0_PIN_IO_PU_PD(267),
SH73A0_PIN_IO_PU_PD(268),
SH73A0_PIN_IO_PU_PD(269),
SH73A0_PIN_IO_PU_PD(270),
SH73A0_PIN_IO_PU_PD(271),
SH73A0_PIN_IO_PU_PD(272),
SH73A0_PIN_IO_PU_PD(273),
SH73A0_PIN_IO_PU_PD(274),
SH73A0_PIN_IO_PU_PD(275),
SH73A0_PIN_IO_PU_PD(276),
SH73A0_PIN_IO_PU_PD(277),
SH73A0_PIN_IO_PU_PD(278),
SH73A0_PIN_IO_PU_PD(279),
SH73A0_PIN_IO_PU_PD(280),
SH73A0_PIN_O(281),
SH73A0_PIN_O(282),
SH73A0_PIN_I_PU(288),
SH73A0_PIN_IO_PU_PD(289),
SH73A0_PIN_IO_PU_PD(290),
SH73A0_PIN_IO_PU_PD(291),
SH73A0_PIN_IO_PU_PD(292),
SH73A0_PIN_IO_PU_PD(293),
SH73A0_PIN_IO_PU_PD(294),
SH73A0_PIN_IO_PU_PD(295),
SH73A0_PIN_IO_PU_PD(296),
SH73A0_PIN_IO_PU_PD(297),
SH73A0_PIN_IO_PU_PD(298),
SH73A0_PIN_IO_PU_PD(299),
SH73A0_PIN_IO_PU_PD(300),
SH73A0_PIN_IO_PU_PD(301),
SH73A0_PIN_IO_PU_PD(302),
SH73A0_PIN_IO_PU_PD(303),
SH73A0_PIN_IO_PU_PD(304),
SH73A0_PIN_IO_PU_PD(305),
SH73A0_PIN_O(306),
SH73A0_PIN_O(307),
SH73A0_PIN_I_PU(308),
SH73A0_PIN_O(309),
/* Pins not associated with a GPIO port */
SH_PFC_PIN_NAMED(6, 26, F26),
};
/* - BSC -------------------------------------------------------------------- */
static const unsigned int bsc_data_0_7_pins[] = {
/* D[0:7] */
74, 75, 76, 77, 78, 79, 80, 81,
};
static const unsigned int bsc_data_0_7_mux[] = {
D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
};
static const unsigned int bsc_data_8_15_pins[] = {
/* D[8:15] */
82, 83, 84, 85, 86, 87, 88, 89,
};
static const unsigned int bsc_data_8_15_mux[] = {
D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
};
static const unsigned int bsc_cs4_pins[] = {
/* CS */
90,
};
static const unsigned int bsc_cs4_mux[] = {
CS4__MARK,
};
static const unsigned int bsc_cs5_a_pins[] = {
/* CS */
91,
};
static const unsigned int bsc_cs5_a_mux[] = {
CS5A__MARK,
};
static const unsigned int bsc_cs5_b_pins[] = {
/* CS */
92,
};
static const unsigned int bsc_cs5_b_mux[] = {
CS5B__MARK,
};
static const unsigned int bsc_cs6_a_pins[] = {
/* CS */
94,
};
static const unsigned int bsc_cs6_a_mux[] = {
CS6A__MARK,
};
static const unsigned int bsc_cs6_b_pins[] = {
/* CS */
93,
};
static const unsigned int bsc_cs6_b_mux[] = {
CS6B__MARK,
};
static const unsigned int bsc_rd_pins[] = {
/* RD */
96,
};
static const unsigned int bsc_rd_mux[] = {
RD__FSC_MARK,
};
static const unsigned int bsc_rdwr_0_pins[] = {
/* RDWR */
91,
};
static const unsigned int bsc_rdwr_0_mux[] = {
PORT91_RDWR_MARK,
};
static const unsigned int bsc_rdwr_1_pins[] = {
/* RDWR */
97,
};
static const unsigned int bsc_rdwr_1_mux[] = {
RDWR_FWE_MARK,
};
static const unsigned int bsc_rdwr_2_pins[] = {
/* RDWR */
149,
};
static const unsigned int bsc_rdwr_2_mux[] = {
PORT149_RDWR_MARK,
};
static const unsigned int bsc_we0_pins[] = {
/* WE0 */
97,
};
static const unsigned int bsc_we0_mux[] = {
WE0__FWE_MARK,
};
static const unsigned int bsc_we1_pins[] = {
/* WE1 */
98,
};
static const unsigned int bsc_we1_mux[] = {
WE1__MARK,
};
/* - FSIA ------------------------------------------------------------------- */
static const unsigned int fsia_mclk_in_pins[] = {
/* CK */
49,
};
static const unsigned int fsia_mclk_in_mux[] = {
FSIACK_MARK,
};
static const unsigned int fsia_mclk_out_pins[] = {
/* OMC */
49,
};
static const unsigned int fsia_mclk_out_mux[] = {
FSIAOMC_MARK,
};
static const unsigned int fsia_sclk_in_pins[] = {
/* ILR, IBT */
50, 51,
};
static const unsigned int fsia_sclk_in_mux[] = {
FSIAILR_MARK, FSIAIBT_MARK,
};
static const unsigned int fsia_sclk_out_pins[] = {
/* OLR, OBT */
50, 51,
};
static const unsigned int fsia_sclk_out_mux[] = {
FSIAOLR_MARK, FSIAOBT_MARK,
};
static const unsigned int fsia_data_in_pins[] = {
/* ISLD */
55,
};
static const unsigned int fsia_data_in_mux[] = {
FSIAISLD_MARK,
};
static const unsigned int fsia_data_out_pins[] = {
/* OSLD */
52,
};
static const unsigned int fsia_data_out_mux[] = {
FSIAOSLD_MARK,
};
static const unsigned int fsia_spdif_pins[] = {
/* SPDIF */
53,
};
static const unsigned int fsia_spdif_mux[] = {
FSIASPDIF_MARK,
};
/* - FSIB ------------------------------------------------------------------- */
static const unsigned int fsib_mclk_in_pins[] = {
/* CK */
54,
};
static const unsigned int fsib_mclk_in_mux[] = {
FSIBCK_MARK,
};
static const unsigned int fsib_mclk_out_pins[] = {
/* OMC */
54,
};
static const unsigned int fsib_mclk_out_mux[] = {
FSIBOMC_MARK,
};
static const unsigned int fsib_sclk_in_pins[] = {
/* ILR, IBT */
37, 36,
};
static const unsigned int fsib_sclk_in_mux[] = {
FSIBILR_MARK, FSIBIBT_MARK,
};
static const unsigned int fsib_sclk_out_pins[] = {
/* OLR, OBT */
37, 36,
};
static const unsigned int fsib_sclk_out_mux[] = {
FSIBOLR_MARK, FSIBOBT_MARK,
};
static const unsigned int fsib_data_in_pins[] = {
/* ISLD */
39,
};
static const unsigned int fsib_data_in_mux[] = {
FSIBISLD_MARK,
};
static const unsigned int fsib_data_out_pins[] = {
/* OSLD */
38,
};
static const unsigned int fsib_data_out_mux[] = {
FSIBOSLD_MARK,
};
static const unsigned int fsib_spdif_pins[] = {
/* SPDIF */
53,
};
static const unsigned int fsib_spdif_mux[] = {
FSIBSPDIF_MARK,
};
/* - FSIC ------------------------------------------------------------------- */
static const unsigned int fsic_mclk_in_pins[] = {
/* CK */
54,
};
static const unsigned int fsic_mclk_in_mux[] = {
FSICCK_MARK,
};
static const unsigned int fsic_mclk_out_pins[] = {
/* OMC */
54,
};
static const unsigned int fsic_mclk_out_mux[] = {
FSICOMC_MARK,
};
static const unsigned int fsic_sclk_in_pins[] = {
/* ILR, IBT */
46, 45,
};
static const unsigned int fsic_sclk_in_mux[] = {
FSICILR_MARK, FSICIBT_MARK,
};
static const unsigned int fsic_sclk_out_pins[] = {
/* OLR, OBT */
46, 45,
};
static const unsigned int fsic_sclk_out_mux[] = {
FSICOLR_MARK, FSICOBT_MARK,
};
static const unsigned int fsic_data_in_pins[] = {
/* ISLD */
48,
};
static const unsigned int fsic_data_in_mux[] = {
FSICISLD_MARK,
};
static const unsigned int fsic_data_out_pins[] = {
/* OSLD, OSLDT1, OSLDT2, OSLDT3 */
47, 44, 42, 16,
};
static const unsigned int fsic_data_out_mux[] = {
FSICOSLD_MARK, FSICOSLDT1_MARK, FSICOSLDT2_MARK, FSICOSLDT3_MARK,
};
static const unsigned int fsic_spdif_0_pins[] = {
/* SPDIF */
53,
};
static const unsigned int fsic_spdif_0_mux[] = {
PORT53_FSICSPDIF_MARK,
};
static const unsigned int fsic_spdif_1_pins[] = {
/* SPDIF */
47,
};
static const unsigned int fsic_spdif_1_mux[] = {
PORT47_FSICSPDIF_MARK,
};
/* - FSID ------------------------------------------------------------------- */
static const unsigned int fsid_sclk_in_pins[] = {
/* ILR, IBT */
46, 45,
};
static const unsigned int fsid_sclk_in_mux[] = {
FSIDILR_MARK, FSIDIBT_MARK,
};
static const unsigned int fsid_sclk_out_pins[] = {
/* OLR, OBT */
46, 45,
};
static const unsigned int fsid_sclk_out_mux[] = {
FSIDOLR_MARK, FSIDOBT_MARK,
};
static const unsigned int fsid_data_in_pins[] = {
/* ISLD */
48,
};
static const unsigned int fsid_data_in_mux[] = {
FSIDISLD_MARK,
};
/* - I2C2 ------------------------------------------------------------------- */
static const unsigned int i2c2_0_pins[] = {
/* SCL, SDA */
237, 236,
};
static const unsigned int i2c2_0_mux[] = {
PORT237_I2C_SCL2_MARK, PORT236_I2C_SDA2_MARK,
};
static const unsigned int i2c2_1_pins[] = {
/* SCL, SDA */
27, 28,
};
static const unsigned int i2c2_1_mux[] = {
PORT27_I2C_SCL2_MARK, PORT28_I2C_SDA2_MARK,
};
static const unsigned int i2c2_2_pins[] = {
/* SCL, SDA */
115, 116,
};
static const unsigned int i2c2_2_mux[] = {
PORT115_I2C_SCL2_MARK, PORT116_I2C_SDA2_MARK,
};
/* - I2C3 ------------------------------------------------------------------- */
static const unsigned int i2c3_0_pins[] = {
/* SCL, SDA */
248, 249,
};
static const unsigned int i2c3_0_mux[] = {
PORT248_I2C_SCL3_MARK, PORT249_I2C_SDA3_MARK,
};
static const unsigned int i2c3_1_pins[] = {
/* SCL, SDA */
27, 28,
};
static const unsigned int i2c3_1_mux[] = {
PORT27_I2C_SCL3_MARK, PORT28_I2C_SDA3_MARK,
};
static const unsigned int i2c3_2_pins[] = {
/* SCL, SDA */
115, 116,
};
static const unsigned int i2c3_2_mux[] = {
PORT115_I2C_SCL3_MARK, PORT116_I2C_SDA3_MARK,
};
/* - IrDA ------------------------------------------------------------------- */
static const unsigned int irda_0_pins[] = {
/* OUT, IN, FIRSEL */
241, 242, 243,
};
static const unsigned int irda_0_mux[] = {
PORT241_IRDA_OUT_MARK, PORT242_IRDA_IN_MARK, PORT243_IRDA_FIRSEL_MARK,
};
static const unsigned int irda_1_pins[] = {
/* OUT, IN, FIRSEL */
49, 53, 54,
};
static const unsigned int irda_1_mux[] = {
PORT49_IRDA_OUT_MARK, PORT53_IRDA_IN_MARK, PORT54_IRDA_FIRSEL_MARK,
};
/* - KEYSC ------------------------------------------------------------------ */
static const unsigned int keysc_in5_pins[] = {
/* KEYIN[0:4] */
66, 67, 68, 69, 70,
};
static const unsigned int keysc_in5_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK,
};
static const unsigned int keysc_in6_pins[] = {
/* KEYIN[0:5] */
66, 67, 68, 69, 70, 71,
};
static const unsigned int keysc_in6_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK,
};
static const unsigned int keysc_in7_pins[] = {
/* KEYIN[0:6] */
66, 67, 68, 69, 70, 71, 72,
};
static const unsigned int keysc_in7_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK,
};
static const unsigned int keysc_in8_pins[] = {
/* KEYIN[0:7] */
66, 67, 68, 69, 70, 71, 72, 73,
};
static const unsigned int keysc_in8_mux[] = {
KEYIN0_MARK, KEYIN1_MARK, KEYIN2_MARK, KEYIN3_MARK,
KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
};
static const unsigned int keysc_out04_pins[] = {
/* KEYOUT[0:4] */
65, 64, 63, 62, 61,
};
static const unsigned int keysc_out04_mux[] = {
KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK, KEYOUT4_MARK,
};
static const unsigned int keysc_out5_pins[] = {
/* KEYOUT5 */
60,
};
static const unsigned int keysc_out5_mux[] = {
KEYOUT5_MARK,
};
static const unsigned int keysc_out6_0_pins[] = {
/* KEYOUT6 */
59,
};
static const unsigned int keysc_out6_0_mux[] = {
PORT59_KEYOUT6_MARK,
};
static const unsigned int keysc_out6_1_pins[] = {
/* KEYOUT6 */
131,
};
static const unsigned int keysc_out6_1_mux[] = {
PORT131_KEYOUT6_MARK,
};
static const unsigned int keysc_out6_2_pins[] = {
/* KEYOUT6 */
143,
};
static const unsigned int keysc_out6_2_mux[] = {
PORT143_KEYOUT6_MARK,
};
static const unsigned int keysc_out7_0_pins[] = {
/* KEYOUT7 */
58,
};
static const unsigned int keysc_out7_0_mux[] = {
PORT58_KEYOUT7_MARK,
};
static const unsigned int keysc_out7_1_pins[] = {
/* KEYOUT7 */
132,
};
static const unsigned int keysc_out7_1_mux[] = {
PORT132_KEYOUT7_MARK,
};
static const unsigned int keysc_out7_2_pins[] = {
/* KEYOUT7 */
144,
};
static const unsigned int keysc_out7_2_mux[] = {
PORT144_KEYOUT7_MARK,
};
static const unsigned int keysc_out8_0_pins[] = {
/* KEYOUT8 */
PIN_NUMBER(6, 26),
};
static const unsigned int keysc_out8_0_mux[] = {
KEYOUT8_MARK,
};
static const unsigned int keysc_out8_1_pins[] = {
/* KEYOUT8 */
136,
};
static const unsigned int keysc_out8_1_mux[] = {
PORT136_KEYOUT8_MARK,
};
static const unsigned int keysc_out8_2_pins[] = {
/* KEYOUT8 */
138,
};
static const unsigned int keysc_out8_2_mux[] = {
PORT138_KEYOUT8_MARK,
};
static const unsigned int keysc_out9_0_pins[] = {
/* KEYOUT9 */
137,
};
static const unsigned int keysc_out9_0_mux[] = {
PORT137_KEYOUT9_MARK,
};
static const unsigned int keysc_out9_1_pins[] = {
/* KEYOUT9 */
139,
};
static const unsigned int keysc_out9_1_mux[] = {
PORT139_KEYOUT9_MARK,
};
static const unsigned int keysc_out9_2_pins[] = {
/* KEYOUT9 */
149,
};
static const unsigned int keysc_out9_2_mux[] = {
PORT149_KEYOUT9_MARK,
};
static const unsigned int keysc_out10_0_pins[] = {
/* KEYOUT10 */
132,
};
static const unsigned int keysc_out10_0_mux[] = {
PORT132_KEYOUT10_MARK,
};
static const unsigned int keysc_out10_1_pins[] = {
/* KEYOUT10 */
142,
};
static const unsigned int keysc_out10_1_mux[] = {
PORT142_KEYOUT10_MARK,
};
static const unsigned int keysc_out11_0_pins[] = {
/* KEYOUT11 */
131,
};
static const unsigned int keysc_out11_0_mux[] = {
PORT131_KEYOUT11_MARK,
};
static const unsigned int keysc_out11_1_pins[] = {
/* KEYOUT11 */
143,
};
static const unsigned int keysc_out11_1_mux[] = {
PORT143_KEYOUT11_MARK,
};
/* - LCD -------------------------------------------------------------------- */
static const unsigned int lcd_data8_pins[] = {
/* D[0:7] */
192, 193, 194, 195, 196, 197, 198, 199,
};
static const unsigned int lcd_data8_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
};
static const unsigned int lcd_data9_pins[] = {
/* D[0:8] */
192, 193, 194, 195, 196, 197, 198, 199,
200,
};
static const unsigned int lcd_data9_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK,
};
static const unsigned int lcd_data12_pins[] = {
/* D[0:11] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203,
};
static const unsigned int lcd_data12_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
};
static const unsigned int lcd_data16_pins[] = {
/* D[0:15] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
};
static const unsigned int lcd_data16_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
};
static const unsigned int lcd_data18_pins[] = {
/* D[0:17] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
208, 209,
};
static const unsigned int lcd_data18_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
LCDD16_MARK, LCDD17_MARK,
};
static const unsigned int lcd_data24_pins[] = {
/* D[0:23] */
192, 193, 194, 195, 196, 197, 198, 199,
200, 201, 202, 203, 204, 205, 206, 207,
208, 209, 210, 211, 212, 213, 214, 215
};
static const unsigned int lcd_data24_mux[] = {
LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
};
static const unsigned int lcd_display_pins[] = {
/* DON */
222,
};
static const unsigned int lcd_display_mux[] = {
LCDDON_MARK,
};
static const unsigned int lcd_lclk_pins[] = {
/* LCLK */
221,
};
static const unsigned int lcd_lclk_mux[] = {
LCDLCLK_MARK,
};
static const unsigned int lcd_sync_pins[] = {
/* VSYN, HSYN, DCK, DISP */
220, 218, 216, 219,
};
static const unsigned int lcd_sync_mux[] = {
LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
};
static const unsigned int lcd_sys_pins[] = {
/* CS, WR, RD, RS */
218, 216, 217, 219,
};
static const unsigned int lcd_sys_mux[] = {
LCDCS__MARK, LCDWR__MARK, LCDRD__MARK, LCDRS_MARK,
};
/* - LCD2 ------------------------------------------------------------------- */
static const unsigned int lcd2_data8_pins[] = {
/* D[0:7] */
128, 129, 142, 143, 144, 145, 138, 139,
};
static const unsigned int lcd2_data8_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
};
static const unsigned int lcd2_data9_pins[] = {
/* D[0:8] */
128, 129, 142, 143, 144, 145, 138, 139,
140,
};
static const unsigned int lcd2_data9_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK,
};
static const unsigned int lcd2_data12_pins[] = {
/* D[0:11] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131,
};
static const unsigned int lcd2_data12_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
};
static const unsigned int lcd2_data16_pins[] = {
/* D[0:15] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
};
static const unsigned int lcd2_data16_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
};
static const unsigned int lcd2_data18_pins[] = {
/* D[0:17] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
136, 137,
};
static const unsigned int lcd2_data18_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
LCD2D16_MARK, LCD2D17_MARK,
};
static const unsigned int lcd2_data24_pins[] = {
/* D[0:23] */
128, 129, 142, 143, 144, 145, 138, 139,
140, 141, 130, 131, 132, 133, 134, 135,
136, 137, 146, 147, 234, 235, 238, 239
};
static const unsigned int lcd2_data24_mux[] = {
LCD2D0_MARK, LCD2D1_MARK, LCD2D2_MARK, LCD2D3_MARK,
LCD2D4_MARK, LCD2D5_MARK, LCD2D6_MARK, LCD2D7_MARK,
LCD2D8_MARK, LCD2D9_MARK, LCD2D10_MARK, LCD2D11_MARK,
LCD2D12_MARK, LCD2D13_MARK, LCD2D14_MARK, LCD2D15_MARK,
LCD2D16_MARK, LCD2D17_MARK, LCD2D18_MARK, LCD2D19_MARK,
LCD2D20_MARK, LCD2D21_MARK, LCD2D22_MARK, LCD2D23_MARK,
};
static const unsigned int lcd2_sync_0_pins[] = {
/* VSYN, HSYN, DCK, DISP */
128, 129, 146, 145,
};
static const unsigned int lcd2_sync_0_mux[] = {
PORT128_LCD2VSYN_MARK, PORT129_LCD2HSYN_MARK,
LCD2DCK_MARK, PORT145_LCD2DISP_MARK,
};
static const unsigned int lcd2_sync_1_pins[] = {
/* VSYN, HSYN, DCK, DISP */
222, 221, 219, 217,
};
static const unsigned int lcd2_sync_1_mux[] = {
PORT222_LCD2VSYN_MARK, PORT221_LCD2HSYN_MARK,
LCD2DCK_2_MARK, PORT217_LCD2DISP_MARK,
};
static const unsigned int lcd2_sys_0_pins[] = {
/* CS, WR, RD, RS */
129, 146, 147, 145,
};
static const unsigned int lcd2_sys_0_mux[] = {
PORT129_LCD2CS__MARK, PORT146_LCD2WR__MARK,
LCD2RD__MARK, PORT145_LCD2RS_MARK,
};
static const unsigned int lcd2_sys_1_pins[] = {
/* CS, WR, RD, RS */
221, 219, 147, 217,
};
static const unsigned int lcd2_sys_1_mux[] = {
PORT221_LCD2CS__MARK, PORT219_LCD2WR__MARK,
LCD2RD__MARK, PORT217_LCD2RS_MARK,
};
/* - MMCIF ------------------------------------------------------------------ */
static const unsigned int mmc0_data1_0_pins[] = {
/* D[0] */
271,
};
static const unsigned int mmc0_data1_0_mux[] = {
MMCD0_0_MARK,
};
static const unsigned int mmc0_data4_0_pins[] = {
/* D[0:3] */
271, 272, 273, 274,
};
static const unsigned int mmc0_data4_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
};
static const unsigned int mmc0_data8_0_pins[] = {
/* D[0:7] */
271, 272, 273, 274, 275, 276, 277, 278,
};
static const unsigned int mmc0_data8_0_mux[] = {
MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
};
static const unsigned int mmc0_ctrl_0_pins[] = {
/* CMD, CLK */
279, 270,
};
static const unsigned int mmc0_ctrl_0_mux[] = {
MMCCMD0_MARK, MMCCLK0_MARK,
};
static const unsigned int mmc0_data1_1_pins[] = {
/* D[0] */
305,
};
static const unsigned int mmc0_data1_1_mux[] = {
MMCD1_0_MARK,
};
static const unsigned int mmc0_data4_1_pins[] = {
/* D[0:3] */
305, 304, 303, 302,
};
static const unsigned int mmc0_data4_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
};
static const unsigned int mmc0_data8_1_pins[] = {
/* D[0:7] */
305, 304, 303, 302, 301, 300, 299, 298,
};
static const unsigned int mmc0_data8_1_mux[] = {
MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
};
static const unsigned int mmc0_ctrl_1_pins[] = {
/* CMD, CLK */
297, 289,
};
static const unsigned int mmc0_ctrl_1_mux[] = {
MMCCMD1_MARK, MMCCLK1_MARK,
};
/* - MSIOF0 ----------------------------------------------------------------- */
static const unsigned int msiof0_rsck_pins[] = {
/* RSCK */
66,
};
static const unsigned int msiof0_rsck_mux[] = {
MSIOF0_RSCK_MARK,
};
static const unsigned int msiof0_tsck_pins[] = {
/* TSCK */
64,
};
static const unsigned int msiof0_tsck_mux[] = {
MSIOF0_TSCK_MARK,
};
static const unsigned int msiof0_rsync_pins[] = {
/* RSYNC */
67,
};
static const unsigned int msiof0_rsync_mux[] = {
MSIOF0_RSYNC_MARK,
};
static const unsigned int msiof0_tsync_pins[] = {
/* TSYNC */
63,
};
static const unsigned int msiof0_tsync_mux[] = {
MSIOF0_TSYNC_MARK,
};
static const unsigned int msiof0_ss1_pins[] = {
/* SS1 */
62,
};
static const unsigned int msiof0_ss1_mux[] = {
MSIOF0_SS1_MARK,
};
static const unsigned int msiof0_ss2_pins[] = {
/* SS2 */
71,
};
static const unsigned int msiof0_ss2_mux[] = {
MSIOF0_SS2_MARK,
};
static const unsigned int msiof0_rxd_pins[] = {
/* RXD */
70,
};
static const unsigned int msiof0_rxd_mux[] = {
MSIOF0_RXD_MARK,
};
static const unsigned int msiof0_txd_pins[] = {
/* TXD */
65,
};
static const unsigned int msiof0_txd_mux[] = {
MSIOF0_TXD_MARK,
};
static const unsigned int msiof0_mck0_pins[] = {
/* MSCK0 */
68,
};
static const unsigned int msiof0_mck0_mux[] = {
MSIOF0_MCK0_MARK,
};
static const unsigned int msiof0_mck1_pins[] = {
/* MSCK1 */
69,
};
static const unsigned int msiof0_mck1_mux[] = {
MSIOF0_MCK1_MARK,
};
static const unsigned int msiof0l_rsck_pins[] = {
/* RSCK */
214,
};
static const unsigned int msiof0l_rsck_mux[] = {
MSIOF0L_RSCK_MARK,
};
static const unsigned int msiof0l_tsck_pins[] = {
/* TSCK */
219,
};
static const unsigned int msiof0l_tsck_mux[] = {
MSIOF0L_TSCK_MARK,
};
static const unsigned int msiof0l_rsync_pins[] = {
/* RSYNC */
215,
};
static const unsigned int msiof0l_rsync_mux[] = {
MSIOF0L_RSYNC_MARK,
};
static const unsigned int msiof0l_tsync_pins[] = {
/* TSYNC */
217,
};
static const unsigned int msiof0l_tsync_mux[] = {
MSIOF0L_TSYNC_MARK,
};
static const unsigned int msiof0l_ss1_a_pins[] = {
/* SS1 */
207,
};
static const unsigned int msiof0l_ss1_a_mux[] = {
PORT207_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss1_b_pins[] = {
/* SS1 */
210,
};
static const unsigned int msiof0l_ss1_b_mux[] = {
PORT210_MSIOF0L_SS1_MARK,
};
static const unsigned int msiof0l_ss2_a_pins[] = {
/* SS2 */
208,
};
static const unsigned int msiof0l_ss2_a_mux[] = {
PORT208_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_ss2_b_pins[] = {
/* SS2 */
211,
};
static const unsigned int msiof0l_ss2_b_mux[] = {
PORT211_MSIOF0L_SS2_MARK,
};
static const unsigned int msiof0l_rxd_pins[] = {
/* RXD */
221,
};
static const unsigned int msiof0l_rxd_mux[] = {
MSIOF0L_RXD_MARK,
};
static const unsigned int msiof0l_txd_pins[] = {
/* TXD */
222,
};
static const unsigned int msiof0l_txd_mux[] = {
MSIOF0L_TXD_MARK,
};
static const unsigned int msiof0l_mck0_pins[] = {
/* MSCK0 */
212,
};
static const unsigned int msiof0l_mck0_mux[] = {
MSIOF0L_MCK0_MARK,
};
static const unsigned int msiof0l_mck1_pins[] = {
/* MSCK1 */
213,
};
static const unsigned int msiof0l_mck1_mux[] = {
MSIOF0L_MCK1_MARK,
};
/* - MSIOF1 ----------------------------------------------------------------- */
static const unsigned int msiof1_rsck_pins[] = {
/* RSCK */
234,
};
static const unsigned int msiof1_rsck_mux[] = {
MSIOF1_RSCK_MARK,
};
static const unsigned int msiof1_tsck_pins[] = {
/* TSCK */
232,
};
static const unsigned int msiof1_tsck_mux[] = {
MSIOF1_TSCK_MARK,
};
static const unsigned int msiof1_rsync_pins[] = {
/* RSYNC */
235,
};
static const unsigned int msiof1_rsync_mux[] = {
MSIOF1_RSYNC_MARK,
};
static const unsigned int msiof1_tsync_pins[] = {
/* TSYNC */
231,
};
static const unsigned int msiof1_tsync_mux[] = {
MSIOF1_TSYNC_MARK,
};
static const unsigned int msiof1_ss1_pins[] = {
/* SS1 */
238,
};
static const unsigned int msiof1_ss1_mux[] = {
MSIOF1_SS1_MARK,
};
static const unsigned int msiof1_ss2_pins[] = {
/* SS2 */
239,
};
static const unsigned int msiof1_ss2_mux[] = {
MSIOF1_SS2_MARK,
};
static const unsigned int msiof1_rxd_pins[] = {
/* RXD */
233,
};
static const unsigned int msiof1_rxd_mux[] = {
MSIOF1_RXD_MARK,
};
static const unsigned int msiof1_txd_pins[] = {
/* TXD */
230,
};
static const unsigned int msiof1_txd_mux[] = {
MSIOF1_TXD_MARK,
};
static const unsigned int msiof1_mck0_pins[] = {
/* MSCK0 */
236,
};
static const unsigned int msiof1_mck0_mux[] = {
MSIOF1_MCK0_MARK,
};
static const unsigned int msiof1_mck1_pins[] = {
/* MSCK1 */
237,
};
static const unsigned int msiof1_mck1_mux[] = {
MSIOF1_MCK1_MARK,
};
/* - MSIOF2 ----------------------------------------------------------------- */
static const unsigned int msiof2_rsck_pins[] = {
/* RSCK */
151,
};
static const unsigned int msiof2_rsck_mux[] = {
MSIOF2_RSCK_MARK,
};
static const unsigned int msiof2_tsck_pins[] = {
/* TSCK */
135,
};
static const unsigned int msiof2_tsck_mux[] = {
MSIOF2_TSCK_MARK,
};
static const unsigned int msiof2_rsync_pins[] = {
/* RSYNC */
152,
};
static const unsigned int msiof2_rsync_mux[] = {
MSIOF2_RSYNC_MARK,
};
static const unsigned int msiof2_tsync_pins[] = {
/* TSYNC */
133,
};
static const unsigned int msiof2_tsync_mux[] = {
MSIOF2_TSYNC_MARK,
};
static const unsigned int msiof2_ss1_a_pins[] = {
/* SS1 */
131,
};
static const unsigned int msiof2_ss1_a_mux[] = {
PORT131_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss1_b_pins[] = {
/* SS1 */
153,
};
static const unsigned int msiof2_ss1_b_mux[] = {
PORT153_MSIOF2_SS1_MARK,
};
static const unsigned int msiof2_ss2_a_pins[] = {
/* SS2 */
132,
};
static const unsigned int msiof2_ss2_a_mux[] = {
PORT132_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_ss2_b_pins[] = {
/* SS2 */
156,
};
static const unsigned int msiof2_ss2_b_mux[] = {
PORT156_MSIOF2_SS2_MARK,
};
static const unsigned int msiof2_rxd_a_pins[] = {
/* RXD */
130,
};
static const unsigned int msiof2_rxd_a_mux[] = {
PORT130_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_rxd_b_pins[] = {
/* RXD */
157,
};
static const unsigned int msiof2_rxd_b_mux[] = {
PORT157_MSIOF2_RXD_MARK,
};
static const unsigned int msiof2_txd_pins[] = {
/* TXD */
134,
};
static const unsigned int msiof2_txd_mux[] = {
MSIOF2_TXD_MARK,
};
static const unsigned int msiof2_mck0_pins[] = {
/* MSCK0 */
154,
};
static const unsigned int msiof2_mck0_mux[] = {
MSIOF2_MCK0_MARK,
};
static const unsigned int msiof2_mck1_pins[] = {
/* MSCK1 */
155,
};
static const unsigned int msiof2_mck1_mux[] = {
MSIOF2_MCK1_MARK,
};
static const unsigned int msiof2r_tsck_pins[] = {
/* TSCK */
248,
};
static const unsigned int msiof2r_tsck_mux[] = {
MSIOF2R_TSCK_MARK,
};
static const unsigned int msiof2r_tsync_pins[] = {
/* TSYNC */
249,
};
static const unsigned int msiof2r_tsync_mux[] = {
MSIOF2R_TSYNC_MARK,
};
static const unsigned int msiof2r_rxd_pins[] = {
/* RXD */
244,
};
static const unsigned int msiof2r_rxd_mux[] = {
MSIOF2R_RXD_MARK,
};
static const unsigned int msiof2r_txd_pins[] = {
/* TXD */
245,
};
static const unsigned int msiof2r_txd_mux[] = {
MSIOF2R_TXD_MARK,
};
/* - MSIOF3 (Pin function name of MSIOF3 is named BBIF1) -------------------- */
static const unsigned int msiof3_rsck_pins[] = {
/* RSCK */
115,
};
static const unsigned int msiof3_rsck_mux[] = {
BBIF1_RSCK_MARK,
};
static const unsigned int msiof3_tsck_pins[] = {
/* TSCK */
112,
};
static const unsigned int msiof3_tsck_mux[] = {
BBIF1_TSCK_MARK,
};
static const unsigned int msiof3_rsync_pins[] = {
/* RSYNC */
116,
};
static const unsigned int msiof3_rsync_mux[] = {
BBIF1_RSYNC_MARK,
};
static const unsigned int msiof3_tsync_pins[] = {
/* TSYNC */
113,
};
static const unsigned int msiof3_tsync_mux[] = {
BBIF1_TSYNC_MARK,
};
static const unsigned int msiof3_ss1_pins[] = {
/* SS1 */
117,
};
static const unsigned int msiof3_ss1_mux[] = {
BBIF1_SS1_MARK,
};
static const unsigned int msiof3_ss2_pins[] = {
/* SS2 */
109,
};
static const unsigned int msiof3_ss2_mux[] = {
BBIF1_SS2_MARK,
};
static const unsigned int msiof3_rxd_pins[] = {
/* RXD */
111,
};
static const unsigned int msiof3_rxd_mux[] = {
BBIF1_RXD_MARK,
};
static const unsigned int msiof3_txd_pins[] = {
/* TXD */
114,
};
static const unsigned int msiof3_txd_mux[] = {
BBIF1_TXD_MARK,
};
static const unsigned int msiof3_flow_pins[] = {
/* FLOW */
117,
};
static const unsigned int msiof3_flow_mux[] = {
BBIF1_FLOW_MARK,
};
/* - SCIFA0 ----------------------------------------------------------------- */
static const unsigned int scifa0_data_pins[] = {
/* RXD, TXD */
43, 17,
};
static const unsigned int scifa0_data_mux[] = {
SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
};
static const unsigned int scifa0_clk_pins[] = {
/* SCK */
16,
};
static const unsigned int scifa0_clk_mux[] = {
SCIFA0_SCK_MARK,
};
static const unsigned int scifa0_ctrl_pins[] = {
/* RTS, CTS */
42, 44,
};
static const unsigned int scifa0_ctrl_mux[] = {
SCIFA0_RTS__MARK, SCIFA0_CTS__MARK,
};
/* - SCIFA1 ----------------------------------------------------------------- */
static const unsigned int scifa1_data_pins[] = {
/* RXD, TXD */
228, 225,
};
static const unsigned int scifa1_data_mux[] = {
SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
};
static const unsigned int scifa1_clk_pins[] = {
/* SCK */
226,
};
static const unsigned int scifa1_clk_mux[] = {
SCIFA1_SCK_MARK,
};
static const unsigned int scifa1_ctrl_pins[] = {
/* RTS, CTS */
227, 229,
};
static const unsigned int scifa1_ctrl_mux[] = {
SCIFA1_RTS__MARK, SCIFA1_CTS__MARK,
};
/* - SCIFA2 ----------------------------------------------------------------- */
static const unsigned int scifa2_data_0_pins[] = {
/* RXD, TXD */
155, 154,
};
static const unsigned int scifa2_data_0_mux[] = {
SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,