)]}'
{
  "commit": "06ed7e7e7aa656f7054af7d3d3387a07244d85b1",
  "tree": "f1dd2c33eacb8c0952399a3f683ae1c8cb232455",
  "parents": [
    "1e1b90d46d0ca616a82e99972e0a56058d5336c8"
  ],
  "author": {
    "name": "FUJITA Tomonori",
    "email": "fujita.tomonori@gmail.com",
    "time": "Sun Dec 28 21:05:46 2025 +0900"
  },
  "committer": {
    "name": "Boqun Feng",
    "email": "boqun.feng@gmail.com",
    "time": "Tue Dec 30 09:34:40 2025 +0800"
  },
  "message": "rust: sync: atomic: Add i8/i16 xchg and cmpxchg support\n\nAdd atomic xchg and cmpxchg operation support for i8 and i16 types\nwith tests.\n\nNote that since the current implementation of\nAtomic::\u003c{i8,i16}\u003e::{load,store}() is READ_ONCE()/WRITE_ONCE()-based.\nThe atomicity between load/store and xchg/cmpxchg is only guaranteed if\nthe architecture has native RmW support, hence i8/i16 is currently\nAtomicImpl only when CONFIG_ARCH_SUPPORTS_ATOMIC_RWM\u003dy.\n\n[boqun: Make i8/i16 AtomicImpl only when\nCONFIG_ARCH_SUPPORTS_ATOMIC_RWM\u003dy]\n\nSigned-off-by: FUJITA Tomonori \u003cfujita.tomonori@gmail.com\u003e\nSigned-off-by: Boqun Feng \u003cboqun.feng@gmail.com\u003e\nLink: https://patch.msgid.link/20251228120546.1602275-4-fujita.tomonori@gmail.com\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1b2a7933bc14ba038c5b1cf1038b0d7a8438ea1b",
      "old_mode": 33188,
      "old_path": "rust/kernel/sync/atomic/internal.rs",
      "new_id": "0dac58bca2b30558e7ec1755b6ae09a10e02a629",
      "new_mode": 33188,
      "new_path": "rust/kernel/sync/atomic/internal.rs"
    },
    {
      "type": "modify",
      "old_id": "51e9df0cf56edeb1cc76950a86f73d43a149acbd",
      "old_mode": 33188,
      "old_path": "rust/kernel/sync/atomic/predefine.rs",
      "new_id": "248d26555ccf67a087557f9e225abf26f4625e1a",
      "new_mode": 33188,
      "new_path": "rust/kernel/sync/atomic/predefine.rs"
    }
  ]
}