tree 0a53ecdc88999040c5c1d760740b06c80aed05b9
parent 71bd98aff05a644a2cfc3ac6ca848a586fa210b9
author Rob Herring <rob.herring@calxeda.com> 1366213612 -0500
committer Olof Johansson <olof@lixom.net> 1366303066 -0700

ARM: highbank: fix cache flush ordering for cpu hotplug

The L1 data cache flush needs to be after highbank_set_cpu_jump call which
pollutes the cache with the l2x0_lock. This causes other cores to deadlock
waiting for the l2x0_lock. Moving the flush of the entire data cache after
highbank_set_cpu_jump fixes the problem. Use flush_cache_louis instead of
flush_cache_all are that is sufficient to flush only the L1 data cache.
flush_cache_louis did not exist when highbank_cpu_die was originally
written.

With PL310 errata 769419 enabled, a wmb is inserted into idle which takes
the l2x0_lock. This makes the problem much more easily hit and causes
reset to hang.

Reported-by: Paolo Pisati <p.pisati@gmail.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Olof Johansson <olof@lixom.net>