| From: Chen-Yu Tsai <wens@csie.org> |
| Date: Mon, 6 Jan 2020 11:09:22 +0800 |
| Subject: net: stmmac: dwmac-sunxi: Allow all RGMII modes |
| |
| commit 52cc73e5404c7ba0cbfc50cb4c265108c84b3d5a upstream. |
| |
| Allow all the RGMII modes to be used. This would allow us to represent |
| the hardware better in the device tree with RGMII_ID where in most |
| cases the PHY's internal delay for both RX and TX are used. |
| |
| Fixes: af0bd4e9ba80 ("net: stmmac: sunxi platform extensions for GMAC in Allwinner A20 SoC's") |
| Signed-off-by: Chen-Yu Tsai <wens@csie.org> |
| Signed-off-by: David S. Miller <davem@davemloft.net> |
| Signed-off-by: Ben Hutchings <ben@decadent.org.uk> |
| --- |
| drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c |
| +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-sunxi.c |
| @@ -78,7 +78,7 @@ static int sun7i_gmac_init(struct platfo |
| * rate, which then uses the auto-reparenting feature of the |
| * clock driver, and enabling/disabling the clock. |
| */ |
| - if (gmac->interface == PHY_INTERFACE_MODE_RGMII) { |
| + if (phy_interface_mode_is_rgmii(gmac->interface)) { |
| clk_set_rate(gmac->tx_clk, SUN7I_GMAC_GMII_RGMII_RATE); |
| clk_prepare_enable(gmac->tx_clk); |
| gmac->clk_enabled = 1; |
