)]}' { "log": [ { "commit": "2f2db618fe4dd8f37539e527480c88f6dd093e78", "tree": "b19130e7f5dc8ac5fe3c3ceba36ef0497fb34c62", "parents": [ "b652c443c4b2100d3ff6e87baed5869744af3a92" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 14:13:51 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:22 2012 -0400" }, "message": "ARM: keystone: add support for coherent dma\n\nThis patch adds a bus notifier that walks up the device tree, looking for a\n\"dma-coherent\" property in the device\u0027s node, and its ancestors. If this\nproperty is found, the notifier callback applies coherent dma ops for the\ndevice.\n" }, { "commit": "b652c443c4b2100d3ff6e87baed5869744af3a92", "tree": "a2c4a298b5bb55346b21ca21a5493271957a3c87", "parents": [ "a2bab9d57c37a15250bd944d00dfcf18282cd002" ], "author": { "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com", "time": "Tue Sep 11 07:39:48 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:22 2012 -0400" }, "message": "ARM: dma-mapping: Refrain noisy console message\n\nWith many IOMMU\u0027able devices, console gets noisy.\n\nTegra30 has a few dozen of IOMMU\u0027able devices.\n\nSigned-off-by: Hiroshi Doyu \u003chdoyu@nvidia.com\u003e\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "a2bab9d57c37a15250bd944d00dfcf18282cd002", "tree": "1c753579b404e3c0181c5f169ace2494b7dd0cfc", "parents": [ "6287018d9798f85b28c0ed9e804724080d736590" ], "author": { "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com", "time": "Tue Sep 11 07:39:39 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:22 2012 -0400" }, "message": "ARM: dma-mapping: Small logical clean up\n\nSkip unnecessary operations if order \u003d\u003d 0. A little bit easier to\nread.\n\nSigned-off-by: Hiroshi Doyu \u003chdoyu@nvidia.com\u003e\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "6287018d9798f85b28c0ed9e804724080d736590", "tree": "3d972fb8a89eece70a079241baa82050e35f9150", "parents": [ "1003e91f49c18dc105d533a8e28f5ad870f31261" ], "author": { "name": "Michal Nazarewicz", "email": "mina86@mina86.com", "time": "Wed Sep 05 07:50:41 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:22 2012 -0400" }, "message": "drivers: dma-contiguous: refactor dma_alloc_from_contiguous()\n\nThe dma_alloc_from_contiguous() function returns either a valid pointer\nto a page structure or NULL, the error code set when pageno \u003e\u003d cma-\u003ecount\nis not used at all and can be safely removed.\n\nThis commit also changes the function to avoid goto and have only one exit\npath and one place where mutex is unlocked.\n\nSigned-off-by: Michal Nazarewicz \u003cmina86@mina86.com\u003e\n[fixed compilation break caused by missing semicolon]\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "1003e91f49c18dc105d533a8e28f5ad870f31261", "tree": "95e6a430d282542661b75de3616b014190250c1b", "parents": [ "c9b1081893f7dc879fe83c4d96818b07a0816bdc" ], "author": { "name": "Hiroshi Doyu", "email": "hdoyu@nvidia.com", "time": "Tue Sep 11 07:43:59 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:22 2012 -0400" }, "message": "ARM: dma-mapping: Remove unsed var at arm_coherent_iommu_unmap_page\n\nSigned-off-by: Hiroshi Doyu \u003chdoyu@nvidia.com\u003e\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "c9b1081893f7dc879fe83c4d96818b07a0816bdc", "tree": "cb9d884680e576bb6323d2fedd6cdf5bc32e0bbe", "parents": [ "939368e650a0b214e42cef921f552c1c0635a560" ], "author": { "name": "Rob Herring", "email": "rob.herring@calxeda.com", "time": "Tue Aug 21 12:23:23 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:21 2012 -0400" }, "message": "ARM: add coherent iommu dma ops\n\nRemove arch_is_coherent() from iommu dma ops and implement separate\ncoherent ops functions.\n\nSigned-off-by: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "939368e650a0b214e42cef921f552c1c0635a560", "tree": "f5682ff16f2fdbf8c9539b547e53d55f54e82343", "parents": [ "88a078ec098b41f8fba00c853f77311c6b41a3ed" ], "author": { "name": "Rob Herring", "email": "rob.herring@calxeda.com", "time": "Tue Aug 21 12:20:17 2012 +0200" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:21 2012 -0400" }, "message": "ARM: add coherent dma ops\n\narch_is_coherent is problematic as it is a global symbol. This\ndoesn\u0027t work for multi-platform kernels or platforms which can support\nper device coherent DMA.\n\nThis adds arm_coherent_dma_ops to be used for devices which connected\ncoherently (i.e. to the ACP port on Cortex-A9 or A15). The arm_dma_ops\nare modified at boot when arch_is_coherent is true.\n\nSigned-off-by: Rob Herring \u003crob.herring@calxeda.com\u003e\nCc: Russell King \u003clinux@arm.linux.org.uk\u003e\nCc: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\nSigned-off-by: Marek Szyprowski \u003cm.szyprowski@samsung.com\u003e\n" }, { "commit": "88a078ec098b41f8fba00c853f77311c6b41a3ed", "tree": "70a6c95ab938aea79e27afb523d7cb685d8582fa", "parents": [ "84a5c77765c556496707300f20d537949f37d234" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 12:47:46 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:21 2012 -0400" }, "message": "ARM: use phys_addr_t in pfn_to_kaddr()\n\nThis patch fixes pfn_to_kaddr() to use phys_addr_t. Without this, this macro\nis broken on LPAE systems.\n" }, { "commit": "84a5c77765c556496707300f20d537949f37d234", "tree": "9c2ca9a9a4b80f3f2d801c23176e1fe6835803c5", "parents": [ "372fc3d98c907da78bd570948792c652a9bb8361" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 12:46:31 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:21 2012 -0400" }, "message": "ARM: keystone: override dma address conversion helpers\n\nThis patch adds keystone specific overrides for helper functions that convert\nback and forth between dma_addr_t and physical/virtual addresses.\n" }, { "commit": "372fc3d98c907da78bd570948792c652a9bb8361", "tree": "a7d6ee20cced0b7d4e13603a30401d4609aa111c", "parents": [ "efc8d3c14a8c30a401a1f896922bebbc98333715" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 10:45:32 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "tci6614: add pm-runtime to defconfig\n" }, { "commit": "efc8d3c14a8c30a401a1f896922bebbc98333715", "tree": "9ec4b7fd808dd2f9cf2b7f457cc2ff3ef6a9e153", "parents": [ "89acd2559abfd7c0cc031910acfe1fedfad4e2d4" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 10:44:34 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "tci6614: cleanup defconfigs\n\nRe-align for the 50th time with savedefconfig. Jeez!\n" }, { "commit": "89acd2559abfd7c0cc031910acfe1fedfad4e2d4", "tree": "4278452a6e8164f2dbd9e8e06581e7db33674f39", "parents": [ "37ca07f898556798bf732abfa8f7bf4f05fcb2c8" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Sep 20 10:28:19 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "tci6614: add fake fck clock for mdio\n\nThis patch adds a fake fck clock for the mdio module. This is required for\nthe new pm-runtime enabled mdio driver in the mainline 3.6 kernel code.\n" }, { "commit": "37ca07f898556798bf732abfa8f7bf4f05fcb2c8", "tree": "66866a95fd03b46614c387ba5faa2abcf7834573", "parents": [ "7df20a57fd203b2409c8fbc8f7900b2d649d5b9a" ], "author": { "name": "Mugunthan V N", "email": "mugunthanvnm@ti.com", "time": "Mon Aug 06 05:05:57 2012 +0000" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "drivers: net: ethernet: davince_mdio: device tree implementation\n\ndevice tree implementation for davinci mdio driver\n\nSigned-off-by: Mugunthan V N \u003cmugunthanvnm@ti.com\u003e\nSigned-off-by: David S. Miller \u003cdavem@davemloft.net\u003e\n" }, { "commit": "7df20a57fd203b2409c8fbc8f7900b2d649d5b9a", "tree": "1c13c35634dba419df62f886cf3b978d52f341df", "parents": [ "bb11673fea0d591342929a39686b0d8ca9df190a" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Wed Sep 19 19:51:17 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "davinci: fix decompressor crash on non-uart platforms\n\nThe decompressor debug macro definitions for davinci crash miserably on\nplatforms that do not have a UART defined. This is a problem for pure-DT\nplatforms such as TCI6614, where an early UART definition is unavailable in\nthe decompressor.\n\nThis patch makes the UART usage in the decompressor truly optional.\n" }, { "commit": "bb11673fea0d591342929a39686b0d8ca9df190a", "tree": "53464ce33c712c1821e1aa68f365ff4ae53b3f07", "parents": [ "93504db548ea4cdecc8c655bf52caff090071fd2" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Wed Sep 19 15:31:58 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:20 2012 -0400" }, "message": "tci6614: add jtag-id to support PG 1.3\n\nFor PG 1.3, a new variant value of 1 is used. So add this to the list of\ndavinci ids.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "93504db548ea4cdecc8c655bf52caff090071fd2", "tree": "6c79fc04adf30a1560f8dc5cc5a1589b34b3eb9c", "parents": [ "fdef6ea75b9e0b733c2893c28a22dd961779a36c" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Wed Sep 19 17:47:46 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:19 2012 -0400" }, "message": "tci6614: remove decompressor uart config for tci6614\n\nThis patch removes the decompress time uart setup for early-printk. This does\nnot work any more, now that mach-types definitions have been removed.\n\nSubsequent mainline patches will restore this functionality, but for the time\nbeing we\u0027re living without decompress time debug support.\n" }, { "commit": "fdef6ea75b9e0b733c2893c28a22dd961779a36c", "tree": "6cc5c7c6367a16743ddd2bec291bbabf5e278b8d", "parents": [ "2e67662efd2b97fa08fcd926445883297ea4e4b4" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Wed Sep 19 17:46:53 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:19 2012 -0400" }, "message": "tci6614: use DT_MACHINE_START() to avoid mach-type definition\n\nThis patch uses DT_MACHINE_START() instead of MACHINE_START(), allowing us to\nget by without adding our fake entries into the mach-types table.\n" }, { "commit": "2e67662efd2b97fa08fcd926445883297ea4e4b4", "tree": "eb3bc13321db7955fd53c1e9a83c6d090421c629", "parents": [ "ea8370844cd76927a851d4d31b013aa73caf8c43" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 14:31:43 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:19 2012 -0400" }, "message": "tci6614: add default config for evaluation module\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "ea8370844cd76927a851d4d31b013aa73caf8c43", "tree": "037658f8391c13043c14631eaa6b5ab510dc310b", "parents": [ "be6c1cf33606ceaa876f24a3e05f16b6096bb7a0" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 14:31:21 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:19 2012 -0400" }, "message": "tci6614: add default config for evm with cache disabled\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "be6c1cf33606ceaa876f24a3e05f16b6096bb7a0", "tree": "acbf511702f2b613be2147752cca3dafc04f8d4c", "parents": [ "6e3f4a3f292544d2ae3e24825b133b02159218e1" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Nov 21 16:26:11 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "tci6614: add default config for simulator board\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "6e3f4a3f292544d2ae3e24825b133b02159218e1", "tree": "02e18c48cd140643a9771d68ad5ae2ef3f387c7c", "parents": [ "f815603baf99ea03f945cb84a16645d2f2a7e24b" ], "author": { "name": "WingMan Kwok", "email": "w-kwok2@ti.com", "time": "Tue Aug 07 17:19:24 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "tci6614: added rapid io config for tci6614 evm\n\nSigned-off-by: WingMan Kwok \u003cw-kwok2@ti.com\u003e\n" }, { "commit": "f815603baf99ea03f945cb84a16645d2f2a7e24b", "tree": "66a1de3d61d103c4e7aa437e75634aebd589141e", "parents": [ "4bde64d1d4c51bf44078002ab2bc223ad342f58c" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Sun Jul 22 09:54:19 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "ARM: keystone: add switch over to high physical address range\n\nKeystone platforms have their physical memory mapped at an address outside the\n32-bit physical range. A Keystone machine with 16G of RAM would find its\nmemory at 0x0800000000 - 0x0bffffffff.\n\nFor boot purposes, the interconnect supports a limited alias of some of this\nmemory within the 32-bit addressable space (0x80000000 - 0xffffffff). This\naliasing is implemented in hardware, and is not intended to be used much\nbeyond boot. For instance, DMA coherence does not work when running out of\nthis aliased address space.\n\nTherefore, we\u0027ve taken the approach of booting out of the low physical address\nrange, and subsequently we switch over to the high range once we\u0027re safely\ninside machine specific territory. This patch implements this switch over\nmechanism, which involves rewiring the TTBRs and page tables to point to the\nnew physical address space.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "4bde64d1d4c51bf44078002ab2bc223ad342f58c", "tree": "b9a917ee821b0e87e6a4be73c529195dfb02cd45", "parents": [ "a1c249d2cd613ea4f9dc313778e560369f095981" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Sun Jul 22 09:19:36 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "ARM: keystone: enable SMP on Keystone machines\n\nThis patch adds basic SMP support for Keystone machines. Nothing very fancy\nhere, just enough to get 4 CPUs booted up. This does not include support for\nhotplug, etc.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "a1c249d2cd613ea4f9dc313778e560369f095981", "tree": "cee5fc237fd81778ea7f7ece0b0aa357513c58e9", "parents": [ "0e4ac0a763e2dc011f5993678cf795110272b06c" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Sun Jul 22 08:31:48 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "ARM: keystone: introducing TI Keystone platform\n\nTexas Instruments Keystone family of multicore devices now includes an\nupcoming slew of Cortex A15 based devices. This patch adds basic definitions\nfor a new Keystone sub-architecture in ARM.\n\nSubsequent patches in this series will extend support to include SMP and take\nadvantage of the large physical memory addressing capabilities via LPAE.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nReviewed-by: Arnd Bergmann \u003carnd@arndb.de\u003e\n" }, { "commit": "0e4ac0a763e2dc011f5993678cf795110272b06c", "tree": "1301f56cb161131d6baf8318e9745f66b517869f", "parents": [ "181fa5ccb96b73e5ddaaa622834735a895f3c06a" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Jul 20 21:40:31 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:18 2012 -0400" }, "message": "ARM: recreate kernel mappings in early_paging_init()\n\nThis patch adds a step in the init sequence, in order to recreate the kernel\ncode/data page table mappings prior to full paging initialization. This is\nnecessary on LPAE systems that run out of a physical address space outside the\n4G limit. On these systems, this implementation provides a machine descriptor\nhook that allows the PHYS_OFFSET to be overridden in a machine specific\nfashion.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\n" }, { "commit": "181fa5ccb96b73e5ddaaa622834735a895f3c06a", "tree": "e61bb3766409df16cdcfab55685cc63c21525df9", "parents": [ "1e1919b34866db079d20474405981d1ece7e04ec" ], "author": { "name": "Vitaly Andrianov", "email": "vitalya@ti.com", "time": "Thu Jun 21 07:57:25 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:17 2012 -0400" }, "message": "ARM: add virt_to_idmap for interconnect aliasing\n\nOn some PAE systems (e.g. TI Keystone), memory is above the 32-bit addressible\nlimit, and the interconnect provides an aliased view of parts of physical\nmemory in the 32-bit addressible space. This alias is strictly for boot time\nusage, and is not otherwise usable because of coherency limitations.\n\nOn such systems, the idmap mechanism needs to take this aliased mapping into\naccount. This patch introduces a virt_to_idmap() macro, which can be used on\nsuch sub-architectures to represent the interconnect supported boot time\nalias. Most other systems would leave this macro untouched, i.e., do a simply\nvirt_to_phys() and nothing more.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "1e1919b34866db079d20474405981d1ece7e04ec", "tree": "3e7443b7a9f2919e1a7c721f6bf6141aae2ddc60", "parents": [ "9926dd16385573735ec283fa2a84307025fd1692" ], "author": { "name": "Jonathan Austin", "email": "(address hidden)", "time": "Tue Sep 11 12:52:22 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:17 2012 -0400" }, "message": "delay: add registration mechanism for delay timer sources\n\nThe current timer-based delay loop relies on the architected timer to\ninitiate the switch away from the polling-based implementation. This is\nunfortunate for platforms without the architected timers but with a\nsuitable delay source (that is, constant frequency, always powered-up\nand ticking as long as the CPUs are online).\n\nThis patch introduces a registration mechanism for the delay timer\n(which provides an unconditional read_current_timer implementation) and\nupdates the architected timer code to use the new interface.\n\nReviewed-by: Stephen Boyd \u003c(address hidden)\u003e\nSigned-off-by: Jonathan Austin \u003c(address hidden)\u003e\nSigned-off-by: Will Deacon \u003c(address hidden)\u003e\n" }, { "commit": "9926dd16385573735ec283fa2a84307025fd1692", "tree": "899bd45c28340d75aba338858de20c29ec4139bc", "parents": [ "712f43097b9f4b341654058abb86dbb13d09fe8c" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Wed Sep 12 10:21:26 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:17 2012 -0400" }, "message": "ARM: fix warning on uninitialized offset.un\n\nThis patch fixes the following warning:\n\narch/arm/mm/alignment.c: In function \u0027do_alignment\u0027:\narch/arm/mm/alignment.c:327:15: warning: \u0027offset.un\u0027 may be used uninitialized in this function [-Wmaybe-uninitialized]\narch/arm/mm/alignment.c:749:21: note: \u0027offset.un\u0027 was declared here\n\nThe fix is to promote the initialization of offset into do_alignment().\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "712f43097b9f4b341654058abb86dbb13d09fe8c", "tree": "04567e690f51f3524d11a34ffda1e420194c0c2b", "parents": [ "537cebb96334f74d383fee1a1b02c46cc2024822" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Wed Sep 12 10:19:05 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:16 2012 -0400" }, "message": "ARM: fix type of PHYS_PFN_OFFSET to unsigned long\n\nOn LPAE machines, PHYS_OFFSET evaluates to a phys_addr_t and this type is\ninherited by the PHYS_PFN_OFFSET definition as well. Consequently, the kernel\nbuild emits warnings of the form:\n\ninit/main.c: In function \u0027start_kernel\u0027:\ninit/main.c:588:7: warning: format \u0027%lx\u0027 expects argument of type \u0027long unsigned int\u0027, but argument 2 has type \u0027phys_addr_t\u0027 [-Wformat]\n\nThis patch fixes this warning by pinning down the PFN type to unsigned long.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "537cebb96334f74d383fee1a1b02c46cc2024822", "tree": "a31f9a5b846fe6790961383f8ada377810df844d", "parents": [ "df126a3be1329377049e0cd1060d8b6da1333938" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Aug 10 18:46:45 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:16 2012 -0400" }, "message": "/dev/mem: use phys_addr_t for physical addresses\n\nThis patch fixes the /dev/mem driver to use phys_addr_t for physical\naddresses. This is required on PAE systems, especially those that run\nentirely out of \u003e4G physical memory space.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "df126a3be1329377049e0cd1060d8b6da1333938", "tree": "aa68d6c3dfc7e0f8ded5aa51c81552deeadb424d", "parents": [ "9d50beea27bebddfe3b2eb75e3fbf04e8937f631" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Aug 10 07:57:27 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:16 2012 -0400" }, "message": "of: specify initrd location using 64-bit\n\nOn some PAE architectures, the entire range of physical memory could reside\noutside the 32-bit limit. These systems need the ability to specify the\ninitrd location using 64-bit numbers.\n\nThis patch globally modifies the early_init_dt_setup_initrd_arch() function to\nuse 64-bit numbers instead of the current unsigned long.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "9d50beea27bebddfe3b2eb75e3fbf04e8937f631", "tree": "8e2e058b2675d8b80100899fcc2d7439eb6c9a81", "parents": [ "756b8adc4ec7533acaab3ddefaf5bf392b9777a2" ], "author": { "name": "Vitaly Andrianov", "email": "vitalya@ti.com", "time": "Fri Jun 15 13:37:32 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:16 2012 -0400" }, "message": "mm: bootmem: use phys_addr_t for physical addresses\n\nOn a physical address extended (PAE) systems physical memory may be located\noutside the first 4GB address range. In particular, on TI Keystone devices,\nall memory (including lowmem) is located outside the 4G address space. Many\nfunctions in the bootmem.c use unsigned long as a type for physical addresses,\nand this breaks badly on such PAE systems.\n\nThis patch intensively mangles the bootmem allocator to use phys_addr_t where\nnecessary. We are aware that this is most certainly not the way to go\nconsidering that the ARM architecture appears to be moving towards memblock.\nMemblock may be a better solution, and fortunately it looks a lot more PAE\nsavvy than bootmem is.\n\nHowever, we do not fully understand the motivations and restrictions behind\nthe mixed bootmem + memblock model in current ARM code. We hope for a\nmeaningful discussion and useful guidance towards a better solution to this\nproblem.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "756b8adc4ec7533acaab3ddefaf5bf392b9777a2", "tree": "d3f98cf8a5da433be7de402f6af27e172c33580e", "parents": [ "7cef77aa815d7467944b83c30546e4de4c459df6" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Mon Jul 16 18:52:47 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:16 2012 -0400" }, "message": "drivers: cma: fix addressing on PAE machines\n\nThis patch fixes a couple of bugs that otherwise impair CMA functionality on\nPAE machines:\n\n - alignment must be a 64-bit type when running on systems with 64-bit\n physical addresses. If this is not the case, the limit calculation thunks\n allocations down to an address range \u003c 4G.\n\n - The allocated range is now being checked using dma_supported() instead of\n hardcoding a 32-bit addressable limit.\n\nSigned-off-by: Vitaly Andrianov \u003cvitalya@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "7cef77aa815d7467944b83c30546e4de4c459df6", "tree": "bfd43cb940a5183d0ad9cfde8fa2d5e601b9fe12", "parents": [ "550d5ccade02e030fd80222c09b5db3ccdeacfde" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Sep 11 14:29:50 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:15 2012 -0400" }, "message": "crypto: add stub keystone crypto accelerator driver\n\nThis driver only enables the clock for now.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "550d5ccade02e030fd80222c09b5db3ccdeacfde", "tree": "a9a99401437ab871cbb1ea13eed252d1ae6ac0e5", "parents": [ "20d0a30ad28e1eb4952e4e764c3ec29e72c7b860" ], "author": { "name": "Sajesh Kumar Saran", "email": "sajesh@ti.com", "time": "Wed May 09 19:14:55 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:15 2012 -0400" }, "message": "misc: add keystone ipc irq chip\n\nThe keystone ipc interrupt mechanism have 28 source id bits.\nIn this irq chip patch provides 28 ipc interrupts, which are\nderived from source id bits.\n\nFollowing is the source id bits to irq mapping\n\nSrcID\tBit\tIRQ\t\tFor TCI6614\nSRCS0\t4\tbase\t\t512\nSRCS1\t5\tbase + 1\t513\nSRCS2\t6\tbase + 2\t514\nSRCS3\t7\tbase + 3\t515\n........\n........\nSRCS27\t31\tbase + 27\t539\n\nSigned-off-by: Sajesh Kumar Saran \u003csajesh@ti.com\u003e\n" }, { "commit": "20d0a30ad28e1eb4952e4e764c3ec29e72c7b860", "tree": "9ad25ce04aa5f00bbbe3890466b0b5106dd44551", "parents": [ "349829da60edc631f45fc9de427641e88ef78c4d" ], "author": { "name": "WingMan Kwok", "email": "w-kwok2@ti.com", "time": "Wed Aug 08 11:58:36 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:15 2012 -0400" }, "message": "rapidio: keystone: add rapid io driver\n\nSigned-off-by: WingMan Kwok \u003cw-kwok2@ti.com\u003e\nSigned-off-by: Aurelien Jacquiot \u003ca-jacquiot@ti.com\u003e\n" }, { "commit": "349829da60edc631f45fc9de427641e88ef78c4d", "tree": "86fe4610564600df7a656565b956b9cdf5daf6c3", "parents": [ "b8b521f7e75f74f6baabc788186efa5e3ca6ff7d" ], "author": { "name": "WingMan Kwok", "email": "w-kwok2@ti.com", "time": "Tue Aug 07 17:38:29 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:15 2012 -0400" }, "message": "rapidio: remove rio_init_mports from system initcall\n\nCall rio_init_mports in rio_register_mport.\n\nSigned-off-by: WingMan Kwok \u003cw-kwok2@ti.com\u003e\n" }, { "commit": "b8b521f7e75f74f6baabc788186efa5e3ca6ff7d", "tree": "c47bc5ff11b3b0a64ee3bbd2970240049b4849e4", "parents": [ "b5f75e0269ee9db5521a7c9bb2c2d713f5be3fa2" ], "author": { "name": "WingMan Kwok", "email": "w-kwok2@ti.com", "time": "Tue Aug 07 17:32:16 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:15 2012 -0400" }, "message": "rapidio: remove rionet from system initcall.\n\nWorkaround Keystone RapidIO device doorbell issue\n\nSigned-off-by: WingMan Kwok \u003cw-kwok2@ti.com\u003e\n" }, { "commit": "b5f75e0269ee9db5521a7c9bb2c2d713f5be3fa2", "tree": "031bdd50250eb69a59a5409a9345d85835197c3b", "parents": [ "bb9bd4cbb148233a92c57ec19828f263ed1a914a" ], "author": { "name": "WingMan Kwok", "email": "w-kwok2@ti.com", "time": "Tue Aug 07 17:24:26 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "rapidio: added rapid io subsystem config\n\nSigned-off-by: WingMan Kwok \u003cw-kwok2@ti.com\u003e\n" }, { "commit": "bb9bd4cbb148233a92c57ec19828f263ed1a914a", "tree": "9367638b27fe28d5bf7a39ddb59652ce7abb80bc", "parents": [ "68d6163fc0af1c01f8397b80c62d9f036421a217" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 10:40:41 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "net:keystone: add security accelerator module\n\nThis commit adds a security accelerator module\nin the keystone network core engine.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "68d6163fc0af1c01f8397b80c62d9f036421a217", "tree": "b7fe18616d614051633e6da75fbc96588196c146", "parents": [ "ea590abf3a411b22a099293a10e54e7495f300d0" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:30:23 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "net:keystone: add packet accelerator driver\n\nThis commit adds support for the packet acclerator on the\nkeystone devices. The driver downloads the firmware to each of the 6 PDSP\u0027s\nof the packet accelerator. It will also initializes the timers so as to enable\nthe timestamping feature.\nMAC rules are also added to filer mac addresses.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "ea590abf3a411b22a099293a10e54e7495f300d0", "tree": "01b2e62b1f485272febfbda78836255eae70c53c", "parents": [ "c3502d7ff94bc6a21febbecfd9ebc872538d2767" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:29:41 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "net:keystone: add ethernet subsystem driver\n\nThis commit adds an ethernet subsystem driver for the switch on\nkeystone devices. It initializes the host port and initializes\nthe slave ports. the number of slave ports to be initialized depends\non the device tree bindings that are deciede by the user. Depending\non the device tree bindings, the appropriate sgmii api\u0027s will\nbe called to setup the sgmii link in an appropriate way.\n\nIf there is a phy, then the driver will call phylib api\u0027s to monitor\nthe phy.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "c3502d7ff94bc6a21febbecfd9ebc872538d2767", "tree": "129b83098944f2dc45311fb17665424d5fe0e31d", "parents": [ "f6d0447c9cfd9d5f31d93a662292fb60b04a4036" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:29:16 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "net:keystone: add sgmii driver\n\nThe sgmii link can be of 4 differetnt types\n\n- mac-phy\n- mac-mac(forced link)\n- mac-mac(slave)\n- mac-fibre\n\nThis patch improves the sgmii driver by allowing the the interface to\nbe determined by the user. Depending on the user input through device\ntree, the sgmii will be appropriately setup.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "f6d0447c9cfd9d5f31d93a662292fb60b04a4036", "tree": "f49bba1cc6ead7a68bf64457668a877ad5eaa24e", "parents": [ "0c9a8df26a4ded7bd16d8101e8c2b1d9d58baa07" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:33:05 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:14 2012 -0400" }, "message": "net:keystone: add net core driver\n\ns commit adds an ethernet driver for keystone devices which exposes the\nstandard netdev operations.\n\nThe specifics on the device tree bindings for Keystone Network support\ncan be found in:\n Documentation/devicetree/bindings/net/keystone-net.txt\n\n The network driver sets up the streaming switch interface to route all\n packets to PDSP0. At present this is the only mode that is supported\n by the driver. In the near future we intend to add a feature in the driver\n which will enable a user to bypass the PA.\n\n The SGMII ports need to be initialized and appropriately configured.\n SERDES initialization also needs to done. These APIs are found in\n keystone_sgmii.c\n\n The switch and the mac sliver ports need to be configured. In the\n switch we enable all statistics to be collected. All ports of the\n ALE are put in the forward mode.\n\n A private structure is maintained which stores the dma channels and dma\n channel names and rx state. The platform device and network device are also\n stored in this privare structure\n\n each packet has a structure(called netcp_packet) associated with it. This\n comprises of a scatterl;ist array, the number of scatterlist entries, the\n status of the dma and the dma cookie. A pomiter to the skb is also stored in\n this structure.\n\n Model:\n\n 1) Open:\n\n On device open, we request DMA channels using standard dma engine APIs\n provided by the dmaengine layer. The capabilities of the DMA are\n appropriately\n set and the appropriate channels are requested by name. We invoke the\n dma_request_channel_by_name API to acquire dma engine channels. The netdev\n open also sets up the streaming switch, SGMII, Serdes, switch and mac\n sliver.\n Finally we configure the PA\n\n 2) Stop:\n\n A standard netdev stop operation stops the netif queue. It sets the receive\n state to teardown and calls dmaengine_pause APIs from the dmaengine layer to\n pause both the RX and TX channel. After NAPI is disabled, the operation goes\n onto release the dma channels by calling the dma_release_channel API.\n The RX state is set to invalid and the ethernet susbsystem is stopped\n\n 3) Polling\n\n A NAPI poll function is implemented. which sets the RX state to poll and\n resume the dma engine. It will then go onto initialize the queues.\n We allocate memory for each packet and initialize the scatterlist.\n We iterate in a loop till we run out memory for the descriptors.These\n dma descriptors are acquired using a dmaengine API called\n device_prep_slave_sg. We pass appropriate arguments to the API. At this\n instant we are not concerned about the Software info and PS info associated\n with each descriptor. We use a single scatterlist associated with each\n packet.\n netcp_rx_complete is the callback associated with the dma engine on the RX\n side. The callback function checks for the correct DMA and RX state and\n warns\n the user on seeing abnormal behavior. It then goes onto stahs the received\n packet to the tail of a linked list.\n\n 4) Xmit\n\n netcp_ndo_start_xmit is the stanndard netdev operation that is used to push\n an\n outgoing packet. Again we have a structure for each packet. This will\n contain\n an array of scatterlists and the number of scatterlist entries which at this\n point should be 1. We then call the device_prep_slave_sg API with\n appropriate\n parameters to acquire a descriptor for the TX operation. \u0027netcp_tx_complete\u0027\n is the callback fucntion attached to each TX dma callback. All the network\n statistics are appropriately updated on a successful transfer. The callback\n then proceeds to free the skb with the dev_kfree_skb_any API.\n\n 5) Receive\n\n In the napi_poll netdev operation, we call the netcp_refill_rx function\n which\n will allocate skbs and attch these skbs to a descriptor until we run out of\n descriptor memory. the deliver_stash routine fills the appropriate RX\n statictics and send the skb up the stack.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\nnet:keystone: add device tree bindings for keystone net core engine\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "0c9a8df26a4ded7bd16d8101e8c2b1d9d58baa07", "tree": "106cae6a37d7561f7e91b2edf75167b787a75344", "parents": [ "e8657cd42b5b42a283d9e6915669d8a5976d099e" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:32:04 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:13 2012 -0400" }, "message": "net:ti-cpsw: update driver with vlan support\n\nThe existing ti cpsw driver is used in DaVinci and OMAP SOC\u0027s.\nThe address lookup engine driver was enhanced to add support for vlan\u0027s.\nThis required a change in the ale api\u0027s.\nThe driver is being modified to call the api\u0027s with updated arguments.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "e8657cd42b5b42a283d9e6915669d8a5976d099e", "tree": "03379595715c41e9fcee4af5d40deb79052f3108", "parents": [ "66f523c03b5b0eb40626c5f231f32986b297f605" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:31:08 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:13 2012 -0400" }, "message": "net:cpsw-ale: add support for vlan\n\nThe address lookup engine driver did not have support for\nadding/removing vlan entries. Also we can have unicast/multicast\nvlan addresses. These shortcomings have been addressed in this\npatch.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "66f523c03b5b0eb40626c5f231f32986b297f605", "tree": "2e6bf6ef92e382acb0b6fca503ddc24a1624e4ec", "parents": [ "8c7a1a65b17d6d712c6aee4f835c510d3461b450" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Jul 05 11:22:35 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:13 2012 -0400" }, "message": "of/mdio: add context argument to adjust link callback\n\nThis patch implements extensions to device-tree phy interfaces in order to\nhave context information passed back into the adjust link callbacks.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "8c7a1a65b17d6d712c6aee4f835c510d3461b450", "tree": "259cc869f9d9afe01af96ad09277c00ff23ce494", "parents": [ "7b0b2c59558b41a53931f78772f16fed3565e2b0" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 13 11:27:45 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:13 2012 -0400" }, "message": "net: update phy adjust callback\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "7b0b2c59558b41a53931f78772f16fed3565e2b0", "tree": "207f5c1e3df1baf15e6ef6dbc6d23608eb72a979", "parents": [ "2e25ecfd869e15689d1eab2563914cda0a0bc760" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Jul 03 12:00:35 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:13 2012 -0400" }, "message": "phylib: add context argument to adjust link callback\n\nThis patch introduces a context argument for the adjust link callback. This\ncontext information is set at phy_connect() (and its variants), and is passed\nback into the adjust_link callbacks on link state change events.\n\nSuch context information is necessary when a network device has multiple\nunderlying ports. Specifically, this comes into play when the netdev is\nreally one of the ports going into an on-chip switch of some sort.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "2e25ecfd869e15689d1eab2563914cda0a0bc760", "tree": "b183ba636e9a4863258b11a151e9a9dbf3e68fcf", "parents": [ "1a3261fa98b39f283c318024d58469891979fa0b" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Jul 03 11:38:33 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:12 2012 -0400" }, "message": "phylib: factor out handler callouts into helper\n\nThis patch pulls out adjust_link handler callbacks into a helper function. The\npatch does not modify phylib behavior in any material way.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "1a3261fa98b39f283c318024d58469891979fa0b", "tree": "65cff815fd0ecddf5186134763b007dbd93f7b36", "parents": [ "3e3cf16d08ccdba7cc213d004b42340f47dc12a9" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Sep 17 12:41:28 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:12 2012 -0400" }, "message": "dma: keystone: add support for more than 4096 queues\n\nThe existing implementation of the keystone dma engine prevented queues\nabove 4095 from being used. This commit adds support in the keystone dma\nengine to enable queues greater than 4095 to be used.\nAny queue from 4096 to 8192 logically belongs to another queue manager.\nSo based on the queue number we calculate the queue manager number.\nThe existing implementation was never writing the queue manager number into\nthe appropriate locations in the descriptor and the packet dma rx flow\nregister. At reset this value was zero and things worked. While using any\nqueue above 4095, we have to appropriatley calculate the queue manager number\nand put it in the descriptor and the appropriate packet dma rx flow register.\n\nAlso, the driver was not modifying the qm_base_address registers in the\nglobal packet dma control registers. Again on reset, the appropriate value is\nset into QM0 base address register and the others are 0. This also prevents\nqueues greater than 4095 from being used. To this effect, device tree support\nis being added. We can have a maximum of 4 logical queue managers but in the\ncurrent generation of devices we have 2. From device tree we apprise the\ndriver of the number of queue managers using the binding\nlogical-queue-managers. In the device tree we also define the\nqm-base-address for each logical queue manager using an array.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "3e3cf16d08ccdba7cc213d004b42340f47dc12a9", "tree": "f2f0189a5ae6b714409b762f6d3b29bdedd847a6", "parents": [ "1e73a4e989ae4493392887798a6d052ab5f1b2e2" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu May 03 14:12:12 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:12 2012 -0400" }, "message": "dma: add zero copy user mode access to dma channels\n\nThis commit adds a keystone-udma driver that provides zero-copy access from\nuser-space to packet dma channels.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n\ndma: keystone: avoid non-cacheable coherent allocs for dma buffers\n\nThis patch replaces the original DMA coherent allocation with a cacheable\nallocation that is then mapped for DMA usage using streaming dma APIs.\n\ndma: keystone: remember last used vma to speed up map lookups\n\nThis patch accelerates the map search mechanism by remembering the last looked\nup vma on a per-channel basis. This substantially speeds up the common case\nby avoiding expensive mutex operations and find_vma().\n\ndma: keystone: rename dma data and transfer direction fields\n\nThis patch simply renames dma_data_direction and dma_transfer_direction fields\nto improve readability and reduce confusion while reading through the code.\n\nThe dma_data_direction is used for dma map/unmap APIs, i.e., as inputs to the\nDMA-APIs. The dma_transfer_direction, on the other hand, is an argument to\nthe DMA Engine APIs.\n\ndma: keystone: tighten ioctl dispatch\n\nThis patch replaces the ioctl dispatch code with an equivalent, but simpler\nif-then-else structure. In the process, we are also able to provide a branch\nhint to the optimizer, streamlining the handling of the kick data path ioctl.\n\ndma: keystone: gracefully handle descriptor alloc failure\n\nThis patch improves the handling of descriptor allocation failures (i.e.\nfailure returned by device_prep_slave_sg(), by not discarding the transfer\nrequest that faced the allocation failure. This allows this particular\nrequest to be retried at a subsequent kick, when descriptors are likely\navailable.\n\ndma: keystone: optimize data layout\n\nThis patch reorders the layout of key data structures, optimizing it by\ngrouping together elements that are accessed often on a per-packet basis.\n\ndma: keystone: pre-initialize request contents at init\n\nThis patch pre-initializes the static fields of the udma_request structure, so\nas to not have to initialize these in the data path. This also forces a\none-to-one mapping between request and vring descriptor.\n\nudma: Add support for per channel fd\n\nThis is an initial request for comments patch that creates a fd per udma channel.\nThe file operations support release and read. The read fop does not read\nanything currently. It calls the chan_kick() API.\nThe subsequent patches will include support to be able to select on these fd\u0027s.\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\n\nudma: Add select functionality\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\n\nConflicts:\n\n\tinclude/linux/hwqueue.h\n\nudma: update driver to the new scatter gather implementation\n\nThis commit completes a set of patches that changes the udma driver code to\nadd support of select functionality, and to support the new sg implementation\nthat requires a allocator and destructor for each rx channel.\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\n\ndma: keystone: fix udma race on poll\n\nThis patch fixes a condition where a notification fired during a fop_poll\ncould be missed. This would occassionally result in a stuck user-space\napplication.\n\ndma: keystone: add dma_rfree_refill in the udma driver\n\nthis commit adds the dma_rxfree_refill API to the keystone\nudma driver\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndma: keystone: use dmaengine_prep_slave_sg() in udma\n\nThis patch moves udma code over to using the newly added slave dma prep\nfunction.\n\ndma: keystone: update dma header location in udma driver\n" }, { "commit": "1e73a4e989ae4493392887798a6d052ab5f1b2e2", "tree": "1de3703ae99d3d5edcd7e33356cd73fe55ffd2fa", "parents": [ "81358096f88a367a49fc1ddcacc363c8910358fc" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Mar 12 19:08:38 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:12 2012 -0400" }, "message": "dma: add keystone packet dma driver\n\nThis commit adds a dmaengine driver for Keystone Packet DMA hardware. The\ndmaengine interface exposes logical DMA channels to user drivers. These logical\nchannels are explicitly specified via device tree, and are fixed at probe time.\nFurther, dmaengine logical channels are unidirectional, with the direction\nspecified in the device tree. This deviates slightly from the traditional\ndmaengine model, where channels may be used for both to-device and from-device\ndirections.\n\nThe specifics on the device tree bindings for Packet DMA can be found in:\n Documentation/devicetree/bindings/dma/keystone-pktdma.txt\n\nMapping to Packet DMA Hardware :\n--------------------------------\n\nBoth transmit and receive channels map to a pair of underlying hardware\nqueues provided by the hardware queue subsystem. This driver supports only\na strict ring model of descriptor handoff to/from hardware DMAs. More exotic\nmodes of Packet DMA usage are not supported at present. This includes support\nfor packet buffer bins of varying sizes, as well as support for packet\nscatter/gather.\n\nMost of the mappings to hardware resources (tx channels, rx channels, rx\nflows) are optional in this implementation. This allows the Packet DMA driver\nto be used flexibily in a variety of different use cases ranging from direct\nI/O rings with DSPs/accelerators, DMA copied rings with the infrastructure\nDMA, and traditional packet I/O rings with Ethernet and SRIO hardware.\n\nUsage Model:\n------------\n\nHigher level drivers have a consistent usage model independent of the transfer\ndirection. Typically, this involves the following steps:\n\n1. Channel open:\n\n DMA channels are opened using standard dmaengine API calls\n (dma_request_channel or dma_request_channel_by_name). The\n dma_request_channel() interface allows for a flexible \"filter\" model by\n which the requestor may scan and select a channel based on various\n criteria. In the Packet DMA usage model, the \"by name\" variant is expected\n to be used in most scenarios.\n\n2. Transfer request submission:\n\n Once a channel is opened, the user may submit one or more transfer requests\n on the opened channel. This is a three step process:\n\n a. Allocate a transfer descriptor:\n\n The DMA device includes a device_prep_slave_sg() interface which\n allocates and fills up a transfer descriptor based on the contents of a\n scatterlist. Standard Linux for scatterlist manipulation APIs\n (sg_table_init(), dma_map_sg(), etc.) apply here.\n\n The Keystone Packet DMA recognizes a couple of extra flags in the\n device_prep_slave_sg() call. These flags indicate the presence of\n \"software info\" and/or \"protocol specific\" info as required by the user\n driver. When so indicated, the software/protocol info buffers are\n passed as separate scatterlist entries in the scatterlist array passed\n into the device_prep_slave_sg() call. The Keystone Packet DMA driver\n then ensures that these pieces of information are copied to/from the\n descriptor as needed.\n\n Note: The DMA engine writes to the scatterlist entries on completion.\n For example, on RX channels the actual packet/buffer size will be filled\n into the scatterlist entry. Therefore, the scatterlist array MUST NOT\n be placed on the stack.\n\n b. Prepare descriptor callbacks:\n\n The device_prep_slave_sg() call returns a DMA transfer descriptor. Note\n that this descriptor has nothing to do with the hardware descriptor\n specified in the Keystone Navigator architecture. The user driver is\n expected to fill up a callback and an optional callback parameter into\n the returned descriptor.\n\n c. Submit descriptor:\n\n Once the descriptor callbacks have been set, the user driver is expected\n to call dmaengine_submit() in order to hand the descriptor back to the\n DMA engine. The dmaengine_submit() call returns a transfer cookie that\n may be used at subsequent points to check the transfer status (via\n dma_async_is_tx_complete()). This cookie must also be checked for error\n values using the dma_submit_error() macro.\n\n2. Transfer request completion:\n\n When a pending DMA transfer has completed, the DMA engine driver will call\n the user provided callback with the user provided callback parameter. This\n callback may be in an atomic context, and therefore the callback must not\n block. While within the callback, the user driver may use the\n dma_async_is_tx_complete() function to determine if the transfer completed\n successfully (see dma_status codes). The callback may also optionally\n pause the channel (see dmaengine_pause()) to prevent further callbacks.\n Once the callback returns, the DMA driver frees up associated transfer\n resources.\n\n3. Channel pause and resume:\n\n User drivers may pause or resume the DMA channel at any point of time.\n Note that pause and resume have no impact on the actual hardware operation\n of the DMA, and in reality DMA transfers continue as normal. However, when\n a channel is paused, the DMA driver will not issue any further callbacks,\n and may choose to disable the underlying hardware interrupt or other\n notification mechanism as necessary.\n\n4. Channel close:\n\n As a part of the user driver\u0027s shutdown sequence, it must close all opened\n DMA channels in order to free resources. In the process of closing down\n the channel, the DMA driver will issue callbacks regardless of the\n pause/resume state. Further, some of these transfers may indicate a\n failure statue (DMA_ERROR) indicating that the transfer did not complete.\n\nOther Features :\n----------------\n\nLoopback mode:\n This mode supports Packet DMA loopback mode, as is the case with the\n infrastructure DMA built into the hardware queue subsystem.\n\nBig-Endian mode:\n When running in mixed-endian mode (i.e. ARM-LE, DSP-BE), the Keystone SoC\n peripherals (including DMAs) are big-endian. Consequently, descriptors need\n to be endian converted at read/write.\n\nEnable-All mode:\n The mapping between hardware channels and hardware receive flows are not\n consistent across DMA instances on the Keystone SoC. For example,\n infrastructure DMAs have a near one-to-one mapping between flows and RX\n channels, but the network coprocessor DMA does not. In order to support\n such variations, this driver has an enable-all mode that simply enables all\n TX and RX channels on the DMA at probe time, instead of incrementally\n enabling/disabling DMA resources at logical channel initialization.\n\nFlow Tag support:\n For infrastructure mode DMA usage, the transmit descriptors need to specify\n the receive flow number in the descriptor \"flow tag\". This is useful in the\n virtual ethernet use case, where ARM/Linux and DSP software open their\n respective receive flows, and transmit packets to each others\u0027 flows. In\n this scenario, the DSP flow number would be configured into the Linux\n dmaengine channel\u0027s flowtag.\n\nDebug support:\n When built with debug enabled (CONFIG_DMADEVICES_DEBUG), debug messages of\n individual channels and individual dmaengine instances are controllable via\n device tree. By default all debugs are turned off.\n\nRevisions:\n 0 - initial implementation\n 1 - add sysfs support for channel params\n 2 - fix up pktdma for dma_transfer_direction\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndma: keystone: streamline descriptor accesses\n\nThe compiler unfortunately generates horrid looking branch infested code\nfor the conditional endian conversions that we were doing on descriptor field\naccesses.\n\nFundamentally, the cpu_to_*32() functions expand to inline assembly \"rev\"\ninstructions opaque to the compiler. Therefore, conditional cpu_to_*32()\ncalls do not get optimized into conditionally executed \"rev\" instructions,\neven though the CPU technically supports this.\n\nOur work around here is to check once and fill all descriptor fields in one\nfell swoop. We similarly avoid endian checks/conversions inside loops when\ncopying data in/out of descriptors.\n\ndma: keystone: simplify descriptor state handling\n\nWhile debugging the initial packet dma driver implementation, we had added in\noverly paranoid code to handle descriptor state changes. This patch removes\nthese self-checks and cleans it up.\n\ndma: keystone: add optimization hints\n\nThis patch mainly adds branch optimization hints and prefetches to the packet\ndma driver\u0027s data path code. In addition, it also aligns key data structures\nto cacheline size, and reorders structure members to group together fields\nused often during packet I/O.\n\ndma: keystone: cleanup desc conversion helpers\n\nThis patch replaces helper macros for descriptor conversion (between hardware,\ndriver, and dma engine types) with equivalent inline functions. This also\nreplaces the index computation with shifts to speed up conversion back and\nforth from descriptor indices.\n\ndma: keystone: loosen accounting for used descriptors\n\nWith this patch, used descriptors are no longer maintained in a list.\nInstead, a simple atomic counter is maintained to track the number of\ndescriptors in-flight at any point of time.\n\ndma: keystone: abstract out descriptor alloc and free operations\n\nThis patch forks out descriptor allocation and free sequences into inlined\nfunctions.\n\ndma: keystone: add lock free descriptor accounting\n\nThis patch modifies the descriptor accounting code in the DMA implementation\nto use lock-free techniques instead. This way, we get by without having to\nprotect list maintenance operations with locks.\n\nThe lock-free list (actually more of a stack than a list) implementation is\nindex based, i.e., it maintains a singly linked list using 16-bit descriptor\nindices instead of pointers. In addition to the descriptor index, it\nmaintains a sequentially incremented token as some sort of a generation\ncounter. This generation counter is used to solve the ABA problem inherent\nwith cmpxchg based lock-free singly linked lists (see [1] for details).\n\n[1] http://en.wikipedia.org/wiki/ABA_problem\n\ndma: keystone: adjust sg length only on receive traffic\n\nThis patch modifies the completion side processing of the DMA driver, to\nadjust the length in the sglist entry only for receive side packets. This\nadjustment is useless on transmit side packets.\n\ndma: keystone: remove descriptor state tracking\n\nThe original implementation of the packet dma driver had paranoid atomic state\ntransitions on a per-descriptor basis. This was implemented at the time to\ncatch bugs in the implementation. Now that we are past that stage, we no\nlonger need such detailed state tracking, and so this patch cleans this up.\n\ndma: keystone: use calculated descriptor size at push\n\nWith this patch, we now compute the descriptor size based on presence of an\nExtended Packet Info Block (EPIB) and Protocol Specific data (psdata). This\nminimizes the amount of descriptor data that needs to be written back to\nmemory from cache.\n\ndma: keystone: add clock api\u0027s to the keystone packet dma engine\n\nthe packet processor clock was being called in the packet accelerator\ndriver. When the packet accelerator driver is built out of the kernel,\nwe still need to be able to enable the clock domains for ethernet to\nbe functional. This required adding clk api\u0027s to the engine.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\nImplement scatter/gather support for PktDMA\n\nPrior to this patch set, PktDMA supported only one buffer per submit.\nThis prevented transmission of chains of buffer descriptors. It also\nassumed there was exactly one receive free queue per channel, which\nprevented the reception of chains of buffers.\n\nAfter opening a channel, you MUST call dma_keystone_config() to set\nup the channel. Queue depths (and thus the number of descriptors\nallocated to the channel) are being moved from the FDT to this function\n(this transition is not yet complete). Use of dmaengine_slave_config()\nis entirely optional.\n\nNB: The dma_keystone_info structure contains an entry for the scatterlist\nsize. This MUST be set to the length of the scatterlists passed into and\nthe DMA engine. This is because the receive code has no other way to tell\nif the chain will fit the pre-allocated scatterlist. Also, the scatterlist\npassed to device_prep_slave_sg() when allocating for free queue 0 MUST be\npersistant -- NO stack variables!\n\nFor transmit channels, the scatterlist can now describe multiple buffers.\nAll buffers in the scatterlist must be mapped using dma_map_sg() or the\nlike. device_prep_slave_sg() will configure a buffer descriptor for each\nentry in the scatterlist, and the buffer descriptors will be chained\ntogether properly. The resulting dma_async_tx_descriptor describes the\nentire chain, and can be passed to dmaengine_submit() for transmission.\n\nFor receive channels, you no longer use dmaengine_submit() to provide free\nbuffers. In fact, dmaengine_submit() will now FAIL for receive channels.\nInstead, you provide the address of receive queue allocator and destructor\nfunctions in the dma_keystone_config() parameter block. The allocator is\ncalled from within the context of dma_poll() to replenish the free buffer\npool as necessary. This function must map the buffer using dma_map_sg()\nor dma_map_single() before calling device_prep_slave_sg(). The queue index\n(range [0..3]) is passed to the allocator along with the specified buffer\nsize to make the job of the allocator easier when multiple queues are\nsupported per channel. The destructor function is called only when a buffer\nalready on the free buffer list needs to be freed. It is NOT called for\nbuffers passed to the RX Complete function.\n\nPlease look at the code in drivers/net/ethernet/ti/keystone_net_core.c for\na working example.\n\ndma: keystone: Fix EBUSY error when bouncing a TX channel\n\nSetting an Ethernet interface to DOWN and then UP caused an EBUSY error\nto be returned. The problem is that the hwqueue was not being closed for\nTX channels because the rxpool_count was zero. This fix ignores rxpool_count\nand closes all open hwqueues during shutdown.\n\nSigned-off-by: Reece Pollack \u003cx0183204@ti.com\u003e\n\ndma: keystone: fix for descriptor corruption\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndma: keystone: enable driver to function without a defined clock\n\nThis commit allows instances of the packet dma like infra dma\nto operate without a defined clock\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndma: keystone: update the keystone dma engine\n\nIf the buffer descriptor chain contained more entries than the scatterlist,\nthe extra buffer descriptors and the buffers were lost. This patch frees\nthe buffer descriptors. In the case of an RX queue, the buffer destructor\nis called to free the buffer; for a TX queue the higher level code is\nassumed to know how to recover the buffers.\n\nAlso added some sanity checks. Warnings will be issued if the scatterlist\nis too short for the buffer chain, or if the number of bytes for the entire\npacket (reported in Word 0 of the packet descriptor) does not match the sum\nof the number of bytes reported for each of the buffer descriptors (word 3\nof each buffer descriptor).\n\nTesting shows the per-buffer byte count in descriptor word 3 is zeroed\nby the hardware on TX queues, so sanity-check this only on RX channels.\nAlso, don\u0027t reconstruct the scatterlist for TX channels.\n\nThe hwqueue_unmap() function may fail if a bogus packet is dequeued. This\ncan occur when a DSP has pushed a packet whose descriptor is not part of\nthe ARM descriptor pool to an ARM queue. This patch changes the handling\nof this case in chan_complete() so that processing of the queue continues\nrather than terminating.\n\nSigned-off-by: Reece Pollack \u003cx0183204@ti.com\u003e\n\ndma: keystone: expose dma_rxfree_refill() to upper layers\n\nPreviously, the internal chan_rxfree_refill() function was called at the\nend of chan_keystone_config() and chan_poll() to refill the RX free queues.\n\nThis patch exposes this function as dma_rxfree_refill(). Upper level drivers\nmust call this function at some point after dma_keystone_config() to initially\nfill the RX free queue, and again after dma_poll() to refill these queues.\n\nSigned-off-by: Reece Pollack \u003cx0183204@ti.com\u003e\n\ndma: keystone: add context argument to slave prep function\n\nThis patch adds a context argument to the prep_slave_sg function in line with\nmainline modifications towards the same end.\n\ndma: move keystone dma header to include/linux\n\nThis patch moves the keystone dma header file to include/linux to allow for\nsharing with keystone 2 devices.\n\ndma: keystone: update dma header location in packet dma driver\n\ndma:keystone: driver updates for common clock framework\n\nreplaced clk_enable()/clk_disable() with clk_prepare_enable() and\nclk_disable_unprepare() as per common clock API change.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n\ndma:keystone: allow use of entire psdata area\n\nThe check for psdata length rejected a length equal to the\nfull hw descriptor\u0027s psdata area. Change this to reject only\nlengths greater than the available area.\n\nSigned-off-by: Reece Pollack \u003cx0183204@ti.com\u003e\n\ndma:keystone: add dma_get_tx_queue() function\n\nSigned-off-by: Reece Pollack \u003cx0183204@ti.com\u003e\n\ndmaengine:keystone: enable submit queues to be shared\n\nReceive queues, submit queues and completion queues all had the\nO_EXCL flag associated with the. This resultd in none of the queues being\nshared. This commit enables submit queues to be shared. The \"O_EXCL\"\nflag in not associated with submit queues.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndmaengine:keystone: add port specific option flag\n\nif we want to send a descriptor to a specific slave port in the switch,\nthe the psflags section in the descriptor should have the\nappropritae information. We thus add an option flag called DMA_PORT\nwhich should be used with a prep_slav_sg on the transmit.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ndma: add kesytone device tree bindings documentation\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "81358096f88a367a49fc1ddcacc363c8910358fc", "tree": "d875cadc07b3474940127be6f6ab99e699d6dcfb", "parents": [ "51041e144ba8e8d78f7e6ac98449fe8e9ad52716" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Sep 18 16:00:28 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "hwqueue: keystone: add support for multiple queue managers\n\nOn the next generation of keystone devices, there will be multiple\ninstances of the queue manager. This commit adds support for\nmultiple queue managers in the keystone hardware queue driver.\nOn the current range of keystone devices we have only one queue\nmanager. Thus we will have only one queue manager node in the\ndevice tree bindings.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "51041e144ba8e8d78f7e6ac98449fe8e9ad52716", "tree": "ee9a1a6b836c01c4065d7b03cc60a09eb35cb832", "parents": [ "1d5aa3c983047468590a52246f1ef2dfae71499e" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Tue Jun 26 08:53:46 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "hwqueue: keystone: add accumulator support\n\nThe accumulator is a piece of PDSP firmware that pops descriptors from a queue\nand collects them in a memory based ping-pong buffer. In addition to this\nfunctionality, it provides a configurable interrupt pacing capability that can\nbe used in some instances to reduce the interrupt rate on high packet rate\nchannels.\n\nThis patch adds support for both single-queue and multi-queue variants of\naccumulator channels. Multi-queue channels are capable of monitoring up to 32\nqueues in a single channel. Both variants have been verified by rewiring the\nethernet receive queue through the accumulator.\n\nThis patch is nowhere near final, the following work items remain to be done:\n\n1. Performance problems - for some reason the ethernet throughput appears to\n be terrible when running on an accumulator channel. This is true for both\n single-queue and multi-queue cases, and needs further investigation.\n\n2. Device tree bindings - this patch extends the keystone hwqueue device tree\n bindings, but does not document the extensions as is the norm. This will\n need to be addressed in a future version of this patch.\n\n3. Hardware spinlock support - the accumulator channel programming process is\n not atomic. Therefore, when running in a multi-core system shared with\n DSPs, we need to acquire a hardware spinlock to protect the channel\n programming sequence. This capability does not exist in this patch, and\n will need to addressed in a future verison.\n\n4. List overruns - with this patch, accumulated queues maintain a page long\n list of descriptors in software. This list is maintained using atomic\n operations, and is fed from the ping-pong list in the interrupt handler.\n There is a possibility for this list to get overrun, and this case is not\n handled in the code.\n\n5. PDSP ID Handling - The device tree PDSP ID mapping between accumulator\n channels and PDSPs is obscene. This should be replaced with phandles or at\n least PDSP names instead of having a convoluted ID thingy.\n\n6. Termination and cleanup - This driver in general (not restricted to this\n patch) has lousy cleanup and termination handling. This needs to be\n revisited.\n\nCredits for the original patch go to Hao Zhang \u003chzhang@ti.com\u003e.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n\nhwqueue: fix flush on accumulator channels\n\nThis patch fixes the handling of queue flush on accumulator channels\n\nhwqueue: keystone: fix bug in the irq free routine\n\nThere was a small calculation mistake while calculating the ir number\nof a queue that needs to be freed.\nThis patch fixes the issues\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\nhwqueue: keystone: fix accumulator interrupt re-triggering\n\nThe accumulator interrupt re-triggering mechanism in place earlier was flawed.\nWriting a set bit to the status register internally bumps up the pending IRQ\ncount on the QMSS interrupt distributor. This means that we cannot rely on\nthe count \u003d\u003d 0 condition in the ISR to distinguish between normal list flips\nand re-triggered IRQs.\n\nThis patch adds explicit re-trigger accounting to circumvent this problem.\nThis is temporary at best.\n" }, { "commit": "1d5aa3c983047468590a52246f1ef2dfae71499e", "tree": "8ee55cfb9b80e8257d4f0cf7cb1cf0490c8d89e3", "parents": [ "7b97af7a27bcede4861fc6ddb91840e7fb407e04" ], "author": { "name": "Prabhu Kuttiyam", "email": "pkuttiyam@ti.com", "time": "Tue Jan 31 19:38:50 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "hwqueue: add hwqueue subsystem test cases\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\n\nhwqueue-test: Modified test code to treat the descriptor like a value.\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\n" }, { "commit": "7b97af7a27bcede4861fc6ddb91840e7fb407e04", "tree": "ff8398c3a7250f8533014af22626c0ef8e0a29b4", "parents": [ "4c96ea43f8d8c91c2f5bf6ddd6b934a6d4a62908" ], "author": { "name": "Prabhu Kuttiyam", "email": "pkuttiyam@ti.com", "time": "Mon Mar 12 18:54:23 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "hwqueue: add keystone hwqueue driver\n\nThis commit adds an hwqueue driver for the keystone qmss hardware. As of this\ncommit, accumulator functionality is non-existent.\n\nSigned-off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n\nhwqueue: keystone: avoid non-cacheable coherent allocs for descriptor regions\n\nThis patch replaces the original dma coherent allocation with a cacheable\nallocation that is then mapped for dma usage.\n\nhwqueue: keystone: add optimization hints\n\nIn addition to a few cosmetic fixes, this patch mainly adds branch\noptimization hints for the compiler\u0027s benefit. We also prefetch descriptors\non pop, and mournfully retry on finding an invalid descriptor on a hardware\nqueue.\n\nhwqueue: cleanup unused keystone specific structures\n\nThe hwqueue header had unnecessary remnant definitions from the\npre-device-tree era. These have been removed by this patch.\n\nhwqueue: align descriptor size to cache line size\n\nThis patch aligns descriptor size to the cache line size at push.\n\nhwqueue: keystone: verify descriptor size on push\n\nThis patch adds verification on descriptor size before pushing it to a\nhardware queue.\n\nhwqueue: keystone: scatter/gather support\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "4c96ea43f8d8c91c2f5bf6ddd6b934a6d4a62908", "tree": "c097cc2bd6391931d6f655ed8259cfefe2f0378d", "parents": [ "6721114d9f2ce161cb4e5b870f37a64b7b657772" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Sun Jan 08 15:46:41 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "hwqueue: add hwqueue core infrastructure\n\nThis patch adds an hwqueue core framework roughly along the lines of the\nhwspinlock architecture. This framework is hardware/platform independent and\nonly provides an API abstraction on top of a registration/unregistration\nmechanism for real hardware hwqueue implementations.\n\nThe abstraction elements in here are as follows:\n\n - \"device\" corresponds to a hardware queue manager. In the case of Appleton\n there is only one instance of a hwqueue device in the system. However,\n future devices may have more than one physical instance, for example,\n Keystone 2 devices have 2 instances of QMSS 1.5 devices.\n\n - \"instance\" corresponds to an actual hardware queue. Instances are numbered\n per-device as offsets from the device\u0027s base_id.\n\n- \"handle\" corresponds to a particular user of a hardware queue instance.\n Hardware queues may be opened by multiple entities in the kernel, and each\n entity may open the queue with a different read/write mode.\n\nSupported functionality:\n\n- Registration: The hwqueue core framework depends only on statically\n initialized state, and is therefore active very early in the kernel boot\n process. This allows other drivers to use hwqueue APIs without worrying\n about actual probe order. The registration/unregistration APIs allow\n underlying hardware implementations to add (and remove) themselves on the\n fly.\n\n- File semantics: The hwqueue core framework enforces traditional Unix\n open() mode semantics on top of hardware queues. These semantics include:\n * read/write modes: read-only, write-only, and read-write\n * creation mode: enforces that a queue not be already open\n * exclusive mode: enforces exclusive ownership on the queue\n\n- Notification: Read-capable users of an hwqueue may register one or more\n notifiers on the queue. These notifiers are called out independent of the\n underlying notification mechanism (accumulation, qpend interrupt, timer\n poll). The hwqueue core framework provides a timer based poll\n implementation for hwqueue hardware that does not support interrupt driven\n notification.\n\n- Debug visibility: The hwqueue core framework provides reasonably detailed\n debugfs visibility into the queues managed through this framework.\n\nThis framework is nowhere near complete, and is sure to be extended quite a\nbit more as we add real hardware drivers under this framework, and real API\nusers above it. It would, however, be useful to get some early feedback on\nthe overall model, assumptions, etc. before we go too far down this road.\n\nSigned-Off-by: Prabhu Kuttiyam \u003cpkuttiyam@ti.com\u003e\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n\nhwqueue: cleanups, improve debugfs dump\n\nhwqueue: avoid divide on queue push/pop\n\nThis patch speeds up hwqueue push and pop operations by eliminating a divide\noperation in the processing. Since the ARM CPU does not have a divide\ninstruction, this operation was spending measurable time in software divide\nroutines.\n\nThis divide was being done in mapping an hwqueue instance pointer to and from\na queue index. With this patch in place, we round up the size of the hwqueue\ninstance data to the nearest power of two, and use faster shift operations\ninstead.\n\nhwqueue: add branch optimization hints\n\nThis patch mainly adds branch optimization hints (likely/unlikely) for the\ncompiler\u0027s benefit. In addition, we now enforce the presence of push and pop\nhandlers at device registration time instead of checking on every push/pop.\nWe\u0027ve also removed a couple of impossible warning checks on helper routines\nthat convert back and forth between hwqueue handles and internal types.\n\nhwqueue: reorder fields to group frequently used data\n\nThis patch reorders the contents of the hwqueue_device data structure, to\ngroup together data that is frequently used in the data path.\n\nhwqueue: simplify data structures, inline data path ops\n\nThis patch simplifies the hwqueue core data structures, by eliminating the\nneed for a distinct hwqueue_handle structure. This further allows data path\noperations such as push and pop to be inlined in hwqueue.h.\n\nhwqueue: add scatter/gather support to hwqueue\n\nPrior to this patch, hwqueue_push() assumed the \"data\" parameter was\nthe address of a buffer that needed to be mapped before being pushed.\nLikewise, hwqueue_pop() assumed the value popped was the address of a\nbuffer that needed to be unmapped.\n\nThis patch set breaks out these operations into separate functions.\nIf the value to be pushed is the address of a buffer, it must be mapped\nusing hwqueue_map(), and the DMA address returned is then passed to\nhwqueue_push(). Similarly, if the value retrieved by hwqueue_pop() is\nthe address of a buffer, it must be unmapped using hwqueue_unmap()\nto get the virtual address of the buffer.\n\nThese changes BREAK the old semantics of hwqueue_push() and hwqueue_pop().\nExpect compile errors due to argument list changes. Do NOT just cast the\nold arguments to the new types; fix the errors properly.\n\nhwqueue fix\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\nhwqueue: clean up statistics to separate out error counters\n\nThis patch cleans up hwqueue statistics. Specifically, it separates out\nerror counters from the original push/pop counters.\n\nhwqueue: add device tree bindings documentation\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\nhwqueue: move hwqueue doc\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "6721114d9f2ce161cb4e5b870f37a64b7b657772", "tree": "1c5186d7bfb552ba91e7cb6d1242816a48ccbd60", "parents": [ "596d624a81b30f869ed93c499f1f9130865c8ba1" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Sep 06 12:24:56 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:11 2012 -0400" }, "message": "firmware:keystone: update the packet accelerator image names\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "596d624a81b30f869ed93c499f1f9130865c8ba1", "tree": "e60baf589675fead1961a4f78305c76ddeae2307", "parents": [ "0e4e9dcad0159cf5e84ea41d08150776c0bc74df" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Wed Aug 29 13:51:32 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:10 2012 -0400" }, "message": "firmware: keystone: update packet acccelerator firmware to version 1.3.0.1\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "0e4e9dcad0159cf5e84ea41d08150776c0bc74df", "tree": "c542bd50e5df89ed18e2829110ca7a999880d3da", "parents": [ "a0f383e5a6afa435b96d7534ef43f97d595e2415" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Aug 20 16:49:06 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:10 2012 -0400" }, "message": "firmware: keystone: update packet accelerator firmware to version 1.3.0.0\n\nThis commit updates the packet accelerator firmware to version\n1.3.0.0\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "a0f383e5a6afa435b96d7534ef43f97d595e2415", "tree": "00c8a42f5be4d2a8d2c28acc8191856747958cd1", "parents": [ "6f7a52a425fc8bc6bbb02d94c988b164dcd8f27c" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Jun 25 12:44:20 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:10 2012 -0400" }, "message": "firmware: update qmss firmware to version 1.0.3.12\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "6f7a52a425fc8bc6bbb02d94c988b164dcd8f27c", "tree": "4c42cf9c5f7a2151f26793b2fbb0fd0dda4b256d", "parents": [ "e416412fb763fc55e48dbf779117299e741763fd" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Thu Jun 07 10:29:24 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:10 2012 -0400" }, "message": "firmware: add support for keystone packet accelerator PDSPs\n\nThe keystone packet accelerator has 6 PDSPs.\npa_pdsp02_1_2_2_2.fw.ihex is downloaded to PDSP0, PDSP1 and PDSP2\npa_pdsp3_1_2_2_2.fw.ihex is downloaded to PDSP3\npa_pdsp45_1_2_2_2.fw.ihex is downloaded to PDSP4 and PDSP5\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "e416412fb763fc55e48dbf779117299e741763fd", "tree": "05c9c33b57396f75e61768ff541284875bdf230f", "parents": [ "ac94caa36c09d43e6748a81ba8ba9789574acc5d" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Mar 12 18:28:14 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:10 2012 -0400" }, "message": "firmware: add support for keystone QMSS\n\nThe keystone Queue Manager Subsystem needs firmware to be\ndownloaded to the PDSP for features such as accumulator\nsupport to function.\nWhile in big endian mode qmss_pdsp_acc48_be_1_0_2_0.fw.ihex needs to be\ndownloaded to the PDSP.\nWhile in little endian mode qmss_pdsp_acc48_le_1_0_2_0.fw.ihex needs to be\ndownloaded to the PDSP.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "ac94caa36c09d43e6748a81ba8ba9789574acc5d", "tree": "e40384aa562d4974a5da51ed941392af0da771de", "parents": [ "1c4ce4ac49f7d43c24b0d10fcb959efb510051ad" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Mar 12 18:26:09 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:09 2012 -0400" }, "message": "firmware: add support for keystone security accelerator PDSPs\n\nThe keystone security accelerator has 2 PDSPS.\nsa_pdsp0_1_0_2_1.fw.ihex is downloaded to PDSP0\nsa_pdsp1_1_0_2_1.fw.ihex is downloaded to PDSP1\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "1c4ce4ac49f7d43c24b0d10fcb959efb510051ad", "tree": "cf437baa9167e057a1e2e928fea0e7731700c5c3", "parents": [ "c9564b7821713c76dbb319489517f931db9abc80" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Sep 18 16:02:07 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:09 2012 -0400" }, "message": "tci6614: add device tree bindings for queue manager\n\nOn keystone 1 devices we should have only 1 queue manager node.\nNumber of queue manager nodes can be more than 1 in keystone 2 devices.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "c9564b7821713c76dbb319489517f931db9abc80", "tree": "7be68c1dba00ed6955c450062a4620fb2daacc86", "parents": [ "c6569d50531e5dc6bd1a2fbb721a63eae6b76f1c" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Mon Sep 17 14:08:45 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:09 2012 -0400" }, "message": "tci6614: add support for more than 4096 hardware queues\n\nThis commit updates the device tree bindings to enable queues with\nqueue numbers more than 4095 to be used.\n\nThe general purpose queues have been defined to start at queue 8000.\nThis was for testing only. We can revert back to 4000 if other teams\ndon\u0027t want to make a change. Other changes are independent.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "c6569d50531e5dc6bd1a2fbb721a63eae6b76f1c", "tree": "1accdceb5be20f98aef1b935b97fe63cb1e48994", "parents": [ "47660b6d5891895605610a6ea90445c1e34c02cd" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 16:04:19 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:09 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for rapid io\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "47660b6d5891895605610a6ea90445c1e34c02cd", "tree": "78e589ac5b1928b740571ec1e7dd8e3ab9c01a9e", "parents": [ "a06f4e6fc5c7ea7b55fa3e9b3ecbd9298dfef6c2" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 16:03:25 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:09 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for remote proc\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "a06f4e6fc5c7ea7b55fa3e9b3ecbd9298dfef6c2", "tree": "03e80fe35b6aa3fcfd884c00abeb42db38b31005", "parents": [ "330c5039367d0312aae764ceae55598167202a9a" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 16:02:16 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:08 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the ipc irq\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "330c5039367d0312aae764ceae55598167202a9a", "tree": "5caa442e9353c31262c5204ce44457abab9a1df0", "parents": [ "002bd37537a47a321af120e454202e7c0ca2316b" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 16:01:28 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:08 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for crypto engine\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "002bd37537a47a321af120e454202e7c0ca2316b", "tree": "525167be25acd221e2c38a896e13f376b53e0dbe", "parents": [ "18e4f7f8af2931d08aa27e2077b74131f3d188c2" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 16:00:28 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:08 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the network co-processor\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "18e4f7f8af2931d08aa27e2077b74131f3d188c2", "tree": "ec84fd4d3e8dcf526a0ab175c68a284bf54f6787", "parents": [ "540743c9b71cd9a3698546eae427d770dee710b3" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:59:18 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:08 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the udma\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "540743c9b71cd9a3698546eae427d770dee710b3", "tree": "4813528758d69f1b6ba21e1dde8bd62ac04698c8", "parents": [ "17a184fd1d61ab95c634996469ac5b7a30e6b435" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:58:37 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:07 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the davinci mdio\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "17a184fd1d61ab95c634996469ac5b7a30e6b435", "tree": "c5b9766f3eeaf0343483d0ca16242895333ea23d", "parents": [ "a14224d77259a3cbd7fb66f4802449989270fb22" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:57:47 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:07 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for srio packet dma\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "a14224d77259a3cbd7fb66f4802449989270fb22", "tree": "c93e4219d851c3b5841affea9cff7f7d2b3bc3b0", "parents": [ "0e919d381962393046746061bb3a07fac3e62f73" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:56:49 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:07 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the pa packet dma\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "0e919d381962393046746061bb3a07fac3e62f73", "tree": "a99e4cb5a769c491126335bc8fc2b11b3c47eaee", "parents": [ "c9742d0d666fc98d97b562418ce633ac45e4d011" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:55:53 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:07 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for the infrastructure packet dma\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "c9742d0d666fc98d97b562418ce633ac45e4d011", "tree": "b119afd670b1a3992615b93b68d130e532784b08", "parents": [ "e0a211834d5225df8d27a42eb60b71be1bde6a42" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:54:04 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:07 2012 -0400" }, "message": "tci6614: dt: add device tree bindings for hardware queues\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "e0a211834d5225df8d27a42eb60b71be1bde6a42", "tree": "c43182e891c2b27cbf06aa4055b144596aa55648", "parents": [ "c5822784be106d2ab0da029c47286ba0b2c316b4" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 15:52:11 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:06 2012 -0400" }, "message": "tci6614: dt: add minimum device tree bindings for evm\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "c5822784be106d2ab0da029c47286ba0b2c316b4", "tree": "098d73fe7558b574f10cce71a4952b02fbf8cccc", "parents": [ "ccc5704c097e01ed13a251393585661b6fdad486" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Tue Jun 26 09:34:16 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:06 2012 -0400" }, "message": "tci6614: add cpintc irq debug helper macros\n\nThis patch adds a simple debug mechanism that allows one or more specific\ncpintc interrupts to be traced.\n\nSigned-off-by: Cyril Chemparathy \u003ccyril@ti.com\u003e\n" }, { "commit": "ccc5704c097e01ed13a251393585661b6fdad486", "tree": "558d049d7b04824833d89005c0e401ec33bf0ed6", "parents": [ "e43749d90ac691dcc0c8eca02e31da10f77bfed0" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue May 01 13:47:29 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:06 2012 -0400" }, "message": "tci6614: Updating the cpgmac and mdio clock definition\n\nAlthough the tci6614 spec clearly demarcates power domain 7 and 8; based\non experiments, there defintely is a dependency between the two domains.\nPower domain 8 has to be enabled only after domain 7.\nTo this effect, the parent of the the cpgmac\nand mdio clocks are being appropriately changed.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ntci6614: add clock for mdio\n\nAs of now it is not possible to use clk_add_alias because the API\nrequires a \"device\" to be passed in as an argument.\nSince this device is being defined in the clock lookups, there\nis currently no way to get this information.\n\nThis commit essentially achieves something we would have achieved using\nthe clock_add_alias\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n\ntci6614: adding additional ethernet related clocks\n\nThis patch adds additional clocks for ethernet related clocks\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "e43749d90ac691dcc0c8eca02e31da10f77bfed0", "tree": "0445f8cf87f3ef1a151c0a354d37c8c491d166bc", "parents": [ "54ef16d755e66621b79f605bc7661eee69fdf97b" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Tue Apr 17 17:02:50 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:06 2012 -0400" }, "message": "tci6614: fix the max values of aemif timings\n\nThe max values currently set in board file is in aemif clock cycles\nbut it should be in nano seconds. Also change the type of wstrobe\nand rstrobe to u16\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "54ef16d755e66621b79f605bc7661eee69fdf97b", "tree": "4d06dbe9bb3f45d34cf2175d63f7781cbb365781", "parents": [ "2a32313d553a7ab713779771a441cebfd75acca9" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Tue Mar 13 17:51:07 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:06 2012 -0400" }, "message": "tci6614: updated reset hookups for v3.3 mainline merge\n" }, { "commit": "2a32313d553a7ab713779771a441cebfd75acca9", "tree": "0b59d3f718440ed7c3c422e2813bdc53077478a5", "parents": [ "f533949d108db8bd43e62e2dc06713964b5aacd6" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Fri Mar 02 14:58:07 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: fix reboot command\n\nFor the reboot command to work, the watchdog output has to trigger a\ndevice reset. In TCI6614 SoC, this requires setting the RSTMUX8 register to\ngenerate a device reset using the WD output.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "f533949d108db8bd43e62e2dc06713964b5aacd6", "tree": "1e3f6d73cb7b7f2ae4360457ea4e15ea28000fb2", "parents": [ "d4c8cfa1e61fc7e1568e1ae255e2dd75f10e74ba" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Feb 16 16:45:38 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: add pmu device definition for oprofile\n" }, { "commit": "d4c8cfa1e61fc7e1568e1ae255e2dd75f10e74ba", "tree": "2c0d7030ecc375d69d9fc4c27ac5d7e47f0ee2ad", "parents": [ "4ad6548ace99861b7a577f4bf4ae0d1198ff9971" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Fri Feb 10 18:09:37 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: redefine partitions for UBIFS\n\nThis patch replaces the kernel and rootfs partition in NAND with just\none ubifs partition. This partition will contains following UBI volumes:-\n\nrootfs - filesystem in this volume is used by the Linux kernel for normal\nboot\n\nrootfs-recovery - filesystem in this volume is used when the filesystem in\nthe rootfs volume is corrupt and not usable for Linux bootup\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "4ad6548ace99861b7a577f4bf4ae0d1198ff9971", "tree": "21f4b185848875cd4bd36c82db1fabb1ad16cfce", "parents": [ "09528dba718f417b732bf026824f0601f6cf8b99" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Fri Sep 14 14:34:28 2012 -0400" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: dt: add device tree support for evm\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "09528dba718f417b732bf026824f0601f6cf8b99", "tree": "bc473246cc181747e8a3ee87e06075756cd478fe", "parents": [ "cbf7672f21f6828694ae75177ab563ff2ef6bd25" ], "author": { "name": "Sandeep Paulraj", "email": "s-paulraj@ti.com", "time": "Tue Jan 17 12:23:00 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: add clocks to be used by the network driver.\n\nThe network driver for Keystone devices was not calling clk_get APIs.\nThis patch adds clocks that can be used by the network driver.\n\nSigned-off-by: Sandeep Paulraj \u003cs-paulraj@ti.com\u003e\n" }, { "commit": "cbf7672f21f6828694ae75177ab563ff2ef6bd25", "tree": "ec5ece5b1f23cf37d64d7e5c057b5c9178b7017c", "parents": [ "5e3977384086281f967b977ff395a338b8682cbc" ], "author": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Thu Jan 19 18:32:30 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:05 2012 -0400" }, "message": "tci6614: add hardware semaphore device\n\nThis patch adds device definitions for the hardware semaphore.\n" }, { "commit": "5e3977384086281f967b977ff395a338b8682cbc", "tree": "98b284cd4d5115bed81c7d80e3d69f663fa8eaba", "parents": [ "72302f0eec2e52982bb014c5d05f1c22da379eee" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Fri Jan 06 14:35:46 2012 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:04 2012 -0400" }, "message": "tci6614: update pd/lpsc based on spec update\n\nAs per verion v0.8 the psc/lpsc spec there are many PD and LPSC\ndefinitions changed. This patch udpates the same in the Linux\npsc code\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "72302f0eec2e52982bb014c5d05f1c22da379eee", "tree": "17b8f953392d33b2693129bd1bd26c08ae5cb804", "parents": [ "1e72e88d4fec2824f8d19f21ccb4defbc3fcca8c" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Dec 19 17:52:45 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:04 2012 -0400" }, "message": "tci6614: fix the NOR flash write issue\n\nModified SPI NOR flash partitions as follows:-\n\n u-boot-sbl - 512K (readonly)\n test - 3.5M (read/write) for test purpose.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "1e72e88d4fec2824f8d19f21ccb4defbc3fcca8c", "tree": "3baaceef4deff232942fcc10dd82cd3ad95e6609", "parents": [ "258d0286a9932c9d12e48cc3ac1045877a29d6eb" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Wed Nov 30 09:28:14 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:04 2012 -0400" }, "message": "tci6614: add serial port stub for evm\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "258d0286a9932c9d12e48cc3ac1045877a29d6eb", "tree": "9112126b04d8d4d5da36e0b9b9c3ff2621a90946", "parents": [ "d55f2384e9b3acae14f135d62d21d38124e142f6" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Wed Nov 30 09:27:05 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:04 2012 -0400" }, "message": "tci6614: add serial port stub for simulator\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "d55f2384e9b3acae14f135d62d21d38124e142f6", "tree": "ba67004d673a6ccf811fd3b87aef092adb684f79", "parents": [ "42ddf5a69765ae8862ee06d5152f9f92ba3ba0e9" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Nov 21 16:25:21 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:04 2012 -0400" }, "message": "tci6614: work around simulator timer issue\n\nThis is a work around for a simulator timer issue\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "42ddf5a69765ae8862ee06d5152f9f92ba3ba0e9", "tree": "c181c6f59645092b3ce4ca7951a4629eaccdd305", "parents": [ "6da4e364f06aa9043ae7a535e28379f6d62b8b52" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Nov 28 11:51:53 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:03 2012 -0400" }, "message": "tci6614: add support for evaluation module\n\nThis is the board setup file for TCI6614 EVM\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "6da4e364f06aa9043ae7a535e28379f6d62b8b52", "tree": "9e78bb6d586947056713f80cb4a97da068fc20d3", "parents": [ "5b2a9fa5aab1fa0fc825e92e69bb91fc5cf80f67" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Nov 21 17:17:09 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:03 2012 -0400" }, "message": "tci6614: add support for simulator board\n\nThis is the board specific file for TCI6614 Simulator. This code\ninitializes minimum set of devices for the simulator.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "5b2a9fa5aab1fa0fc825e92e69bb91fc5cf80f67", "tree": "9da579a24cd2d768b26c1cf17750735de08a7d1f", "parents": [ "cd30dc9d55ffd153f991ba7eb15fd00e456ae7aa" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Sat Nov 26 10:34:11 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:03 2012 -0400" }, "message": "tci6614: add on-chip device definitions\n\nThis is the device initialization code for TCI6614. The board specific\ncode initializes the tci6614_device_info structure for various devices\navailable on the board and calls tci6614_devices_init() to initialize\nthe devices.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "cd30dc9d55ffd153f991ba7eb15fd00e456ae7aa", "tree": "e2ee82cae3c5e6015f690245e85321c972f4067f", "parents": [ "a8d786db1d0a3061e92cceca07b7890eb69fa7ba" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Mon Nov 28 11:17:38 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:03 2012 -0400" }, "message": "tci6614: add soc specific initialization code\n\nThis patch adds SoC specific code for TCI6614.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "a8d786db1d0a3061e92cceca07b7890eb69fa7ba", "tree": "2e5ebc87e93997a255fe5b51c70b8690c1b5af6c", "parents": [ "1519a663308ee2d9c9bbac2302e8c25cc3b88554" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Sat Nov 26 10:28:41 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:02 2012 -0400" }, "message": "tci6614: add driver for omap arm interrupt controller\n\nTCI6614 re-uses the OMAP AINTC for interfacing CP_INTC and other\ninterrupt lines to ARM. This adds the OMAP AINTC driver for the SOC.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" }, { "commit": "1519a663308ee2d9c9bbac2302e8c25cc3b88554", "tree": "583c8837b99dde1ca976e16f9d91ce7328604a60", "parents": [ "f5e26552d252098413df965a289c9150d95727c8" ], "author": { "name": "Murali Karicheri", "email": "m-karicheri2@ti.com", "time": "Sat Nov 26 10:27:32 2011 -0500" }, "committer": { "name": "Cyril Chemparathy", "email": "cyril@ti.com", "time": "Fri Sep 21 10:44:02 2012 -0400" }, "message": "tci6614: add driver for cpintd pulse-level convertor\n\nTCI6614 SOC has CP_INTD (a.k.a Common Platform Interrupt Distributor for\nmapping some of the System interrupts to CP_INTC. This is the driver\nfor CP_INTD. This also extend the davinci_soc_info structure so that\nindividual SOC can define if there is support for CP_INTD or not. This code\nis designed similar to the CP_INTC driver.\n\nSigned-off-by: Murali Karicheri \u003cm-karicheri2@ti.com\u003e\n" } ], "next": "f5e26552d252098413df965a289c9150d95727c8" }