| commit | 00ae4e76f14a732aefe6343b76be60dd20b70d45 | [log] [tgz] |
|---|---|---|
| author | Christoffer Dall <christoffer.dall@linaro.org> | Fri Dec 09 14:22:49 2016 +0100 |
| committer | Christoffer Dall <christoffer.dall@linaro.org> | Sat Dec 10 21:41:42 2016 +0100 |
| tree | 8e3cf475f388416cb7baf179146c58c4c100aff4 | |
| parent | a7ac32420be1584076a3305475ed3e2c3fa04236 [diff] |
ARM: dts: vexpress: Support GICC_DIR operations The GICv2 CPU interface registers span across 8K, not 4K as indicated in the DT. Only the GICC_DIR register is located after the initial 4K boundary, leaving a functional system but without support for separately EOI'ing and deactivating interrupts. After this change the system support split priority drop and interrupt deactivation. Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>