Initial JH7110 clk/reset support
A rake of patches, initially worked on by Emil & later picked up by Hal
that add support for the sys/aon clock & reset controllers on StarFive's
JH7110 SoC.
This SoC is largely similar to the existing JH7100, so a bunch of
refactoring is done to share as many bits as possible between the two.
What's here (plus the already applied pinctrl bits) should be sufficient
to boot a basic initramfs.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
MAINTAINERS: generalise StarFive clk/reset entries
Update the MAINTAINERS entry for StarFive's clock and reset drivers to
account for the addition of JH7110 support and Hal's role in that.
Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
[conor: split this out from the binding patch, since it touches more
than the binding; resort the entries per Hal's request]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
1 file changed
