| /dts-v1/; |
| |
| #include "skeleton.dtsi" |
| #include <dt-bindings/clock/qcom,gcc-msm8960.h> |
| #include <dt-bindings/reset/qcom,gcc-msm8960.h> |
| #include <dt-bindings/clock/qcom,mmcc-msm8960.h> |
| #include <dt-bindings/soc/qcom,gsbi.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| |
| / { |
| model = "Qualcomm APQ8064"; |
| compatible = "qcom,apq8064"; |
| interrupt-parent = <&intc>; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc0>; |
| qcom,saw = <&saw0>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| cpu@1 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <1>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc1>; |
| qcom,saw = <&saw1>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| cpu@2 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <2>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc2>; |
| qcom,saw = <&saw2>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| cpu@3 { |
| compatible = "qcom,krait"; |
| enable-method = "qcom,kpss-acc-v1"; |
| device_type = "cpu"; |
| reg = <3>; |
| next-level-cache = <&L2>; |
| qcom,acc = <&acc3>; |
| qcom,saw = <&saw3>; |
| cpu-idle-states = <&CPU_SPC>; |
| }; |
| |
| L2: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| }; |
| |
| idle-states { |
| CPU_SPC: spc { |
| compatible = "qcom,idle-state-spc", |
| "arm,idle-state"; |
| entry-latency-us = <400>; |
| exit-latency-us = <900>; |
| min-residency-us = <3000>; |
| }; |
| }; |
| }; |
| |
| cpu-pmu { |
| compatible = "qcom,krait-pmu"; |
| interrupts = <1 10 0x304>; |
| }; |
| |
| soc: soc { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| compatible = "simple-bus"; |
| |
| tlmm_pinmux: pinctrl@800000 { |
| compatible = "qcom,apq8064-pinctrl"; |
| reg = <0x800000 0x4000>; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&ps_hold>; |
| |
| sdc4_gpios: sdc4-gpios { |
| pios { |
| pins = "gpio63", "gpio64", "gpio65", "gpio66", "gpio67", "gpio68"; |
| function = "sdc4"; |
| }; |
| }; |
| |
| ps_hold: ps_hold { |
| mux { |
| pins = "gpio78"; |
| function = "ps_hold"; |
| }; |
| }; |
| |
| i2c1_pins: i2c1 { |
| mux { |
| pins = "gpio20", "gpio21"; |
| function = "gsbi1"; |
| }; |
| }; |
| |
| i2c3_pins: i2c3 { |
| mux { |
| pins = "gpio8", "gpio9"; |
| function = "gsbi3"; |
| }; |
| }; |
| }; |
| |
| intc: interrupt-controller@2000000 { |
| compatible = "qcom,msm-qgic2"; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| reg = <0x02000000 0x1000>, |
| <0x02002000 0x1000>; |
| }; |
| |
| timer@200a000 { |
| compatible = "qcom,kpss-timer", "qcom,msm-timer"; |
| interrupts = <1 1 0x301>, |
| <1 2 0x301>, |
| <1 3 0x301>; |
| reg = <0x0200a000 0x100>; |
| clock-frequency = <27000000>, |
| <32768>; |
| cpu-offset = <0x80000>; |
| }; |
| |
| acc0: clock-controller@2088000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x02088000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| acc1: clock-controller@2098000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x02098000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| acc2: clock-controller@20a8000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x020a8000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| acc3: clock-controller@20b8000 { |
| compatible = "qcom,kpss-acc-v1"; |
| reg = <0x020b8000 0x1000>, <0x02008000 0x1000>; |
| }; |
| |
| saw0: power-controller@2089000 { |
| compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; |
| reg = <0x02089000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| saw1: power-controller@2099000 { |
| compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; |
| reg = <0x02099000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| saw2: power-controller@20a9000 { |
| compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; |
| reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| saw3: power-controller@20b9000 { |
| compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; |
| reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; |
| regulator; |
| }; |
| |
| gsbi1: gsbi@12440000 { |
| status = "disabled"; |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <1>; |
| reg = <0x12440000 0x100>; |
| clocks = <&gcc GSBI1_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| syscon-tcsr = <&tcsr>; |
| |
| i2c1: i2c@12460000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x12460000 0x1000>; |
| interrupts = <0 194 IRQ_TYPE_NONE>; |
| clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; |
| clock-names = "core", "iface"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| gsbi2: gsbi@12480000 { |
| status = "disabled"; |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <2>; |
| reg = <0x12480000 0x100>; |
| clocks = <&gcc GSBI2_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| syscon-tcsr = <&tcsr>; |
| |
| i2c2: i2c@124a0000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x124a0000 0x1000>; |
| interrupts = <0 196 IRQ_TYPE_NONE>; |
| clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>; |
| clock-names = "core", "iface"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| gsbi3: gsbi@16200000 { |
| status = "disabled"; |
| compatible = "qcom,gsbi-v1.0.0"; |
| reg = <0x16200000 0x100>; |
| clocks = <&gcc GSBI3_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| i2c3: i2c@16280000 { |
| compatible = "qcom,i2c-qup-v1.1.1"; |
| reg = <0x16280000 0x1000>; |
| interrupts = <GIC_SPI 151 IRQ_TYPE_NONE>; |
| clocks = <&gcc GSBI3_QUP_CLK>, |
| <&gcc GSBI3_H_CLK>; |
| clock-names = "core", "iface"; |
| }; |
| }; |
| |
| gsbi7: gsbi@16600000 { |
| status = "disabled"; |
| compatible = "qcom,gsbi-v1.0.0"; |
| cell-index = <7>; |
| reg = <0x16600000 0x100>; |
| clocks = <&gcc GSBI7_H_CLK>; |
| clock-names = "iface"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| syscon-tcsr = <&tcsr>; |
| |
| gsbi7_serial: serial@16640000 { |
| compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; |
| reg = <0x16640000 0x1000>, |
| <0x16600000 0x1000>; |
| interrupts = <0 158 0x0>; |
| clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>; |
| clock-names = "core", "iface"; |
| status = "disabled"; |
| }; |
| }; |
| |
| qcom,ssbi@500000 { |
| compatible = "qcom,ssbi"; |
| reg = <0x00500000 0x1000>; |
| qcom,controller-type = "pmic-arbiter"; |
| }; |
| |
| gcc: clock-controller@900000 { |
| compatible = "qcom,gcc-apq8064"; |
| reg = <0x00900000 0x4000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| lcc: clock-controller@28000000 { |
| compatible = "qcom,lcc-apq8064"; |
| reg = <0x28000000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| mmcc: clock-controller@4000000 { |
| compatible = "qcom,mmcc-apq8064"; |
| reg = <0x4000000 0x1000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| }; |
| |
| l2cc: clock-controller@2011000 { |
| compatible = "syscon"; |
| reg = <0x2011000 0x1000>; |
| }; |
| |
| rpm@108000 { |
| compatible = "qcom,rpm-apq8064"; |
| reg = <0x108000 0x1000>; |
| qcom,ipc = <&l2cc 0x8 2>; |
| |
| interrupts = <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, |
| <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "ack", "err", "wakeup"; |
| |
| regulators { |
| compatible = "qcom,rpm-pm8921-regulators"; |
| |
| pm8921_hdmi_switch: hdmi-switch { |
| bias-pull-down; |
| }; |
| }; |
| }; |
| |
| usb1_phy: phy@12500000 { |
| compatible = "qcom,usb-otg-ci"; |
| reg = <0x12500000 0x400>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| dr_mode = "host"; |
| |
| clocks = <&gcc USB_HS1_XCVR_CLK>, |
| <&gcc USB_HS1_H_CLK>; |
| clock-names = "core", "iface"; |
| |
| resets = <&gcc USB_HS1_RESET>; |
| reset-names = "link"; |
| }; |
| |
| usb3_phy: phy@12520000 { |
| compatible = "qcom,usb-otg-ci"; |
| reg = <0x12520000 0x400>; |
| interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| dr_mode = "host"; |
| |
| clocks = <&gcc USB_HS3_XCVR_CLK>, |
| <&gcc USB_HS3_H_CLK>; |
| clock-names = "core", "iface"; |
| |
| resets = <&gcc USB_HS3_RESET>; |
| reset-names = "link"; |
| }; |
| |
| usb4_phy: phy@12530000 { |
| compatible = "qcom,usb-otg-ci"; |
| reg = <0x12530000 0x400>; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| dr_mode = "host"; |
| |
| clocks = <&gcc USB_HS4_XCVR_CLK>, |
| <&gcc USB_HS4_H_CLK>; |
| clock-names = "core", "iface"; |
| |
| resets = <&gcc USB_HS4_RESET>; |
| reset-names = "link"; |
| }; |
| |
| gadget1: gadget@12500000 { |
| compatible = "qcom,ci-hdrc"; |
| reg = <0x12500000 0x400>; |
| status = "disabled"; |
| dr_mode = "peripheral"; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; |
| usb-phy = <&usb1_phy>; |
| }; |
| |
| usb1: usb@12500000 { |
| compatible = "qcom,ehci-host"; |
| reg = <0x12500000 0x400>; |
| interrupts = <GIC_SPI 100 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| usb-phy = <&usb1_phy>; |
| }; |
| |
| usb3: usb@12520000 { |
| compatible = "qcom,ehci-host"; |
| reg = <0x12520000 0x400>; |
| interrupts = <GIC_SPI 188 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| usb-phy = <&usb3_phy>; |
| }; |
| |
| usb4: usb@12530000 { |
| compatible = "qcom,ehci-host"; |
| reg = <0x12530000 0x400>; |
| interrupts = <GIC_SPI 215 IRQ_TYPE_NONE>; |
| status = "disabled"; |
| usb-phy = <&usb4_phy>; |
| }; |
| |
| sata_phy0: phy@1b400000 { |
| compatible = "qcom,apq8064-sata-phy"; |
| status = "disabled"; |
| reg = <0x1b400000 0x200>; |
| reg-names = "phy_mem"; |
| clocks = <&gcc SATA_PHY_CFG_CLK>; |
| clock-names = "cfg"; |
| #phy-cells = <0>; |
| }; |
| |
| sata0: sata@29000000 { |
| compatible = "generic-ahci"; |
| status = "disabled"; |
| reg = <0x29000000 0x180>; |
| interrupts = <GIC_SPI 209 IRQ_TYPE_NONE>; |
| |
| clocks = <&gcc SFAB_SATA_S_H_CLK>, |
| <&gcc SATA_H_CLK>, |
| <&gcc SATA_A_CLK>, |
| <&gcc SATA_RXOOB_CLK>, |
| <&gcc SATA_PMALIVE_CLK>; |
| clock-names = "slave_iface", |
| "iface", |
| "bus", |
| "rxoob", |
| "core_pmalive"; |
| |
| assigned-clocks = <&gcc SATA_RXOOB_CLK>, |
| <&gcc SATA_PMALIVE_CLK>; |
| assigned-clock-rates = <100000000>, <100000000>; |
| |
| phys = <&sata_phy0>; |
| phy-names = "sata-phy"; |
| }; |
| |
| /* Temporary fixed regulator */ |
| vsdcc_fixed: vsdcc-regulator { |
| compatible = "regulator-fixed"; |
| regulator-name = "SDCC Power"; |
| regulator-min-microvolt = <2700000>; |
| regulator-max-microvolt = <2700000>; |
| regulator-always-on; |
| }; |
| |
| sdcc1bam:dma@12402000{ |
| compatible = "qcom,bam-v1.3.0"; |
| reg = <0x12402000 0x8000>; |
| interrupts = <0 98 0>; |
| clocks = <&gcc SDC1_H_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| sdcc3bam:dma@12182000{ |
| compatible = "qcom,bam-v1.3.0"; |
| reg = <0x12182000 0x8000>; |
| interrupts = <0 96 0>; |
| clocks = <&gcc SDC3_H_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| sdcc4bam:dma@121c2000{ |
| compatible = "qcom,bam-v1.3.0"; |
| reg = <0x121c2000 0x8000>; |
| interrupts = <0 95 0>; |
| clocks = <&gcc SDC4_H_CLK>; |
| clock-names = "bam_clk"; |
| #dma-cells = <1>; |
| qcom,ee = <0>; |
| }; |
| |
| amba { |
| compatible = "arm,amba-bus"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| sdcc1: sdcc@12400000 { |
| status = "disabled"; |
| compatible = "arm,pl18x", "arm,primecell"; |
| arm,primecell-periphid = <0x00051180>; |
| reg = <0x12400000 0x2000>; |
| interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "cmd_irq"; |
| clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>; |
| clock-names = "mclk", "apb_pclk"; |
| bus-width = <8>; |
| max-frequency = <96000000>; |
| non-removable; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| vmmc-supply = <&vsdcc_fixed>; |
| dmas = <&sdcc1bam 2>, <&sdcc1bam 1>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| sdcc3: sdcc@12180000 { |
| compatible = "arm,pl18x", "arm,primecell"; |
| arm,primecell-periphid = <0x00051180>; |
| status = "disabled"; |
| reg = <0x12180000 0x2000>; |
| interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "cmd_irq"; |
| clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>; |
| clock-names = "mclk", "apb_pclk"; |
| bus-width = <4>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| max-frequency = <192000000>; |
| no-1-8-v; |
| vmmc-supply = <&vsdcc_fixed>; |
| dmas = <&sdcc3bam 2>, <&sdcc3bam 1>; |
| dma-names = "tx", "rx"; |
| }; |
| |
| sdcc4: sdcc@121c0000 { |
| compatible = "arm,pl18x", "arm,primecell"; |
| arm,primecell-periphid = <0x00051180>; |
| status = "disabled"; |
| reg = <0x121c0000 0x2000>; |
| interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "cmd_irq"; |
| clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>; |
| clock-names = "mclk", "apb_pclk"; |
| bus-width = <4>; |
| cap-sd-highspeed; |
| cap-mmc-highspeed; |
| max-frequency = <48000000>; |
| vmmc-supply = <&vsdcc_fixed>; |
| vqmmc-supply = <&vsdcc_fixed>; |
| dmas = <&sdcc4bam 2>, <&sdcc4bam 1>; |
| dma-names = "tx", "rx"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&sdc4_gpios>; |
| }; |
| }; |
| |
| tcsr: syscon@1a400000 { |
| compatible = "qcom,tcsr-apq8064", "syscon"; |
| reg = <0x1a400000 0x100>; |
| }; |
| }; |
| }; |
