| commit | 5e5a195ecc8cc0280d169d6da33c959df6336e9f | [log] [tgz] |
|---|---|---|
| author | Ben Skeggs <bskeggs@redhat.com> | Mon Oct 22 14:10:16 2012 +1000 |
| committer | Ben Skeggs <bskeggs@redhat.com> | Mon Oct 22 14:38:06 2012 +1000 |
| tree | 40622c64d1335ebfcebf379d7f44a5a0ef40f56e | |
| parent | 2c25b7399570ebdcf737c5af67c9d26a1771c002 [diff] |
drm/nouveau/clock: fix missing pll type/addr when matching default entry This issue is a regression from 70790f4f819875e8f390871fd15bbbf823f28e1b, and causes us to miss a special-case for C51 (NV4E) chipsets and return the wrong reference frequency for the VPLLs. Should fix fdo#56202 Signed-off-by: Ben Skeggs <bskeggs@redhat.com>