blob: e0685e630afec795db1e5f1d3221919cd2766ba8 [file] [log] [blame]
/*
* Copyright (c) 2016-2017 Hisilicon Limited.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/
#include <linux/acpi.h>
#include <linux/device.h>
#include <linux/etherdevice.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/netdevice.h>
#include <linux/pci.h>
#include <linux/platform_device.h>
#include "hclge_cmd.h"
#include "hclge_main.h"
#include "hclge_mdio.h"
#include "hclge_tm.h"
#include "hnae3.h"
#define HCLGE_NAME "hclge"
#define HCLGE_STATS_READ(p, offset) (*((u64 *)((u8 *)(p) + (offset))))
#define HCLGE_MAC_STATS_FIELD_OFF(f) (offsetof(struct hclge_mac_stats, f))
#define HCLGE_64BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_64_bit_stats, f))
#define HCLGE_32BIT_STATS_FIELD_OFF(f) (offsetof(struct hclge_32_bit_stats, f))
static int hclge_rss_init_hw(struct hclge_dev *hdev);
static int hclge_set_mta_filter_mode(struct hclge_dev *hdev,
enum hclge_mta_dmac_sel_type mta_mac_sel,
bool enable);
static int hclge_init_vlan_config(struct hclge_dev *hdev);
static struct hnae3_ae_algo ae_algo;
static const struct pci_device_id ae_algo_pci_tbl[] = {
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_GE), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_25GE_RDMA_MACSEC), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_50GE_RDMA_MACSEC), 0},
{PCI_VDEVICE(HUAWEI, HNAE3_DEV_ID_100G_RDMA_MACSEC), 0},
/* required last entry */
{0, }
};
static const char hns3_nic_test_strs[][ETH_GSTRING_LEN] = {
"Mac Loopback test",
"Serdes Loopback test",
"Phy Loopback test"
};
static const struct hclge_comm_stats_str g_all_64bit_stats_string[] = {
{"igu_rx_oversize_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_oversize_pkt)},
{"igu_rx_undersize_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_undersize_pkt)},
{"igu_rx_out_all_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_out_all_pkt)},
{"igu_rx_uni_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_uni_pkt)},
{"igu_rx_multi_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_multi_pkt)},
{"igu_rx_broad_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(igu_rx_broad_pkt)},
{"egu_tx_out_all_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_out_all_pkt)},
{"egu_tx_uni_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_uni_pkt)},
{"egu_tx_multi_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_multi_pkt)},
{"egu_tx_broad_pkt",
HCLGE_64BIT_STATS_FIELD_OFF(egu_tx_broad_pkt)},
{"ssu_ppp_mac_key_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_mac_key_num)},
{"ssu_ppp_host_key_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_ppp_host_key_num)},
{"ppp_ssu_mac_rlt_num",
HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_mac_rlt_num)},
{"ppp_ssu_host_rlt_num",
HCLGE_64BIT_STATS_FIELD_OFF(ppp_ssu_host_rlt_num)},
{"ssu_tx_in_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_in_num)},
{"ssu_tx_out_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_tx_out_num)},
{"ssu_rx_in_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_in_num)},
{"ssu_rx_out_num",
HCLGE_64BIT_STATS_FIELD_OFF(ssu_rx_out_num)}
};
static const struct hclge_comm_stats_str g_all_32bit_stats_string[] = {
{"igu_rx_err_pkt",
HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_err_pkt)},
{"igu_rx_no_eof_pkt",
HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_eof_pkt)},
{"igu_rx_no_sof_pkt",
HCLGE_32BIT_STATS_FIELD_OFF(igu_rx_no_sof_pkt)},
{"egu_tx_1588_pkt",
HCLGE_32BIT_STATS_FIELD_OFF(egu_tx_1588_pkt)},
{"ssu_full_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(ssu_full_drop_num)},
{"ssu_part_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(ssu_part_drop_num)},
{"ppp_key_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(ppp_key_drop_num)},
{"ppp_rlt_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(ppp_rlt_drop_num)},
{"ssu_key_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(ssu_key_drop_num)},
{"pkt_curr_buf_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_cnt)},
{"qcn_fb_rcv_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_rcv_cnt)},
{"qcn_fb_drop_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_drop_cnt)},
{"qcn_fb_invaild_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(qcn_fb_invaild_cnt)},
{"rx_packet_tc0_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_in_cnt)},
{"rx_packet_tc1_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_in_cnt)},
{"rx_packet_tc2_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_in_cnt)},
{"rx_packet_tc3_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_in_cnt)},
{"rx_packet_tc4_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_in_cnt)},
{"rx_packet_tc5_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_in_cnt)},
{"rx_packet_tc6_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_in_cnt)},
{"rx_packet_tc7_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_in_cnt)},
{"rx_packet_tc0_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc0_out_cnt)},
{"rx_packet_tc1_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc1_out_cnt)},
{"rx_packet_tc2_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc2_out_cnt)},
{"rx_packet_tc3_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc3_out_cnt)},
{"rx_packet_tc4_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc4_out_cnt)},
{"rx_packet_tc5_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc5_out_cnt)},
{"rx_packet_tc6_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc6_out_cnt)},
{"rx_packet_tc7_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_packet_tc7_out_cnt)},
{"tx_packet_tc0_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_in_cnt)},
{"tx_packet_tc1_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_in_cnt)},
{"tx_packet_tc2_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_in_cnt)},
{"tx_packet_tc3_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_in_cnt)},
{"tx_packet_tc4_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_in_cnt)},
{"tx_packet_tc5_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_in_cnt)},
{"tx_packet_tc6_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_in_cnt)},
{"tx_packet_tc7_in_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_in_cnt)},
{"tx_packet_tc0_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc0_out_cnt)},
{"tx_packet_tc1_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc1_out_cnt)},
{"tx_packet_tc2_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc2_out_cnt)},
{"tx_packet_tc3_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc3_out_cnt)},
{"tx_packet_tc4_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc4_out_cnt)},
{"tx_packet_tc5_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc5_out_cnt)},
{"tx_packet_tc6_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc6_out_cnt)},
{"tx_packet_tc7_out_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_packet_tc7_out_cnt)},
{"pkt_curr_buf_tc0_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc0_cnt)},
{"pkt_curr_buf_tc1_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc1_cnt)},
{"pkt_curr_buf_tc2_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc2_cnt)},
{"pkt_curr_buf_tc3_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc3_cnt)},
{"pkt_curr_buf_tc4_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc4_cnt)},
{"pkt_curr_buf_tc5_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc5_cnt)},
{"pkt_curr_buf_tc6_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc6_cnt)},
{"pkt_curr_buf_tc7_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(pkt_curr_buf_tc7_cnt)},
{"mb_uncopy_num",
HCLGE_32BIT_STATS_FIELD_OFF(mb_uncopy_num)},
{"lo_pri_unicast_rlt_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_unicast_rlt_drop_num)},
{"hi_pri_multicast_rlt_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(hi_pri_multicast_rlt_drop_num)},
{"lo_pri_multicast_rlt_drop_num",
HCLGE_32BIT_STATS_FIELD_OFF(lo_pri_multicast_rlt_drop_num)},
{"rx_oq_drop_pkt_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(rx_oq_drop_pkt_cnt)},
{"tx_oq_drop_pkt_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(tx_oq_drop_pkt_cnt)},
{"nic_l2_err_drop_pkt_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(nic_l2_err_drop_pkt_cnt)},
{"roc_l2_err_drop_pkt_cnt",
HCLGE_32BIT_STATS_FIELD_OFF(roc_l2_err_drop_pkt_cnt)}
};
static const struct hclge_comm_stats_str g_mac_stats_string[] = {
{"mac_tx_mac_pause_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_mac_pause_num)},
{"mac_rx_mac_pause_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_mac_pause_num)},
{"mac_tx_pfc_pri0_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri0_pkt_num)},
{"mac_tx_pfc_pri1_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri1_pkt_num)},
{"mac_tx_pfc_pri2_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri2_pkt_num)},
{"mac_tx_pfc_pri3_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri3_pkt_num)},
{"mac_tx_pfc_pri4_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri4_pkt_num)},
{"mac_tx_pfc_pri5_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri5_pkt_num)},
{"mac_tx_pfc_pri6_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri6_pkt_num)},
{"mac_tx_pfc_pri7_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_pfc_pri7_pkt_num)},
{"mac_rx_pfc_pri0_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri0_pkt_num)},
{"mac_rx_pfc_pri1_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri1_pkt_num)},
{"mac_rx_pfc_pri2_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri2_pkt_num)},
{"mac_rx_pfc_pri3_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri3_pkt_num)},
{"mac_rx_pfc_pri4_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri4_pkt_num)},
{"mac_rx_pfc_pri5_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri5_pkt_num)},
{"mac_rx_pfc_pri6_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri6_pkt_num)},
{"mac_rx_pfc_pri7_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_pfc_pri7_pkt_num)},
{"mac_tx_total_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_pkt_num)},
{"mac_tx_total_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_total_oct_num)},
{"mac_tx_good_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_pkt_num)},
{"mac_tx_bad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_pkt_num)},
{"mac_tx_good_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_good_oct_num)},
{"mac_tx_bad_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_bad_oct_num)},
{"mac_tx_uni_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_uni_pkt_num)},
{"mac_tx_multi_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_multi_pkt_num)},
{"mac_tx_broad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_broad_pkt_num)},
{"mac_tx_undersize_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_undersize_pkt_num)},
{"mac_tx_overrsize_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_overrsize_pkt_num)},
{"mac_tx_64_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_64_oct_pkt_num)},
{"mac_tx_65_127_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_65_127_oct_pkt_num)},
{"mac_tx_128_255_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_128_255_oct_pkt_num)},
{"mac_tx_256_511_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_256_511_oct_pkt_num)},
{"mac_tx_512_1023_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_512_1023_oct_pkt_num)},
{"mac_tx_1024_1518_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1024_1518_oct_pkt_num)},
{"mac_tx_1519_max_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_tx_1519_max_oct_pkt_num)},
{"mac_rx_total_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_pkt_num)},
{"mac_rx_total_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_total_oct_num)},
{"mac_rx_good_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_pkt_num)},
{"mac_rx_bad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_pkt_num)},
{"mac_rx_good_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_good_oct_num)},
{"mac_rx_bad_oct_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_bad_oct_num)},
{"mac_rx_uni_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_uni_pkt_num)},
{"mac_rx_multi_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_multi_pkt_num)},
{"mac_rx_broad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_broad_pkt_num)},
{"mac_rx_undersize_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_undersize_pkt_num)},
{"mac_rx_overrsize_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_overrsize_pkt_num)},
{"mac_rx_64_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_64_oct_pkt_num)},
{"mac_rx_65_127_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_65_127_oct_pkt_num)},
{"mac_rx_128_255_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_128_255_oct_pkt_num)},
{"mac_rx_256_511_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_256_511_oct_pkt_num)},
{"mac_rx_512_1023_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_512_1023_oct_pkt_num)},
{"mac_rx_1024_1518_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1024_1518_oct_pkt_num)},
{"mac_rx_1519_max_oct_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rx_1519_max_oct_pkt_num)},
{"mac_trans_fragment_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_fragment_pkt_num)},
{"mac_trans_undermin_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_undermin_pkt_num)},
{"mac_trans_jabber_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_jabber_pkt_num)},
{"mac_trans_err_all_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_err_all_pkt_num)},
{"mac_trans_from_app_good_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_good_pkt_num)},
{"mac_trans_from_app_bad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_trans_from_app_bad_pkt_num)},
{"mac_rcv_fragment_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fragment_pkt_num)},
{"mac_rcv_undermin_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_undermin_pkt_num)},
{"mac_rcv_jabber_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_jabber_pkt_num)},
{"mac_rcv_fcs_err_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_fcs_err_pkt_num)},
{"mac_rcv_send_app_good_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_good_pkt_num)},
{"mac_rcv_send_app_bad_pkt_num",
HCLGE_MAC_STATS_FIELD_OFF(mac_rcv_send_app_bad_pkt_num)}
};
static int hclge_64_bit_update_stats(struct hclge_dev *hdev)
{
#define HCLGE_64_BIT_CMD_NUM 5
#define HCLGE_64_BIT_RTN_DATANUM 4
u64 *data = (u64 *)(&hdev->hw_stats.all_64_bit_stats);
struct hclge_desc desc[HCLGE_64_BIT_CMD_NUM];
u64 *desc_data;
int i, k, n;
int ret;
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_64_BIT, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_64_BIT_CMD_NUM);
if (ret) {
dev_err(&hdev->pdev->dev,
"Get 64 bit pkt stats fail, status = %d.\n", ret);
return ret;
}
for (i = 0; i < HCLGE_64_BIT_CMD_NUM; i++) {
if (unlikely(i == 0)) {
desc_data = (u64 *)(&desc[i].data[0]);
n = HCLGE_64_BIT_RTN_DATANUM - 1;
} else {
desc_data = (u64 *)(&desc[i]);
n = HCLGE_64_BIT_RTN_DATANUM;
}
for (k = 0; k < n; k++) {
*data++ += cpu_to_le64(*desc_data);
desc_data++;
}
}
return 0;
}
static void hclge_reset_partial_32bit_counter(struct hclge_32_bit_stats *stats)
{
stats->pkt_curr_buf_cnt = 0;
stats->pkt_curr_buf_tc0_cnt = 0;
stats->pkt_curr_buf_tc1_cnt = 0;
stats->pkt_curr_buf_tc2_cnt = 0;
stats->pkt_curr_buf_tc3_cnt = 0;
stats->pkt_curr_buf_tc4_cnt = 0;
stats->pkt_curr_buf_tc5_cnt = 0;
stats->pkt_curr_buf_tc6_cnt = 0;
stats->pkt_curr_buf_tc7_cnt = 0;
}
static int hclge_32_bit_update_stats(struct hclge_dev *hdev)
{
#define HCLGE_32_BIT_CMD_NUM 8
#define HCLGE_32_BIT_RTN_DATANUM 8
struct hclge_desc desc[HCLGE_32_BIT_CMD_NUM];
struct hclge_32_bit_stats *all_32_bit_stats;
u32 *desc_data;
int i, k, n;
u64 *data;
int ret;
all_32_bit_stats = &hdev->hw_stats.all_32_bit_stats;
data = (u64 *)(&all_32_bit_stats->egu_tx_1588_pkt);
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_32_BIT, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_32_BIT_CMD_NUM);
if (ret) {
dev_err(&hdev->pdev->dev,
"Get 32 bit pkt stats fail, status = %d.\n", ret);
return ret;
}
hclge_reset_partial_32bit_counter(all_32_bit_stats);
for (i = 0; i < HCLGE_32_BIT_CMD_NUM; i++) {
if (unlikely(i == 0)) {
all_32_bit_stats->igu_rx_err_pkt +=
cpu_to_le32(desc[i].data[0]);
all_32_bit_stats->igu_rx_no_eof_pkt +=
cpu_to_le32(desc[i].data[1] & 0xffff);
all_32_bit_stats->igu_rx_no_sof_pkt +=
cpu_to_le32((desc[i].data[1] >> 16) & 0xffff);
desc_data = (u32 *)(&desc[i].data[2]);
n = HCLGE_32_BIT_RTN_DATANUM - 4;
} else {
desc_data = (u32 *)(&desc[i]);
n = HCLGE_32_BIT_RTN_DATANUM;
}
for (k = 0; k < n; k++) {
*data++ += cpu_to_le32(*desc_data);
desc_data++;
}
}
return 0;
}
static int hclge_mac_update_stats(struct hclge_dev *hdev)
{
#define HCLGE_MAC_CMD_NUM 17
#define HCLGE_RTN_DATA_NUM 4
u64 *data = (u64 *)(&hdev->hw_stats.mac_stats);
struct hclge_desc desc[HCLGE_MAC_CMD_NUM];
u64 *desc_data;
int i, k, n;
int ret;
hclge_cmd_setup_basic_desc(&desc[0], HCLGE_OPC_STATS_MAC, true);
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_MAC_CMD_NUM);
if (ret) {
dev_err(&hdev->pdev->dev,
"Get MAC pkt stats fail, status = %d.\n", ret);
return ret;
}
for (i = 0; i < HCLGE_MAC_CMD_NUM; i++) {
if (unlikely(i == 0)) {
desc_data = (u64 *)(&desc[i].data[0]);
n = HCLGE_RTN_DATA_NUM - 2;
} else {
desc_data = (u64 *)(&desc[i]);
n = HCLGE_RTN_DATA_NUM;
}
for (k = 0; k < n; k++) {
*data++ += cpu_to_le64(*desc_data);
desc_data++;
}
}
return 0;
}
static int hclge_tqps_update_stats(struct hnae3_handle *handle)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
struct hnae3_queue *queue;
struct hclge_desc desc[1];
struct hclge_tqp *tqp;
int ret, i;
for (i = 0; i < kinfo->num_tqps; i++) {
queue = handle->kinfo.tqp[i];
tqp = container_of(queue, struct hclge_tqp, q);
/* command : HCLGE_OPC_QUERY_IGU_STAT */
hclge_cmd_setup_basic_desc(&desc[0],
HCLGE_OPC_QUERY_RX_STATUS,
true);
desc[0].data[0] = (tqp->index & 0x1ff);
ret = hclge_cmd_send(&hdev->hw, desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Query tqp stat fail, status = %d,queue = %d\n",
ret, i);
return ret;
}
tqp->tqp_stats.rcb_rx_ring_pktnum_rcd +=
cpu_to_le32(desc[0].data[4]);
}
for (i = 0; i < kinfo->num_tqps; i++) {
queue = handle->kinfo.tqp[i];
tqp = container_of(queue, struct hclge_tqp, q);
/* command : HCLGE_OPC_QUERY_IGU_STAT */
hclge_cmd_setup_basic_desc(&desc[0],
HCLGE_OPC_QUERY_TX_STATUS,
true);
desc[0].data[0] = (tqp->index & 0x1ff);
ret = hclge_cmd_send(&hdev->hw, desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Query tqp stat fail, status = %d,queue = %d\n",
ret, i);
return ret;
}
tqp->tqp_stats.rcb_tx_ring_pktnum_rcd +=
cpu_to_le32(desc[0].data[4]);
}
return 0;
}
static u64 *hclge_tqps_get_stats(struct hnae3_handle *handle, u64 *data)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
struct hclge_tqp *tqp;
u64 *buff = data;
int i;
for (i = 0; i < kinfo->num_tqps; i++) {
tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
*buff++ = cpu_to_le64(tqp->tqp_stats.rcb_tx_ring_pktnum_rcd);
}
for (i = 0; i < kinfo->num_tqps; i++) {
tqp = container_of(kinfo->tqp[i], struct hclge_tqp, q);
*buff++ = cpu_to_le64(tqp->tqp_stats.rcb_rx_ring_pktnum_rcd);
}
return buff;
}
static int hclge_tqps_get_sset_count(struct hnae3_handle *handle, int stringset)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
return kinfo->num_tqps * (2);
}
static u8 *hclge_tqps_get_strings(struct hnae3_handle *handle, u8 *data)
{
struct hnae3_knic_private_info *kinfo = &handle->kinfo;
u8 *buff = data;
int i = 0;
for (i = 0; i < kinfo->num_tqps; i++) {
struct hclge_tqp *tqp = container_of(handle->kinfo.tqp[i],
struct hclge_tqp, q);
snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_tx_pktnum_rcd",
tqp->index);
buff = buff + ETH_GSTRING_LEN;
}
for (i = 0; i < kinfo->num_tqps; i++) {
struct hclge_tqp *tqp = container_of(kinfo->tqp[i],
struct hclge_tqp, q);
snprintf(buff, ETH_GSTRING_LEN, "rcb_q%d_rx_pktnum_rcd",
tqp->index);
buff = buff + ETH_GSTRING_LEN;
}
return buff;
}
static u64 *hclge_comm_get_stats(void *comm_stats,
const struct hclge_comm_stats_str strs[],
int size, u64 *data)
{
u64 *buf = data;
u32 i;
for (i = 0; i < size; i++)
buf[i] = HCLGE_STATS_READ(comm_stats, strs[i].offset);
return buf + size;
}
static u8 *hclge_comm_get_strings(u32 stringset,
const struct hclge_comm_stats_str strs[],
int size, u8 *data)
{
char *buff = (char *)data;
u32 i;
if (stringset != ETH_SS_STATS)
return buff;
for (i = 0; i < size; i++) {
snprintf(buff, ETH_GSTRING_LEN,
strs[i].desc);
buff = buff + ETH_GSTRING_LEN;
}
return (u8 *)buff;
}
static void hclge_update_netstat(struct hclge_hw_stats *hw_stats,
struct net_device_stats *net_stats)
{
net_stats->tx_dropped = 0;
net_stats->rx_dropped = hw_stats->all_32_bit_stats.ssu_full_drop_num;
net_stats->rx_dropped += hw_stats->all_32_bit_stats.ppp_key_drop_num;
net_stats->rx_dropped += hw_stats->all_32_bit_stats.ssu_key_drop_num;
net_stats->rx_errors = hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
net_stats->rx_errors += hw_stats->mac_stats.mac_rx_undersize_pkt_num;
net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_err_pkt;
net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_eof_pkt;
net_stats->rx_errors += hw_stats->all_32_bit_stats.igu_rx_no_sof_pkt;
net_stats->rx_errors += hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
net_stats->multicast = hw_stats->mac_stats.mac_tx_multi_pkt_num;
net_stats->multicast += hw_stats->mac_stats.mac_rx_multi_pkt_num;
net_stats->rx_crc_errors = hw_stats->mac_stats.mac_rcv_fcs_err_pkt_num;
net_stats->rx_length_errors =
hw_stats->mac_stats.mac_rx_undersize_pkt_num;
net_stats->rx_length_errors +=
hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
net_stats->rx_over_errors =
hw_stats->mac_stats.mac_rx_overrsize_pkt_num;
}
static void hclge_update_stats_for_all(struct hclge_dev *hdev)
{
struct hnae3_handle *handle;
int status;
handle = &hdev->vport[0].nic;
if (handle->client) {
status = hclge_tqps_update_stats(handle);
if (status) {
dev_err(&hdev->pdev->dev,
"Update TQPS stats fail, status = %d.\n",
status);
}
}
status = hclge_mac_update_stats(hdev);
if (status)
dev_err(&hdev->pdev->dev,
"Update MAC stats fail, status = %d.\n", status);
status = hclge_32_bit_update_stats(hdev);
if (status)
dev_err(&hdev->pdev->dev,
"Update 32 bit stats fail, status = %d.\n",
status);
hclge_update_netstat(&hdev->hw_stats, &handle->kinfo.netdev->stats);
}
static void hclge_update_stats(struct hnae3_handle *handle,
struct net_device_stats *net_stats)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
struct hclge_hw_stats *hw_stats = &hdev->hw_stats;
int status;
status = hclge_mac_update_stats(hdev);
if (status)
dev_err(&hdev->pdev->dev,
"Update MAC stats fail, status = %d.\n",
status);
status = hclge_32_bit_update_stats(hdev);
if (status)
dev_err(&hdev->pdev->dev,
"Update 32 bit stats fail, status = %d.\n",
status);
status = hclge_64_bit_update_stats(hdev);
if (status)
dev_err(&hdev->pdev->dev,
"Update 64 bit stats fail, status = %d.\n",
status);
status = hclge_tqps_update_stats(handle);
if (status)
dev_err(&hdev->pdev->dev,
"Update TQPS stats fail, status = %d.\n",
status);
hclge_update_netstat(hw_stats, net_stats);
}
static int hclge_get_sset_count(struct hnae3_handle *handle, int stringset)
{
#define HCLGE_LOOPBACK_TEST_FLAGS 0x7
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
int count = 0;
/* Loopback test support rules:
* mac: only GE mode support
* serdes: all mac mode will support include GE/XGE/LGE/CGE
* phy: only support when phy device exist on board
*/
if (stringset == ETH_SS_TEST) {
/* clear loopback bit flags at first */
handle->flags = (handle->flags & (~HCLGE_LOOPBACK_TEST_FLAGS));
if (hdev->hw.mac.speed == HCLGE_MAC_SPEED_10M ||
hdev->hw.mac.speed == HCLGE_MAC_SPEED_100M ||
hdev->hw.mac.speed == HCLGE_MAC_SPEED_1G) {
count += 1;
handle->flags |= HNAE3_SUPPORT_MAC_LOOPBACK;
} else {
count = -EOPNOTSUPP;
}
} else if (stringset == ETH_SS_STATS) {
count = ARRAY_SIZE(g_mac_stats_string) +
ARRAY_SIZE(g_all_32bit_stats_string) +
ARRAY_SIZE(g_all_64bit_stats_string) +
hclge_tqps_get_sset_count(handle, stringset);
}
return count;
}
static void hclge_get_strings(struct hnae3_handle *handle,
u32 stringset,
u8 *data)
{
u8 *p = (char *)data;
int size;
if (stringset == ETH_SS_STATS) {
size = ARRAY_SIZE(g_mac_stats_string);
p = hclge_comm_get_strings(stringset,
g_mac_stats_string,
size,
p);
size = ARRAY_SIZE(g_all_32bit_stats_string);
p = hclge_comm_get_strings(stringset,
g_all_32bit_stats_string,
size,
p);
size = ARRAY_SIZE(g_all_64bit_stats_string);
p = hclge_comm_get_strings(stringset,
g_all_64bit_stats_string,
size,
p);
p = hclge_tqps_get_strings(handle, p);
} else if (stringset == ETH_SS_TEST) {
if (handle->flags & HNAE3_SUPPORT_MAC_LOOPBACK) {
memcpy(p,
hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_MAC],
ETH_GSTRING_LEN);
p += ETH_GSTRING_LEN;
}
if (handle->flags & HNAE3_SUPPORT_SERDES_LOOPBACK) {
memcpy(p,
hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_SERDES],
ETH_GSTRING_LEN);
p += ETH_GSTRING_LEN;
}
if (handle->flags & HNAE3_SUPPORT_PHY_LOOPBACK) {
memcpy(p,
hns3_nic_test_strs[HNAE3_MAC_INTER_LOOP_PHY],
ETH_GSTRING_LEN);
p += ETH_GSTRING_LEN;
}
}
}
static void hclge_get_stats(struct hnae3_handle *handle, u64 *data)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u64 *p;
p = hclge_comm_get_stats(&hdev->hw_stats.mac_stats,
g_mac_stats_string,
ARRAY_SIZE(g_mac_stats_string),
data);
p = hclge_comm_get_stats(&hdev->hw_stats.all_32_bit_stats,
g_all_32bit_stats_string,
ARRAY_SIZE(g_all_32bit_stats_string),
p);
p = hclge_comm_get_stats(&hdev->hw_stats.all_64_bit_stats,
g_all_64bit_stats_string,
ARRAY_SIZE(g_all_64bit_stats_string),
p);
p = hclge_tqps_get_stats(handle, p);
}
static int hclge_parse_func_status(struct hclge_dev *hdev,
struct hclge_func_status *status)
{
if (!(status->pf_state & HCLGE_PF_STATE_DONE))
return -EINVAL;
/* Set the pf to main pf */
if (status->pf_state & HCLGE_PF_STATE_MAIN)
hdev->flag |= HCLGE_FLAG_MAIN;
else
hdev->flag &= ~HCLGE_FLAG_MAIN;
hdev->num_req_vfs = status->vf_num / status->pf_num;
return 0;
}
static int hclge_query_function_status(struct hclge_dev *hdev)
{
struct hclge_func_status *req;
struct hclge_desc desc;
int timeout = 0;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_FUNC_STATUS, true);
req = (struct hclge_func_status *)desc.data;
do {
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"query function status failed %d.\n",
ret);
return ret;
}
/* Check pf reset is done */
if (req->pf_state)
break;
usleep_range(1000, 2000);
} while (timeout++ < 5);
ret = hclge_parse_func_status(hdev, req);
return ret;
}
static int hclge_query_pf_resource(struct hclge_dev *hdev)
{
struct hclge_pf_res *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_PF_RSRC, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"query pf resource failed %d.\n", ret);
return ret;
}
req = (struct hclge_pf_res *)desc.data;
hdev->num_tqps = __le16_to_cpu(req->tqp_num);
hdev->pkt_buf_size = __le16_to_cpu(req->buf_size) << HCLGE_BUF_UNIT_S;
if (hnae3_dev_roce_supported(hdev)) {
hdev->num_roce_msix =
hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
/* PF should have NIC vectors and Roce vectors,
* NIC vectors are queued before Roce vectors.
*/
hdev->num_msi = hdev->num_roce_msix + HCLGE_ROCE_VECTOR_OFFSET;
} else {
hdev->num_msi =
hnae_get_field(__le16_to_cpu(req->pf_intr_vector_number),
HCLGE_PF_VEC_NUM_M, HCLGE_PF_VEC_NUM_S);
}
return 0;
}
static int hclge_parse_speed(int speed_cmd, int *speed)
{
switch (speed_cmd) {
case 6:
*speed = HCLGE_MAC_SPEED_10M;
break;
case 7:
*speed = HCLGE_MAC_SPEED_100M;
break;
case 0:
*speed = HCLGE_MAC_SPEED_1G;
break;
case 1:
*speed = HCLGE_MAC_SPEED_10G;
break;
case 2:
*speed = HCLGE_MAC_SPEED_25G;
break;
case 3:
*speed = HCLGE_MAC_SPEED_40G;
break;
case 4:
*speed = HCLGE_MAC_SPEED_50G;
break;
case 5:
*speed = HCLGE_MAC_SPEED_100G;
break;
default:
return -EINVAL;
}
return 0;
}
static void hclge_parse_cfg(struct hclge_cfg *cfg, struct hclge_desc *desc)
{
struct hclge_cfg_param *req;
u64 mac_addr_tmp_high;
u64 mac_addr_tmp;
int i;
req = (struct hclge_cfg_param *)desc[0].data;
/* get the configuration */
cfg->vmdq_vport_num = hnae_get_field(__le32_to_cpu(req->param[0]),
HCLGE_CFG_VMDQ_M,
HCLGE_CFG_VMDQ_S);
cfg->tc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
HCLGE_CFG_TC_NUM_M, HCLGE_CFG_TC_NUM_S);
cfg->tqp_desc_num = hnae_get_field(__le32_to_cpu(req->param[0]),
HCLGE_CFG_TQP_DESC_N_M,
HCLGE_CFG_TQP_DESC_N_S);
cfg->phy_addr = hnae_get_field(__le32_to_cpu(req->param[1]),
HCLGE_CFG_PHY_ADDR_M,
HCLGE_CFG_PHY_ADDR_S);
cfg->media_type = hnae_get_field(__le32_to_cpu(req->param[1]),
HCLGE_CFG_MEDIA_TP_M,
HCLGE_CFG_MEDIA_TP_S);
cfg->rx_buf_len = hnae_get_field(__le32_to_cpu(req->param[1]),
HCLGE_CFG_RX_BUF_LEN_M,
HCLGE_CFG_RX_BUF_LEN_S);
/* get mac_address */
mac_addr_tmp = __le32_to_cpu(req->param[2]);
mac_addr_tmp_high = hnae_get_field(__le32_to_cpu(req->param[3]),
HCLGE_CFG_MAC_ADDR_H_M,
HCLGE_CFG_MAC_ADDR_H_S);
mac_addr_tmp |= (mac_addr_tmp_high << 31) << 1;
cfg->default_speed = hnae_get_field(__le32_to_cpu(req->param[3]),
HCLGE_CFG_DEFAULT_SPEED_M,
HCLGE_CFG_DEFAULT_SPEED_S);
for (i = 0; i < ETH_ALEN; i++)
cfg->mac_addr[i] = (mac_addr_tmp >> (8 * i)) & 0xff;
req = (struct hclge_cfg_param *)desc[1].data;
cfg->numa_node_map = __le32_to_cpu(req->param[0]);
}
/* hclge_get_cfg: query the static parameter from flash
* @hdev: pointer to struct hclge_dev
* @hcfg: the config structure to be getted
*/
static int hclge_get_cfg(struct hclge_dev *hdev, struct hclge_cfg *hcfg)
{
struct hclge_desc desc[HCLGE_PF_CFG_DESC_NUM];
struct hclge_cfg_param *req;
int i, ret;
for (i = 0; i < HCLGE_PF_CFG_DESC_NUM; i++) {
req = (struct hclge_cfg_param *)desc[i].data;
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_GET_CFG_PARAM,
true);
hnae_set_field(req->offset, HCLGE_CFG_OFFSET_M,
HCLGE_CFG_OFFSET_S, i * HCLGE_CFG_RD_LEN_BYTES);
/* Len should be united by 4 bytes when send to hardware */
hnae_set_field(req->offset, HCLGE_CFG_RD_LEN_M,
HCLGE_CFG_RD_LEN_S,
HCLGE_CFG_RD_LEN_BYTES / HCLGE_CFG_RD_LEN_UNIT);
req->offset = cpu_to_le32(req->offset);
}
ret = hclge_cmd_send(&hdev->hw, desc, HCLGE_PF_CFG_DESC_NUM);
if (ret) {
dev_err(&hdev->pdev->dev,
"get config failed %d.\n", ret);
return ret;
}
hclge_parse_cfg(hcfg, desc);
return 0;
}
static int hclge_get_cap(struct hclge_dev *hdev)
{
int ret;
ret = hclge_query_function_status(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"query function status error %d.\n", ret);
return ret;
}
/* get pf resource */
ret = hclge_query_pf_resource(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"query pf resource error %d.\n", ret);
return ret;
}
return 0;
}
static int hclge_configure(struct hclge_dev *hdev)
{
struct hclge_cfg cfg;
int ret, i;
ret = hclge_get_cfg(hdev, &cfg);
if (ret) {
dev_err(&hdev->pdev->dev, "get mac mode error %d.\n", ret);
return ret;
}
hdev->num_vmdq_vport = cfg.vmdq_vport_num;
hdev->base_tqp_pid = 0;
hdev->rss_size_max = 1;
hdev->rx_buf_len = cfg.rx_buf_len;
ether_addr_copy(hdev->hw.mac.mac_addr, cfg.mac_addr);
hdev->hw.mac.media_type = cfg.media_type;
hdev->hw.mac.phy_addr = cfg.phy_addr;
hdev->num_desc = cfg.tqp_desc_num;
hdev->tm_info.num_pg = 1;
hdev->tm_info.num_tc = cfg.tc_num;
hdev->tm_info.hw_pfc_map = 0;
ret = hclge_parse_speed(cfg.default_speed, &hdev->hw.mac.speed);
if (ret) {
dev_err(&hdev->pdev->dev, "Get wrong speed ret=%d.\n", ret);
return ret;
}
if ((hdev->tm_info.num_tc > HNAE3_MAX_TC) ||
(hdev->tm_info.num_tc < 1)) {
dev_warn(&hdev->pdev->dev, "TC num = %d.\n",
hdev->tm_info.num_tc);
hdev->tm_info.num_tc = 1;
}
/* Currently not support uncontiuous tc */
for (i = 0; i < cfg.tc_num; i++)
hnae_set_bit(hdev->hw_tc_map, i, 1);
if (!hdev->num_vmdq_vport && !hdev->num_req_vfs)
hdev->tx_sch_mode = HCLGE_FLAG_TC_BASE_SCH_MODE;
else
hdev->tx_sch_mode = HCLGE_FLAG_VNET_BASE_SCH_MODE;
return ret;
}
static int hclge_config_tso(struct hclge_dev *hdev, int tso_mss_min,
int tso_mss_max)
{
struct hclge_cfg_tso_status *req;
struct hclge_desc desc;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TSO_GENERIC_CONFIG, false);
req = (struct hclge_cfg_tso_status *)desc.data;
hnae_set_field(req->tso_mss_min, HCLGE_TSO_MSS_MIN_M,
HCLGE_TSO_MSS_MIN_S, tso_mss_min);
hnae_set_field(req->tso_mss_max, HCLGE_TSO_MSS_MIN_M,
HCLGE_TSO_MSS_MIN_S, tso_mss_max);
return hclge_cmd_send(&hdev->hw, &desc, 1);
}
static int hclge_alloc_tqps(struct hclge_dev *hdev)
{
struct hclge_tqp *tqp;
int i;
hdev->htqp = devm_kcalloc(&hdev->pdev->dev, hdev->num_tqps,
sizeof(struct hclge_tqp), GFP_KERNEL);
if (!hdev->htqp)
return -ENOMEM;
tqp = hdev->htqp;
for (i = 0; i < hdev->num_tqps; i++) {
tqp->dev = &hdev->pdev->dev;
tqp->index = i;
tqp->q.ae_algo = &ae_algo;
tqp->q.buf_size = hdev->rx_buf_len;
tqp->q.desc_num = hdev->num_desc;
tqp->q.io_base = hdev->hw.io_base + HCLGE_TQP_REG_OFFSET +
i * HCLGE_TQP_REG_SIZE;
tqp++;
}
return 0;
}
static int hclge_map_tqps_to_func(struct hclge_dev *hdev, u16 func_id,
u16 tqp_pid, u16 tqp_vid, bool is_pf)
{
struct hclge_tqp_map *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_SET_TQP_MAP, false);
req = (struct hclge_tqp_map *)desc.data;
req->tqp_id = cpu_to_le16(tqp_pid);
req->tqp_vf = cpu_to_le16(func_id);
req->tqp_flag = !is_pf << HCLGE_TQP_MAP_TYPE_B |
1 << HCLGE_TQP_MAP_EN_B;
req->tqp_vid = cpu_to_le16(tqp_vid);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "TQP map failed %d.\n",
ret);
return ret;
}
return 0;
}
static int hclge_assign_tqp(struct hclge_vport *vport,
struct hnae3_queue **tqp, u16 num_tqps)
{
struct hclge_dev *hdev = vport->back;
int i, alloced, func_id, ret;
bool is_pf;
func_id = vport->vport_id;
is_pf = (vport->vport_id == 0) ? true : false;
for (i = 0, alloced = 0; i < hdev->num_tqps &&
alloced < num_tqps; i++) {
if (!hdev->htqp[i].alloced) {
hdev->htqp[i].q.handle = &vport->nic;
hdev->htqp[i].q.tqp_index = alloced;
tqp[alloced] = &hdev->htqp[i].q;
hdev->htqp[i].alloced = true;
ret = hclge_map_tqps_to_func(hdev, func_id,
hdev->htqp[i].index,
alloced, is_pf);
if (ret)
return ret;
alloced++;
}
}
vport->alloc_tqps = num_tqps;
return 0;
}
static int hclge_knic_setup(struct hclge_vport *vport, u16 num_tqps)
{
struct hnae3_handle *nic = &vport->nic;
struct hnae3_knic_private_info *kinfo = &nic->kinfo;
struct hclge_dev *hdev = vport->back;
int i, ret;
kinfo->num_desc = hdev->num_desc;
kinfo->rx_buf_len = hdev->rx_buf_len;
kinfo->num_tc = min_t(u16, num_tqps, hdev->tm_info.num_tc);
kinfo->rss_size
= min_t(u16, hdev->rss_size_max, num_tqps / kinfo->num_tc);
kinfo->num_tqps = kinfo->rss_size * kinfo->num_tc;
for (i = 0; i < HNAE3_MAX_TC; i++) {
if (hdev->hw_tc_map & BIT(i)) {
kinfo->tc_info[i].enable = true;
kinfo->tc_info[i].tqp_offset = i * kinfo->rss_size;
kinfo->tc_info[i].tqp_count = kinfo->rss_size;
kinfo->tc_info[i].tc = i;
} else {
/* Set to default queue if TC is disable */
kinfo->tc_info[i].enable = false;
kinfo->tc_info[i].tqp_offset = 0;
kinfo->tc_info[i].tqp_count = 1;
kinfo->tc_info[i].tc = 0;
}
}
kinfo->tqp = devm_kcalloc(&hdev->pdev->dev, kinfo->num_tqps,
sizeof(struct hnae3_queue *), GFP_KERNEL);
if (!kinfo->tqp)
return -ENOMEM;
ret = hclge_assign_tqp(vport, kinfo->tqp, kinfo->num_tqps);
if (ret) {
dev_err(&hdev->pdev->dev, "fail to assign TQPs %d.\n", ret);
return -EINVAL;
}
return 0;
}
static void hclge_unic_setup(struct hclge_vport *vport, u16 num_tqps)
{
/* this would be initialized later */
}
static int hclge_vport_setup(struct hclge_vport *vport, u16 num_tqps)
{
struct hnae3_handle *nic = &vport->nic;
struct hclge_dev *hdev = vport->back;
int ret;
nic->pdev = hdev->pdev;
nic->ae_algo = &ae_algo;
nic->numa_node_mask = hdev->numa_node_mask;
if (hdev->ae_dev->dev_type == HNAE3_DEV_KNIC) {
ret = hclge_knic_setup(vport, num_tqps);
if (ret) {
dev_err(&hdev->pdev->dev, "knic setup failed %d\n",
ret);
return ret;
}
} else {
hclge_unic_setup(vport, num_tqps);
}
return 0;
}
static int hclge_alloc_vport(struct hclge_dev *hdev)
{
struct pci_dev *pdev = hdev->pdev;
struct hclge_vport *vport;
u32 tqp_main_vport;
u32 tqp_per_vport;
int num_vport, i;
int ret;
/* We need to alloc a vport for main NIC of PF */
num_vport = hdev->num_vmdq_vport + hdev->num_req_vfs + 1;
if (hdev->num_tqps < num_vport)
num_vport = hdev->num_tqps;
/* Alloc the same number of TQPs for every vport */
tqp_per_vport = hdev->num_tqps / num_vport;
tqp_main_vport = tqp_per_vport + hdev->num_tqps % num_vport;
vport = devm_kcalloc(&pdev->dev, num_vport, sizeof(struct hclge_vport),
GFP_KERNEL);
if (!vport)
return -ENOMEM;
hdev->vport = vport;
hdev->num_alloc_vport = num_vport;
#ifdef CONFIG_PCI_IOV
/* Enable SRIOV */
if (hdev->num_req_vfs) {
dev_info(&pdev->dev, "active VFs(%d) found, enabling SRIOV\n",
hdev->num_req_vfs);
ret = pci_enable_sriov(hdev->pdev, hdev->num_req_vfs);
if (ret) {
hdev->num_alloc_vfs = 0;
dev_err(&pdev->dev, "SRIOV enable failed %d\n",
ret);
return ret;
}
}
hdev->num_alloc_vfs = hdev->num_req_vfs;
#endif
for (i = 0; i < num_vport; i++) {
vport->back = hdev;
vport->vport_id = i;
if (i == 0)
ret = hclge_vport_setup(vport, tqp_main_vport);
else
ret = hclge_vport_setup(vport, tqp_per_vport);
if (ret) {
dev_err(&pdev->dev,
"vport setup failed for vport %d, %d\n",
i, ret);
return ret;
}
vport++;
}
return 0;
}
static int hclge_cmd_alloc_tx_buff(struct hclge_dev *hdev, u16 buf_size)
{
/* TX buffer size is unit by 128 byte */
#define HCLGE_BUF_SIZE_UNIT_SHIFT 7
#define HCLGE_BUF_SIZE_UPDATE_EN_MSK BIT(15)
struct hclge_tx_buff_alloc *req;
struct hclge_desc desc;
int ret;
u8 i;
req = (struct hclge_tx_buff_alloc *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_TX_BUFF_ALLOC, 0);
for (i = 0; i < HCLGE_TC_NUM; i++)
req->tx_pkt_buff[i] =
cpu_to_le16((buf_size >> HCLGE_BUF_SIZE_UNIT_SHIFT) |
HCLGE_BUF_SIZE_UPDATE_EN_MSK);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "tx buffer alloc cmd failed %d.\n",
ret);
return ret;
}
return 0;
}
static int hclge_tx_buffer_alloc(struct hclge_dev *hdev, u32 buf_size)
{
int ret = hclge_cmd_alloc_tx_buff(hdev, buf_size);
if (ret) {
dev_err(&hdev->pdev->dev,
"tx buffer alloc failed %d\n", ret);
return ret;
}
return 0;
}
static int hclge_get_tc_num(struct hclge_dev *hdev)
{
int i, cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
if (hdev->hw_tc_map & BIT(i))
cnt++;
return cnt;
}
static int hclge_get_pfc_enalbe_num(struct hclge_dev *hdev)
{
int i, cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++)
if (hdev->hw_tc_map & BIT(i) &&
hdev->tm_info.hw_pfc_map & BIT(i))
cnt++;
return cnt;
}
/* Get the number of pfc enabled TCs, which have private buffer */
static int hclge_get_pfc_priv_num(struct hclge_dev *hdev)
{
struct hclge_priv_buf *priv;
int i, cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &hdev->priv_buf[i];
if ((hdev->tm_info.hw_pfc_map & BIT(i)) &&
priv->enable)
cnt++;
}
return cnt;
}
/* Get the number of pfc disabled TCs, which have private buffer */
static int hclge_get_no_pfc_priv_num(struct hclge_dev *hdev)
{
struct hclge_priv_buf *priv;
int i, cnt = 0;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &hdev->priv_buf[i];
if (hdev->hw_tc_map & BIT(i) &&
!(hdev->tm_info.hw_pfc_map & BIT(i)) &&
priv->enable)
cnt++;
}
return cnt;
}
static u32 hclge_get_rx_priv_buff_alloced(struct hclge_dev *hdev)
{
struct hclge_priv_buf *priv;
u32 rx_priv = 0;
int i;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &hdev->priv_buf[i];
if (priv->enable)
rx_priv += priv->buf_size;
}
return rx_priv;
}
static bool hclge_is_rx_buf_ok(struct hclge_dev *hdev, u32 rx_all)
{
u32 shared_buf_min, shared_buf_tc, shared_std;
int tc_num, pfc_enable_num;
u32 shared_buf;
u32 rx_priv;
int i;
tc_num = hclge_get_tc_num(hdev);
pfc_enable_num = hclge_get_pfc_enalbe_num(hdev);
if (hnae3_dev_dcb_supported(hdev))
shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_DV;
else
shared_buf_min = 2 * hdev->mps + HCLGE_DEFAULT_NON_DCB_DV;
shared_buf_tc = pfc_enable_num * hdev->mps +
(tc_num - pfc_enable_num) * hdev->mps / 2 +
hdev->mps;
shared_std = max_t(u32, shared_buf_min, shared_buf_tc);
rx_priv = hclge_get_rx_priv_buff_alloced(hdev);
if (rx_all <= rx_priv + shared_std)
return false;
shared_buf = rx_all - rx_priv;
hdev->s_buf.buf_size = shared_buf;
hdev->s_buf.self.high = shared_buf;
hdev->s_buf.self.low = 2 * hdev->mps;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
if ((hdev->hw_tc_map & BIT(i)) &&
(hdev->tm_info.hw_pfc_map & BIT(i))) {
hdev->s_buf.tc_thrd[i].low = hdev->mps;
hdev->s_buf.tc_thrd[i].high = 2 * hdev->mps;
} else {
hdev->s_buf.tc_thrd[i].low = 0;
hdev->s_buf.tc_thrd[i].high = hdev->mps;
}
}
return true;
}
/* hclge_rx_buffer_calc: calculate the rx private buffer size for all TCs
* @hdev: pointer to struct hclge_dev
* @tx_size: the allocated tx buffer for all TCs
* @return: 0: calculate sucessful, negative: fail
*/
int hclge_rx_buffer_calc(struct hclge_dev *hdev, u32 tx_size)
{
u32 rx_all = hdev->pkt_buf_size - tx_size;
int no_pfc_priv_num, pfc_priv_num;
struct hclge_priv_buf *priv;
int i;
/* When DCB is not supported, rx private
* buffer is not allocated.
*/
if (!hnae3_dev_dcb_supported(hdev)) {
if (!hclge_is_rx_buf_ok(hdev, rx_all))
return -ENOMEM;
return 0;
}
/* step 1, try to alloc private buffer for all enabled tc */
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &hdev->priv_buf[i];
if (hdev->hw_tc_map & BIT(i)) {
priv->enable = 1;
if (hdev->tm_info.hw_pfc_map & BIT(i)) {
priv->wl.low = hdev->mps;
priv->wl.high = priv->wl.low + hdev->mps;
priv->buf_size = priv->wl.high +
HCLGE_DEFAULT_DV;
} else {
priv->wl.low = 0;
priv->wl.high = 2 * hdev->mps;
priv->buf_size = priv->wl.high;
}
} else {
priv->enable = 0;
priv->wl.low = 0;
priv->wl.high = 0;
priv->buf_size = 0;
}
}
if (hclge_is_rx_buf_ok(hdev, rx_all))
return 0;
/* step 2, try to decrease the buffer size of
* no pfc TC's private buffer
*/
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
priv = &hdev->priv_buf[i];
priv->enable = 0;
priv->wl.low = 0;
priv->wl.high = 0;
priv->buf_size = 0;
if (!(hdev->hw_tc_map & BIT(i)))
continue;
priv->enable = 1;
if (hdev->tm_info.hw_pfc_map & BIT(i)) {
priv->wl.low = 128;
priv->wl.high = priv->wl.low + hdev->mps;
priv->buf_size = priv->wl.high + HCLGE_DEFAULT_DV;
} else {
priv->wl.low = 0;
priv->wl.high = hdev->mps;
priv->buf_size = priv->wl.high;
}
}
if (hclge_is_rx_buf_ok(hdev, rx_all))
return 0;
/* step 3, try to reduce the number of pfc disabled TCs,
* which have private buffer
*/
/* get the total no pfc enable TC number, which have private buffer */
no_pfc_priv_num = hclge_get_no_pfc_priv_num(hdev);
/* let the last to be cleared first */
for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
priv = &hdev->priv_buf[i];
if (hdev->hw_tc_map & BIT(i) &&
!(hdev->tm_info.hw_pfc_map & BIT(i))) {
/* Clear the no pfc TC private buffer */
priv->wl.low = 0;
priv->wl.high = 0;
priv->buf_size = 0;
priv->enable = 0;
no_pfc_priv_num--;
}
if (hclge_is_rx_buf_ok(hdev, rx_all) ||
no_pfc_priv_num == 0)
break;
}
if (hclge_is_rx_buf_ok(hdev, rx_all))
return 0;
/* step 4, try to reduce the number of pfc enabled TCs
* which have private buffer.
*/
pfc_priv_num = hclge_get_pfc_priv_num(hdev);
/* let the last to be cleared first */
for (i = HCLGE_MAX_TC_NUM - 1; i >= 0; i--) {
priv = &hdev->priv_buf[i];
if (hdev->hw_tc_map & BIT(i) &&
hdev->tm_info.hw_pfc_map & BIT(i)) {
/* Reduce the number of pfc TC with private buffer */
priv->wl.low = 0;
priv->enable = 0;
priv->wl.high = 0;
priv->buf_size = 0;
pfc_priv_num--;
}
if (hclge_is_rx_buf_ok(hdev, rx_all) ||
pfc_priv_num == 0)
break;
}
if (hclge_is_rx_buf_ok(hdev, rx_all))
return 0;
return -ENOMEM;
}
static int hclge_rx_priv_buf_alloc(struct hclge_dev *hdev)
{
struct hclge_rx_priv_buff *req;
struct hclge_desc desc;
int ret;
int i;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_PRIV_BUFF_ALLOC, false);
req = (struct hclge_rx_priv_buff *)desc.data;
/* Alloc private buffer TCs */
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
struct hclge_priv_buf *priv = &hdev->priv_buf[i];
req->buf_num[i] =
cpu_to_le16(priv->buf_size >> HCLGE_BUF_UNIT_S);
req->buf_num[i] |=
cpu_to_le16(true << HCLGE_TC0_PRI_BUF_EN_B);
}
req->shared_buf =
cpu_to_le16((hdev->s_buf.buf_size >> HCLGE_BUF_UNIT_S) |
(1 << HCLGE_TC0_PRI_BUF_EN_B));
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"rx private buffer alloc cmd failed %d\n", ret);
return ret;
}
return 0;
}
#define HCLGE_PRIV_ENABLE(a) ((a) > 0 ? 1 : 0)
static int hclge_rx_priv_wl_config(struct hclge_dev *hdev)
{
struct hclge_rx_priv_wl_buf *req;
struct hclge_priv_buf *priv;
struct hclge_desc desc[2];
int i, j;
int ret;
for (i = 0; i < 2; i++) {
hclge_cmd_setup_basic_desc(&desc[i], HCLGE_OPC_RX_PRIV_WL_ALLOC,
false);
req = (struct hclge_rx_priv_wl_buf *)desc[i].data;
/* The first descriptor set the NEXT bit to 1 */
if (i == 0)
desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
else
desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
priv = &hdev->priv_buf[i * HCLGE_TC_NUM_ONE_DESC + j];
req->tc_wl[j].high =
cpu_to_le16(priv->wl.high >> HCLGE_BUF_UNIT_S);
req->tc_wl[j].high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.high) <<
HCLGE_RX_PRIV_EN_B);
req->tc_wl[j].low =
cpu_to_le16(priv->wl.low >> HCLGE_BUF_UNIT_S);
req->tc_wl[j].low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(priv->wl.low) <<
HCLGE_RX_PRIV_EN_B);
}
}
/* Send 2 descriptor at one time */
ret = hclge_cmd_send(&hdev->hw, desc, 2);
if (ret) {
dev_err(&hdev->pdev->dev,
"rx private waterline config cmd failed %d\n",
ret);
return ret;
}
return 0;
}
static int hclge_common_thrd_config(struct hclge_dev *hdev)
{
struct hclge_shared_buf *s_buf = &hdev->s_buf;
struct hclge_rx_com_thrd *req;
struct hclge_desc desc[2];
struct hclge_tc_thrd *tc;
int i, j;
int ret;
for (i = 0; i < 2; i++) {
hclge_cmd_setup_basic_desc(&desc[i],
HCLGE_OPC_RX_COM_THRD_ALLOC, false);
req = (struct hclge_rx_com_thrd *)&desc[i].data;
/* The first descriptor set the NEXT bit to 1 */
if (i == 0)
desc[i].flag |= cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
else
desc[i].flag &= ~cpu_to_le16(HCLGE_CMD_FLAG_NEXT);
for (j = 0; j < HCLGE_TC_NUM_ONE_DESC; j++) {
tc = &s_buf->tc_thrd[i * HCLGE_TC_NUM_ONE_DESC + j];
req->com_thrd[j].high =
cpu_to_le16(tc->high >> HCLGE_BUF_UNIT_S);
req->com_thrd[j].high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(tc->high) <<
HCLGE_RX_PRIV_EN_B);
req->com_thrd[j].low =
cpu_to_le16(tc->low >> HCLGE_BUF_UNIT_S);
req->com_thrd[j].low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(tc->low) <<
HCLGE_RX_PRIV_EN_B);
}
}
/* Send 2 descriptors at one time */
ret = hclge_cmd_send(&hdev->hw, desc, 2);
if (ret) {
dev_err(&hdev->pdev->dev,
"common threshold config cmd failed %d\n", ret);
return ret;
}
return 0;
}
static int hclge_common_wl_config(struct hclge_dev *hdev)
{
struct hclge_shared_buf *buf = &hdev->s_buf;
struct hclge_rx_com_wl *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RX_COM_WL_ALLOC, false);
req = (struct hclge_rx_com_wl *)desc.data;
req->com_wl.high = cpu_to_le16(buf->self.high >> HCLGE_BUF_UNIT_S);
req->com_wl.high |=
cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.high) <<
HCLGE_RX_PRIV_EN_B);
req->com_wl.low = cpu_to_le16(buf->self.low >> HCLGE_BUF_UNIT_S);
req->com_wl.low |=
cpu_to_le16(HCLGE_PRIV_ENABLE(buf->self.low) <<
HCLGE_RX_PRIV_EN_B);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"common waterline config cmd failed %d\n", ret);
return ret;
}
return 0;
}
int hclge_buffer_alloc(struct hclge_dev *hdev)
{
u32 tx_buf_size = HCLGE_DEFAULT_TX_BUF;
int ret;
hdev->priv_buf = devm_kmalloc_array(&hdev->pdev->dev, HCLGE_MAX_TC_NUM,
sizeof(struct hclge_priv_buf),
GFP_KERNEL | __GFP_ZERO);
if (!hdev->priv_buf)
return -ENOMEM;
ret = hclge_tx_buffer_alloc(hdev, tx_buf_size);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not alloc tx buffers %d\n", ret);
return ret;
}
ret = hclge_rx_buffer_calc(hdev, tx_buf_size);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not calc rx priv buffer size for all TCs %d\n",
ret);
return ret;
}
ret = hclge_rx_priv_buf_alloc(hdev);
if (ret) {
dev_err(&hdev->pdev->dev, "could not alloc rx priv buffer %d\n",
ret);
return ret;
}
if (hnae3_dev_dcb_supported(hdev)) {
ret = hclge_rx_priv_wl_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure rx private waterline %d\n",
ret);
return ret;
}
ret = hclge_common_thrd_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure common threshold %d\n",
ret);
return ret;
}
}
ret = hclge_common_wl_config(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not configure common waterline %d\n", ret);
return ret;
}
return 0;
}
static int hclge_init_roce_base_info(struct hclge_vport *vport)
{
struct hnae3_handle *roce = &vport->roce;
struct hnae3_handle *nic = &vport->nic;
roce->rinfo.num_vectors = vport->back->num_roce_msix;
if (vport->back->num_msi_left < vport->roce.rinfo.num_vectors ||
vport->back->num_msi_left == 0)
return -EINVAL;
roce->rinfo.base_vector = vport->back->roce_base_vector;
roce->rinfo.netdev = nic->kinfo.netdev;
roce->rinfo.roce_io_base = vport->back->hw.io_base;
roce->pdev = nic->pdev;
roce->ae_algo = nic->ae_algo;
roce->numa_node_mask = nic->numa_node_mask;
return 0;
}
static int hclge_init_msix(struct hclge_dev *hdev)
{
struct pci_dev *pdev = hdev->pdev;
int ret, i;
hdev->msix_entries = devm_kcalloc(&pdev->dev, hdev->num_msi,
sizeof(struct msix_entry),
GFP_KERNEL);
if (!hdev->msix_entries)
return -ENOMEM;
hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
sizeof(u16), GFP_KERNEL);
if (!hdev->vector_status)
return -ENOMEM;
for (i = 0; i < hdev->num_msi; i++) {
hdev->msix_entries[i].entry = i;
hdev->vector_status[i] = HCLGE_INVALID_VPORT;
}
hdev->num_msi_left = hdev->num_msi;
hdev->base_msi_vector = hdev->pdev->irq;
hdev->roce_base_vector = hdev->base_msi_vector +
HCLGE_ROCE_VECTOR_OFFSET;
ret = pci_enable_msix_range(hdev->pdev, hdev->msix_entries,
hdev->num_msi, hdev->num_msi);
if (ret < 0) {
dev_info(&hdev->pdev->dev,
"MSI-X vector alloc failed: %d\n", ret);
return ret;
}
return 0;
}
static int hclge_init_msi(struct hclge_dev *hdev)
{
struct pci_dev *pdev = hdev->pdev;
int vectors;
int i;
hdev->vector_status = devm_kcalloc(&pdev->dev, hdev->num_msi,
sizeof(u16), GFP_KERNEL);
if (!hdev->vector_status)
return -ENOMEM;
for (i = 0; i < hdev->num_msi; i++)
hdev->vector_status[i] = HCLGE_INVALID_VPORT;
vectors = pci_alloc_irq_vectors(pdev, 1, hdev->num_msi, PCI_IRQ_MSI);
if (vectors < 0) {
dev_err(&pdev->dev, "MSI vectors enable failed %d\n", vectors);
return -EINVAL;
}
hdev->num_msi = vectors;
hdev->num_msi_left = vectors;
hdev->base_msi_vector = pdev->irq;
hdev->roce_base_vector = hdev->base_msi_vector +
HCLGE_ROCE_VECTOR_OFFSET;
return 0;
}
static void hclge_check_speed_dup(struct hclge_dev *hdev, int duplex, int speed)
{
struct hclge_mac *mac = &hdev->hw.mac;
if ((speed == HCLGE_MAC_SPEED_10M) || (speed == HCLGE_MAC_SPEED_100M))
mac->duplex = (u8)duplex;
else
mac->duplex = HCLGE_MAC_FULL;
mac->speed = speed;
}
int hclge_cfg_mac_speed_dup(struct hclge_dev *hdev, int speed, u8 duplex)
{
struct hclge_config_mac_speed_dup *req;
struct hclge_desc desc;
int ret;
req = (struct hclge_config_mac_speed_dup *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_SPEED_DUP, false);
hnae_set_bit(req->speed_dup, HCLGE_CFG_DUPLEX_B, !!duplex);
switch (speed) {
case HCLGE_MAC_SPEED_10M:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 6);
break;
case HCLGE_MAC_SPEED_100M:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 7);
break;
case HCLGE_MAC_SPEED_1G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 0);
break;
case HCLGE_MAC_SPEED_10G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 1);
break;
case HCLGE_MAC_SPEED_25G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 2);
break;
case HCLGE_MAC_SPEED_40G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 3);
break;
case HCLGE_MAC_SPEED_50G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 4);
break;
case HCLGE_MAC_SPEED_100G:
hnae_set_field(req->speed_dup, HCLGE_CFG_SPEED_M,
HCLGE_CFG_SPEED_S, 5);
break;
default:
dev_err(&hdev->pdev->dev, "invalid speed (%d)\n", speed);
return -EINVAL;
}
hnae_set_bit(req->mac_change_fec_en, HCLGE_CFG_MAC_SPEED_CHANGE_EN_B,
1);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"mac speed/duplex config cmd failed %d.\n", ret);
return ret;
}
hclge_check_speed_dup(hdev, duplex, speed);
return 0;
}
static int hclge_cfg_mac_speed_dup_h(struct hnae3_handle *handle, int speed,
u8 duplex)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
return hclge_cfg_mac_speed_dup(hdev, speed, duplex);
}
static int hclge_query_mac_an_speed_dup(struct hclge_dev *hdev, int *speed,
u8 *duplex)
{
struct hclge_query_an_speed_dup *req;
struct hclge_desc desc;
int speed_tmp;
int ret;
req = (struct hclge_query_an_speed_dup *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"mac speed/autoneg/duplex query cmd failed %d\n",
ret);
return ret;
}
*duplex = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_DUPLEX_B);
speed_tmp = hnae_get_field(req->an_syn_dup_speed, HCLGE_QUERY_SPEED_M,
HCLGE_QUERY_SPEED_S);
ret = hclge_parse_speed(speed_tmp, speed);
if (ret) {
dev_err(&hdev->pdev->dev,
"could not parse speed(=%d), %d\n", speed_tmp, ret);
return -EIO;
}
return 0;
}
static int hclge_query_autoneg_result(struct hclge_dev *hdev)
{
struct hclge_mac *mac = &hdev->hw.mac;
struct hclge_query_an_speed_dup *req;
struct hclge_desc desc;
int ret;
req = (struct hclge_query_an_speed_dup *)desc.data;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_AN_RESULT, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"autoneg result query cmd failed %d.\n", ret);
return ret;
}
mac->autoneg = hnae_get_bit(req->an_syn_dup_speed, HCLGE_QUERY_AN_B);
return 0;
}
static int hclge_set_autoneg_en(struct hclge_dev *hdev, bool enable)
{
struct hclge_config_auto_neg *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_CONFIG_AN_MODE, false);
req = (struct hclge_config_auto_neg *)desc.data;
hnae_set_bit(req->cfg_an_cmd_flag, HCLGE_MAC_CFG_AN_EN_B, !!enable);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "auto neg set cmd failed %d.\n",
ret);
return ret;
}
return 0;
}
static int hclge_set_autoneg(struct hnae3_handle *handle, bool enable)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
return hclge_set_autoneg_en(hdev, enable);
}
static int hclge_get_autoneg(struct hnae3_handle *handle)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
hclge_query_autoneg_result(hdev);
return hdev->hw.mac.autoneg;
}
static int hclge_mac_init(struct hclge_dev *hdev)
{
struct hclge_mac *mac = &hdev->hw.mac;
int ret;
ret = hclge_cfg_mac_speed_dup(hdev, hdev->hw.mac.speed, HCLGE_MAC_FULL);
if (ret) {
dev_err(&hdev->pdev->dev,
"Config mac speed dup fail ret=%d\n", ret);
return ret;
}
mac->link = 0;
ret = hclge_mac_mdio_config(hdev);
if (ret) {
dev_warn(&hdev->pdev->dev,
"mdio config fail ret=%d\n", ret);
return ret;
}
/* Initialize the MTA table work mode */
hdev->accept_mta_mc = true;
hdev->enable_mta = true;
hdev->mta_mac_sel_type = HCLGE_MAC_ADDR_47_36;
ret = hclge_set_mta_filter_mode(hdev,
hdev->mta_mac_sel_type,
hdev->enable_mta);
if (ret) {
dev_err(&hdev->pdev->dev, "set mta filter mode failed %d\n",
ret);
return ret;
}
return hclge_cfg_func_mta_filter(hdev, 0, hdev->accept_mta_mc);
}
static void hclge_task_schedule(struct hclge_dev *hdev)
{
if (!test_bit(HCLGE_STATE_DOWN, &hdev->state) &&
!test_bit(HCLGE_STATE_REMOVING, &hdev->state) &&
!test_and_set_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state))
(void)schedule_work(&hdev->service_task);
}
static int hclge_get_mac_link_status(struct hclge_dev *hdev)
{
struct hclge_link_status *req;
struct hclge_desc desc;
int link_status;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_QUERY_LINK_STATUS, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev, "get link status cmd failed %d\n",
ret);
return ret;
}
req = (struct hclge_link_status *)desc.data;
link_status = req->status & HCLGE_LINK_STATUS;
return !!link_status;
}
static int hclge_get_mac_phy_link(struct hclge_dev *hdev)
{
int mac_state;
int link_stat;
mac_state = hclge_get_mac_link_status(hdev);
if (hdev->hw.mac.phydev) {
if (!genphy_read_status(hdev->hw.mac.phydev))
link_stat = mac_state &
hdev->hw.mac.phydev->link;
else
link_stat = 0;
} else {
link_stat = mac_state;
}
return !!link_stat;
}
static void hclge_update_link_status(struct hclge_dev *hdev)
{
struct hnae3_client *client = hdev->nic_client;
struct hnae3_handle *handle;
int state;
int i;
if (!client)
return;
state = hclge_get_mac_phy_link(hdev);
if (state != hdev->hw.mac.link) {
for (i = 0; i < hdev->num_vmdq_vport + 1; i++) {
handle = &hdev->vport[i].nic;
client->ops->link_status_change(handle, state);
}
hdev->hw.mac.link = state;
}
}
static int hclge_update_speed_duplex(struct hclge_dev *hdev)
{
struct hclge_mac mac = hdev->hw.mac;
u8 duplex;
int speed;
int ret;
/* get the speed and duplex as autoneg'result from mac cmd when phy
* doesn't exit.
*/
if (mac.phydev)
return 0;
/* update mac->antoneg. */
ret = hclge_query_autoneg_result(hdev);
if (ret) {
dev_err(&hdev->pdev->dev,
"autoneg result query failed %d\n", ret);
return ret;
}
if (!mac.autoneg)
return 0;
ret = hclge_query_mac_an_speed_dup(hdev, &speed, &duplex);
if (ret) {
dev_err(&hdev->pdev->dev,
"mac autoneg/speed/duplex query failed %d\n", ret);
return ret;
}
if ((mac.speed != speed) || (mac.duplex != duplex)) {
ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
if (ret) {
dev_err(&hdev->pdev->dev,
"mac speed/duplex config failed %d\n", ret);
return ret;
}
}
return 0;
}
static int hclge_update_speed_duplex_h(struct hnae3_handle *handle)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
return hclge_update_speed_duplex(hdev);
}
static int hclge_get_status(struct hnae3_handle *handle)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
hclge_update_link_status(hdev);
return hdev->hw.mac.link;
}
static void hclge_service_timer(unsigned long data)
{
struct hclge_dev *hdev = (struct hclge_dev *)data;
(void)mod_timer(&hdev->service_timer, jiffies + HZ);
hclge_task_schedule(hdev);
}
static void hclge_service_complete(struct hclge_dev *hdev)
{
WARN_ON(!test_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state));
/* Flush memory before next watchdog */
smp_mb__before_atomic();
clear_bit(HCLGE_STATE_SERVICE_SCHED, &hdev->state);
}
static void hclge_service_task(struct work_struct *work)
{
struct hclge_dev *hdev =
container_of(work, struct hclge_dev, service_task);
hclge_update_speed_duplex(hdev);
hclge_update_link_status(hdev);
hclge_update_stats_for_all(hdev);
hclge_service_complete(hdev);
}
static void hclge_disable_sriov(struct hclge_dev *hdev)
{
/* If our VFs are assigned we cannot shut down SR-IOV
* without causing issues, so just leave the hardware
* available but disabled
*/
if (pci_vfs_assigned(hdev->pdev)) {
dev_warn(&hdev->pdev->dev,
"disabling driver while VFs are assigned\n");
return;
}
pci_disable_sriov(hdev->pdev);
}
struct hclge_vport *hclge_get_vport(struct hnae3_handle *handle)
{
/* VF handle has no client */
if (!handle->client)
return container_of(handle, struct hclge_vport, nic);
else if (handle->client->type == HNAE3_CLIENT_ROCE)
return container_of(handle, struct hclge_vport, roce);
else
return container_of(handle, struct hclge_vport, nic);
}
static int hclge_get_vector(struct hnae3_handle *handle, u16 vector_num,
struct hnae3_vector_info *vector_info)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hnae3_vector_info *vector = vector_info;
struct hclge_dev *hdev = vport->back;
int alloc = 0;
int i, j;
vector_num = min(hdev->num_msi_left, vector_num);
for (j = 0; j < vector_num; j++) {
for (i = 1; i < hdev->num_msi; i++) {
if (hdev->vector_status[i] == HCLGE_INVALID_VPORT) {
vector->vector = pci_irq_vector(hdev->pdev, i);
vector->io_addr = hdev->hw.io_base +
HCLGE_VECTOR_REG_BASE +
(i - 1) * HCLGE_VECTOR_REG_OFFSET +
vport->vport_id *
HCLGE_VECTOR_VF_OFFSET;
hdev->vector_status[i] = vport->vport_id;
vector++;
alloc++;
break;
}
}
}
hdev->num_msi_left -= alloc;
hdev->num_msi_used += alloc;
return alloc;
}
static int hclge_get_vector_index(struct hclge_dev *hdev, int vector)
{
int i;
for (i = 0; i < hdev->num_msi; i++) {
if (hdev->msix_entries) {
if (vector == hdev->msix_entries[i].vector)
return i;
} else {
if (vector == (hdev->base_msi_vector + i))
return i;
}
}
return -EINVAL;
}
static u32 hclge_get_rss_key_size(struct hnae3_handle *handle)
{
return HCLGE_RSS_KEY_SIZE;
}
static u32 hclge_get_rss_indir_size(struct hnae3_handle *handle)
{
return HCLGE_RSS_IND_TBL_SIZE;
}
static int hclge_get_rss_algo(struct hclge_dev *hdev)
{
struct hclge_rss_config *req;
struct hclge_desc desc;
int rss_hash_algo;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG, true);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Get link status error, status =%d\n", ret);
return ret;
}
req = (struct hclge_rss_config *)desc.data;
rss_hash_algo = (req->hash_config & HCLGE_RSS_HASH_ALGO_MASK);
if (rss_hash_algo == HCLGE_RSS_HASH_ALGO_TOEPLITZ)
return ETH_RSS_HASH_TOP;
return -EINVAL;
}
static int hclge_set_rss_algo_key(struct hclge_dev *hdev,
const u8 hfunc, const u8 *key)
{
struct hclge_rss_config *req;
struct hclge_desc desc;
int key_offset;
int key_size;
int ret;
req = (struct hclge_rss_config *)desc.data;
for (key_offset = 0; key_offset < 3; key_offset++) {
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_GENERIC_CONFIG,
false);
req->hash_config |= (hfunc & HCLGE_RSS_HASH_ALGO_MASK);
req->hash_config |= (key_offset << HCLGE_RSS_HASH_KEY_OFFSET_B);
if (key_offset == 2)
key_size =
HCLGE_RSS_KEY_SIZE - HCLGE_RSS_HASH_KEY_NUM * 2;
else
key_size = HCLGE_RSS_HASH_KEY_NUM;
memcpy(req->hash_key,
key + key_offset * HCLGE_RSS_HASH_KEY_NUM, key_size);
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Configure RSS config fail, status = %d\n",
ret);
return ret;
}
}
return 0;
}
static int hclge_set_rss_indir_table(struct hclge_dev *hdev, const u32 *indir)
{
struct hclge_rss_indirection_table *req;
struct hclge_desc desc;
int i, j;
int ret;
req = (struct hclge_rss_indirection_table *)desc.data;
for (i = 0; i < HCLGE_RSS_CFG_TBL_NUM; i++) {
hclge_cmd_setup_basic_desc
(&desc, HCLGE_OPC_RSS_INDIR_TABLE, false);
req->start_table_index = i * HCLGE_RSS_CFG_TBL_SIZE;
req->rss_set_bitmap = HCLGE_RSS_SET_BITMAP_MSK;
for (j = 0; j < HCLGE_RSS_CFG_TBL_SIZE; j++)
req->rss_result[j] =
indir[i * HCLGE_RSS_CFG_TBL_SIZE + j];
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Configure rss indir table fail,status = %d\n",
ret);
return ret;
}
}
return 0;
}
static int hclge_set_rss_tc_mode(struct hclge_dev *hdev, u16 *tc_valid,
u16 *tc_size, u16 *tc_offset)
{
struct hclge_rss_tc_mode *req;
struct hclge_desc desc;
int ret;
int i;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_TC_MODE, false);
req = (struct hclge_rss_tc_mode *)desc.data;
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
hnae_set_bit(req->rss_tc_mode[i], HCLGE_RSS_TC_VALID_B,
(tc_valid[i] & 0x1));
hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_SIZE_M,
HCLGE_RSS_TC_SIZE_S, tc_size[i]);
hnae_set_field(req->rss_tc_mode[i], HCLGE_RSS_TC_OFFSET_M,
HCLGE_RSS_TC_OFFSET_S, tc_offset[i]);
}
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Configure rss tc mode fail, status = %d\n", ret);
return ret;
}
return 0;
}
static int hclge_set_rss_input_tuple(struct hclge_dev *hdev)
{
#define HCLGE_RSS_INPUT_TUPLE_OTHER 0xf
#define HCLGE_RSS_INPUT_TUPLE_SCTP 0x1f
struct hclge_rss_input_tuple *req;
struct hclge_desc desc;
int ret;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_RSS_INPUT_TUPLE, false);
req = (struct hclge_rss_input_tuple *)desc.data;
req->ipv4_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
req->ipv4_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
req->ipv4_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
req->ipv4_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
req->ipv6_tcp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
req->ipv6_udp_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
req->ipv6_sctp_en = HCLGE_RSS_INPUT_TUPLE_SCTP;
req->ipv6_fragment_en = HCLGE_RSS_INPUT_TUPLE_OTHER;
ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) {
dev_err(&hdev->pdev->dev,
"Configure rss input fail, status = %d\n", ret);
return ret;
}
return 0;
}
static int hclge_get_rss(struct hnae3_handle *handle, u32 *indir,
u8 *key, u8 *hfunc)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
int i;
/* Get hash algorithm */
if (hfunc)
*hfunc = hclge_get_rss_algo(hdev);
/* Get the RSS Key required by the user */
if (key)
memcpy(key, vport->rss_hash_key, HCLGE_RSS_KEY_SIZE);
/* Get indirect table */
if (indir)
for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
indir[i] = vport->rss_indirection_tbl[i];
return 0;
}
static int hclge_set_rss(struct hnae3_handle *handle, const u32 *indir,
const u8 *key, const u8 hfunc)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
u8 hash_algo;
int ret, i;
/* Set the RSS Hash Key if specififed by the user */
if (key) {
/* Update the shadow RSS key with user specified qids */
memcpy(vport->rss_hash_key, key, HCLGE_RSS_KEY_SIZE);
if (hfunc == ETH_RSS_HASH_TOP ||
hfunc == ETH_RSS_HASH_NO_CHANGE)
hash_algo = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
else
return -EINVAL;
ret = hclge_set_rss_algo_key(hdev, hash_algo, key);
if (ret)
return ret;
}
/* Update the shadow RSS table with user specified qids */
for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++)
vport->rss_indirection_tbl[i] = indir[i];
/* Update the hardware */
ret = hclge_set_rss_indir_table(hdev, indir);
return ret;
}
static int hclge_get_tc_size(struct hnae3_handle *handle)
{
struct hclge_vport *vport = hclge_get_vport(handle);
struct hclge_dev *hdev = vport->back;
return hdev->rss_size_max;
}
static int hclge_rss_init_hw(struct hclge_dev *hdev)
{
const u8 hfunc = HCLGE_RSS_HASH_ALGO_TOEPLITZ;
struct hclge_vport *vport = hdev->vport;
u16 tc_offset[HCLGE_MAX_TC_NUM];
u8 rss_key[HCLGE_RSS_KEY_SIZE];
u16 tc_valid[HCLGE_MAX_TC_NUM];
u16 tc_size[HCLGE_MAX_TC_NUM];
u32 *rss_indir = NULL;
u16 rss_size = 0, roundup_size;
const u8 *key;
int i, ret, j;
rss_indir = kcalloc(HCLGE_RSS_IND_TBL_SIZE, sizeof(u32), GFP_KERNEL);
if (!rss_indir)
return -ENOMEM;
/* Get default RSS key */
netdev_rss_key_fill(rss_key, HCLGE_RSS_KEY_SIZE);
/* Initialize RSS indirect table for each vport */
for (j = 0; j < hdev->num_vmdq_vport + 1; j++) {
for (i = 0; i < HCLGE_RSS_IND_TBL_SIZE; i++) {
vport[j].rss_indirection_tbl[i] =
i % vport[j].alloc_rss_size;
/* vport 0 is for PF */
if (j != 0)
continue;
rss_size = vport[j].alloc_rss_size;
rss_indir[i] = vport[j].rss_indirection_tbl[i];
}
}
ret = hclge_set_rss_indir_table(hdev, rss_indir);
if (ret)
goto err;
key = rss_key;
ret = hclge_set_rss_algo_key(hdev, hfunc, key);
if (ret)
goto err;
ret = hclge_set_rss_input_tuple(hdev);
if (ret)
goto err;
/* Each TC have the same queue size, and tc_size set to hardware is
* the log2 of roundup power of two of rss_size, the acutal queue
* size is limited by indirection table.
*/
if (rss_size > HCLGE_RSS_TC_SIZE_7 || rss_size == 0) {
dev_err(&hdev->pdev->dev,
"Configure rss tc size failed, invalid TC_SIZE = %d\n",
rss_size);
return -EINVAL;
}
roundup_size = roundup_pow_of_two(rss_size);
roundup_size = ilog2(roundup_size);
for (i = 0; i < HCLGE_MAX_TC_NUM; i++) {
tc_valid[i] = 0;
if (!(hdev->hw_tc_map & BIT(i)))
continue;
tc_valid[i] = 1;
tc_size[i] = roundup_size;
tc_offset[i] = rss_size * i;
}
ret = hclge_set_rss_tc_mode(hdev, tc_valid, tc_size, tc_offset);
err:
kfree(rss_indir);
return ret;
}
int hclge_map_vport_ring_to_vector(struct hclge_vport *vport, int vector_id,
struct hnae3_ring_chain_node *ring_chain)
{
struct hclge_dev *hdev = vport->back;
struct hclge_ctrl_vector_chain *req;
struct hnae3_ring_chain_node *node;
struct hclge_desc desc;
int ret;
int i;
hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_ADD_RING_TO_VECTOR, false);
req = (struct hclge_ctrl_vector_chain *)desc.data;
req->int_vector_id = vector_id;
i = 0;
for (node = ring_chain