blob: 42ca5346777ddfc4a5d433daf61146ed428fc424 [file] [log] [blame]
/*******************************************************************************
*
* Copyright (c) 2015-2016 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenFabrics.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*******************************************************************************/
#include "i40iw_osdep.h"
#include "i40iw_register.h"
#include "i40iw_status.h"
#include "i40iw_hmc.h"
#include "i40iw_d.h"
#include "i40iw_type.h"
#include "i40iw_p.h"
#include "i40iw_vf.h"
#include "i40iw_virtchnl.h"
/**
* i40iw_insert_wqe_hdr - write wqe header
* @wqe: cqp wqe for header
* @header: header for the cqp wqe
*/
void i40iw_insert_wqe_hdr(u64 *wqe, u64 header)
{
wmb(); /* make sure WQE is populated before polarity is set */
set_64bit_val(wqe, 24, header);
}
void i40iw_check_cqp_progress(struct i40iw_cqp_timeout *cqp_timeout, struct i40iw_sc_dev *dev)
{
if (cqp_timeout->compl_cqp_cmds != dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]) {
cqp_timeout->compl_cqp_cmds = dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS];
cqp_timeout->count = 0;
} else {
if (dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] != cqp_timeout->compl_cqp_cmds)
cqp_timeout->count++;
}
}
/**
* i40iw_get_cqp_reg_info - get head and tail for cqp using registers
* @cqp: struct for cqp hw
* @val: cqp tail register value
* @tail:wqtail register value
* @error: cqp processing err
*/
static inline void i40iw_get_cqp_reg_info(struct i40iw_sc_cqp *cqp,
u32 *val,
u32 *tail,
u32 *error)
{
if (cqp->dev->is_pf) {
*val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPTAIL);
*tail = RS_32(*val, I40E_PFPE_CQPTAIL_WQTAIL);
*error = RS_32(*val, I40E_PFPE_CQPTAIL_CQP_OP_ERR);
} else {
*val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPTAIL1);
*tail = RS_32(*val, I40E_VFPE_CQPTAIL_WQTAIL);
*error = RS_32(*val, I40E_VFPE_CQPTAIL_CQP_OP_ERR);
}
}
/**
* i40iw_cqp_poll_registers - poll cqp registers
* @cqp: struct for cqp hw
* @tail:wqtail register value
* @count: how many times to try for completion
*/
static enum i40iw_status_code i40iw_cqp_poll_registers(
struct i40iw_sc_cqp *cqp,
u32 tail,
u32 count)
{
u32 i = 0;
u32 newtail, error, val;
while (i < count) {
i++;
i40iw_get_cqp_reg_info(cqp, &val, &newtail, &error);
if (error) {
error = (cqp->dev->is_pf) ?
i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES) :
i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
return I40IW_ERR_CQP_COMPL_ERROR;
}
if (newtail != tail) {
/* SUCCESS */
I40IW_RING_MOVE_TAIL(cqp->sq_ring);
cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
return 0;
}
udelay(I40IW_SLEEP_COUNT);
}
return I40IW_ERR_TIMEOUT;
}
/**
* i40iw_sc_parse_fpm_commit_buf - parse fpm commit buffer
* @buf: ptr to fpm commit buffer
* @info: ptr to i40iw_hmc_obj_info struct
* @sd: number of SDs for HMC objects
*
* parses fpm commit info and copy base value
* of hmc objects in hmc_info
*/
static enum i40iw_status_code i40iw_sc_parse_fpm_commit_buf(
u64 *buf,
struct i40iw_hmc_obj_info *info,
u32 *sd)
{
u64 temp;
u64 size;
u64 base = 0;
u32 i, j;
u32 k = 0;
/* copy base values in obj_info */
for (i = I40IW_HMC_IW_QP, j = 0; i <= I40IW_HMC_IW_PBLE; i++, j += 8) {
if ((i == I40IW_HMC_IW_SRQ) ||
(i == I40IW_HMC_IW_FSIMC) ||
(i == I40IW_HMC_IW_FSIAV)) {
info[i].base = 0;
info[i].cnt = 0;
continue;
}
get_64bit_val(buf, j, &temp);
info[i].base = RS_64_1(temp, 32) * 512;
if (info[i].base > base) {
base = info[i].base;
k = i;
}
if (i == I40IW_HMC_IW_APBVT_ENTRY) {
info[i].cnt = 1;
continue;
}
if (i == I40IW_HMC_IW_QP)
info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
else if (i == I40IW_HMC_IW_CQ)
info[i].cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
else
info[i].cnt = (u32)(temp);
}
size = info[k].cnt * info[k].size + info[k].base;
if (size & 0x1FFFFF)
*sd = (u32)((size >> 21) + 1); /* add 1 for remainder */
else
*sd = (u32)(size >> 21);
return 0;
}
/**
* i40iw_sc_decode_fpm_query() - Decode a 64 bit value into max count and size
* @buf: ptr to fpm query buffer
* @buf_idx: index into buf
* @info: ptr to i40iw_hmc_obj_info struct
* @rsrc_idx: resource index into info
*
* Decode a 64 bit value from fpm query buffer into max count and size
*/
static u64 i40iw_sc_decode_fpm_query(u64 *buf,
u32 buf_idx,
struct i40iw_hmc_obj_info *obj_info,
u32 rsrc_idx)
{
u64 temp;
u32 size;
get_64bit_val(buf, buf_idx, &temp);
obj_info[rsrc_idx].max_cnt = (u32)temp;
size = (u32)RS_64_1(temp, 32);
obj_info[rsrc_idx].size = LS_64_1(1, size);
return temp;
}
/**
* i40iw_sc_parse_fpm_query_buf() - parses fpm query buffer
* @buf: ptr to fpm query buffer
* @info: ptr to i40iw_hmc_obj_info struct
* @hmc_fpm_misc: ptr to fpm data
*
* parses fpm query buffer and copy max_cnt and
* size value of hmc objects in hmc_info
*/
static enum i40iw_status_code i40iw_sc_parse_fpm_query_buf(
u64 *buf,
struct i40iw_hmc_info *hmc_info,
struct i40iw_hmc_fpm_misc *hmc_fpm_misc)
{
struct i40iw_hmc_obj_info *obj_info;
u64 temp;
u32 size;
u16 max_pe_sds;
obj_info = hmc_info->hmc_obj;
get_64bit_val(buf, 0, &temp);
hmc_info->first_sd_index = (u16)RS_64(temp, I40IW_QUERY_FPM_FIRST_PE_SD_INDEX);
max_pe_sds = (u16)RS_64(temp, I40IW_QUERY_FPM_MAX_PE_SDS);
/* Reduce SD count for VFs by 1 to account for PBLE backing page rounding */
if (hmc_info->hmc_fn_id >= I40IW_FIRST_VF_FPM_ID)
max_pe_sds--;
hmc_fpm_misc->max_sds = max_pe_sds;
hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index;
get_64bit_val(buf, 8, &temp);
obj_info[I40IW_HMC_IW_QP].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_QPS);
size = (u32)RS_64_1(temp, 32);
obj_info[I40IW_HMC_IW_QP].size = LS_64_1(1, size);
get_64bit_val(buf, 16, &temp);
obj_info[I40IW_HMC_IW_CQ].max_cnt = (u32)RS_64(temp, I40IW_QUERY_FPM_MAX_CQS);
size = (u32)RS_64_1(temp, 32);
obj_info[I40IW_HMC_IW_CQ].size = LS_64_1(1, size);
i40iw_sc_decode_fpm_query(buf, 32, obj_info, I40IW_HMC_IW_HTE);
i40iw_sc_decode_fpm_query(buf, 40, obj_info, I40IW_HMC_IW_ARP);
obj_info[I40IW_HMC_IW_APBVT_ENTRY].size = 8192;
obj_info[I40IW_HMC_IW_APBVT_ENTRY].max_cnt = 1;
i40iw_sc_decode_fpm_query(buf, 48, obj_info, I40IW_HMC_IW_MR);
i40iw_sc_decode_fpm_query(buf, 56, obj_info, I40IW_HMC_IW_XF);
get_64bit_val(buf, 64, &temp);
obj_info[I40IW_HMC_IW_XFFL].max_cnt = (u32)temp;
obj_info[I40IW_HMC_IW_XFFL].size = 4;
hmc_fpm_misc->xf_block_size = RS_64(temp, I40IW_QUERY_FPM_XFBLOCKSIZE);
if (!hmc_fpm_misc->xf_block_size)
return I40IW_ERR_INVALID_SIZE;
i40iw_sc_decode_fpm_query(buf, 72, obj_info, I40IW_HMC_IW_Q1);
get_64bit_val(buf, 80, &temp);
obj_info[I40IW_HMC_IW_Q1FL].max_cnt = (u32)temp;
obj_info[I40IW_HMC_IW_Q1FL].size = 4;
hmc_fpm_misc->q1_block_size = RS_64(temp, I40IW_QUERY_FPM_Q1BLOCKSIZE);
if (!hmc_fpm_misc->q1_block_size)
return I40IW_ERR_INVALID_SIZE;
i40iw_sc_decode_fpm_query(buf, 88, obj_info, I40IW_HMC_IW_TIMER);
get_64bit_val(buf, 112, &temp);
obj_info[I40IW_HMC_IW_PBLE].max_cnt = (u32)temp;
obj_info[I40IW_HMC_IW_PBLE].size = 8;
get_64bit_val(buf, 120, &temp);
hmc_fpm_misc->max_ceqs = (u8)RS_64(temp, I40IW_QUERY_FPM_MAX_CEQS);
hmc_fpm_misc->ht_multiplier = RS_64(temp, I40IW_QUERY_FPM_HTMULTIPLIER);
hmc_fpm_misc->timer_bucket = RS_64(temp, I40IW_QUERY_FPM_TIMERBUCKET);
return 0;
}
/**
* i40iw_fill_qos_list - Change all unknown qs handles to available ones
* @qs_list: list of qs_handles to be fixed with valid qs_handles
*/
static void i40iw_fill_qos_list(u16 *qs_list)
{
u16 qshandle = qs_list[0];
int i;
for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
if (qs_list[i] == QS_HANDLE_UNKNOWN)
qs_list[i] = qshandle;
else
qshandle = qs_list[i];
}
}
/**
* i40iw_qp_from_entry - Given entry, get to the qp structure
* @entry: Points to list of qp structure
*/
static struct i40iw_sc_qp *i40iw_qp_from_entry(struct list_head *entry)
{
if (!entry)
return NULL;
return (struct i40iw_sc_qp *)((char *)entry - offsetof(struct i40iw_sc_qp, list));
}
/**
* i40iw_get_qp - get the next qp from the list given current qp
* @head: Listhead of qp's
* @qp: current qp
*/
static struct i40iw_sc_qp *i40iw_get_qp(struct list_head *head, struct i40iw_sc_qp *qp)
{
struct list_head *entry = NULL;
struct list_head *lastentry;
if (list_empty(head))
return NULL;
if (!qp) {
entry = head->next;
} else {
lastentry = &qp->list;
entry = (lastentry != head) ? lastentry->next : NULL;
}
return i40iw_qp_from_entry(entry);
}
/**
* i40iw_change_l2params - given the new l2 parameters, change all qp
* @vsi: pointer to the vsi structure
* @l2params: New paramaters from l2
*/
void i40iw_change_l2params(struct i40iw_sc_vsi *vsi, struct i40iw_l2params *l2params)
{
struct i40iw_sc_dev *dev = vsi->dev;
struct i40iw_sc_qp *qp = NULL;
bool qs_handle_change = false;
unsigned long flags;
u16 qs_handle;
int i;
vsi->mss = l2params->mss;
i40iw_fill_qos_list(l2params->qs_handle_list);
for (i = 0; i < I40IW_MAX_USER_PRIORITY; i++) {
qs_handle = l2params->qs_handle_list[i];
if (vsi->qos[i].qs_handle != qs_handle)
qs_handle_change = true;
spin_lock_irqsave(&vsi->qos[i].lock, flags);
qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
while (qp) {
if (qs_handle_change) {
qp->qs_handle = qs_handle;
/* issue cqp suspend command */
i40iw_qp_suspend_resume(dev, qp, true);
}
qp = i40iw_get_qp(&vsi->qos[i].qplist, qp);
}
spin_unlock_irqrestore(&vsi->qos[i].lock, flags);
vsi->qos[i].qs_handle = qs_handle;
}
}
/**
* i40iw_qp_rem_qos - remove qp from qos lists during destroy qp
* @qp: qp to be removed from qos
*/
static void i40iw_qp_rem_qos(struct i40iw_sc_qp *qp)
{
struct i40iw_sc_vsi *vsi = qp->vsi;
unsigned long flags;
if (!qp->on_qoslist)
return;
spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
list_del(&qp->list);
spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
}
/**
* i40iw_qp_add_qos - called during setctx fot qp to be added to qos
* @qp: qp to be added to qos
*/
void i40iw_qp_add_qos(struct i40iw_sc_qp *qp)
{
struct i40iw_sc_vsi *vsi = qp->vsi;
unsigned long flags;
if (qp->on_qoslist)
return;
spin_lock_irqsave(&vsi->qos[qp->user_pri].lock, flags);
qp->qs_handle = vsi->qos[qp->user_pri].qs_handle;
list_add(&qp->list, &vsi->qos[qp->user_pri].qplist);
qp->on_qoslist = true;
spin_unlock_irqrestore(&vsi->qos[qp->user_pri].lock, flags);
}
/**
* i40iw_sc_pd_init - initialize sc pd struct
* @dev: sc device struct
* @pd: sc pd ptr
* @pd_id: pd_id for allocated pd
* @abi_ver: ABI version from user context, -1 if not valid
*/
static void i40iw_sc_pd_init(struct i40iw_sc_dev *dev,
struct i40iw_sc_pd *pd,
u16 pd_id,
int abi_ver)
{
pd->size = sizeof(*pd);
pd->pd_id = pd_id;
pd->abi_ver = abi_ver;
pd->dev = dev;
}
/**
* i40iw_get_encoded_wqe_size - given wq size, returns hardware encoded size
* @wqsize: size of the wq (sq, rq, srq) to encoded_size
* @cqpsq: encoded size for sq for cqp as its encoded size is 1+ other wq's
*/
u8 i40iw_get_encoded_wqe_size(u32 wqsize, bool cqpsq)
{
u8 encoded_size = 0;
/* cqp sq's hw coded value starts from 1 for size of 4
* while it starts from 0 for qp' wq's.
*/
if (cqpsq)
encoded_size = 1;
wqsize >>= 2;
while (wqsize >>= 1)
encoded_size++;
return encoded_size;
}
/**
* i40iw_sc_cqp_init - Initialize buffers for a control Queue Pair
* @cqp: IWARP control queue pair pointer
* @info: IWARP control queue pair init info pointer
*
* Initializes the object and context buffers for a control Queue Pair.
*/
static enum i40iw_status_code i40iw_sc_cqp_init(struct i40iw_sc_cqp *cqp,
struct i40iw_cqp_init_info *info)
{
u8 hw_sq_size;
if ((info->sq_size > I40IW_CQP_SW_SQSIZE_2048) ||
(info->sq_size < I40IW_CQP_SW_SQSIZE_4) ||
((info->sq_size & (info->sq_size - 1))))
return I40IW_ERR_INVALID_SIZE;
hw_sq_size = i40iw_get_encoded_wqe_size(info->sq_size, true);
cqp->size = sizeof(*cqp);
cqp->sq_size = info->sq_size;
cqp->hw_sq_size = hw_sq_size;
cqp->sq_base = info->sq;
cqp->host_ctx = info->host_ctx;
cqp->sq_pa = info->sq_pa;
cqp->host_ctx_pa = info->host_ctx_pa;
cqp->dev = info->dev;
cqp->struct_ver = info->struct_ver;
cqp->scratch_array = info->scratch_array;
cqp->polarity = 0;
cqp->en_datacenter_tcp = info->en_datacenter_tcp;
cqp->enabled_vf_count = info->enabled_vf_count;
cqp->hmc_profile = info->hmc_profile;
info->dev->cqp = cqp;
I40IW_RING_INIT(cqp->sq_ring, cqp->sq_size);
cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS] = 0;
cqp->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS] = 0;
i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
"%s: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%llxh] cqp[%p] polarity[x%04X]\n",
__func__, cqp->sq_size, cqp->hw_sq_size,
cqp->sq_base, cqp->sq_pa, cqp, cqp->polarity);
return 0;
}
/**
* i40iw_sc_cqp_create - create cqp during bringup
* @cqp: struct for cqp hw
* @maj_err: If error, major err number
* @min_err: If error, minor err number
*/
static enum i40iw_status_code i40iw_sc_cqp_create(struct i40iw_sc_cqp *cqp,
u16 *maj_err,
u16 *min_err)
{
u64 temp;
u32 cnt = 0, p1, p2, val = 0, err_code;
enum i40iw_status_code ret_code;
*maj_err = 0;
*min_err = 0;
ret_code = i40iw_allocate_dma_mem(cqp->dev->hw,
&cqp->sdbuf,
128,
I40IW_SD_BUF_ALIGNMENT);
if (ret_code)
goto exit;
temp = LS_64(cqp->hw_sq_size, I40IW_CQPHC_SQSIZE) |
LS_64(cqp->struct_ver, I40IW_CQPHC_SVER);
set_64bit_val(cqp->host_ctx, 0, temp);
set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa);
temp = LS_64(cqp->enabled_vf_count, I40IW_CQPHC_ENABLED_VFS) |
LS_64(cqp->hmc_profile, I40IW_CQPHC_HMC_PROFILE);
set_64bit_val(cqp->host_ctx, 16, temp);
set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp);
set_64bit_val(cqp->host_ctx, 32, 0);
set_64bit_val(cqp->host_ctx, 40, 0);
set_64bit_val(cqp->host_ctx, 48, 0);
set_64bit_val(cqp->host_ctx, 56, 0);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQP_HOST_CTX",
cqp->host_ctx, I40IW_CQP_CTX_SIZE * 8);
p1 = RS_32_1(cqp->host_ctx_pa, 32);
p2 = (u32)cqp->host_ctx_pa;
if (cqp->dev->is_pf) {
i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, p1);
i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, p2);
} else {
i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, p1);
i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, p2);
}
do {
if (cnt++ > I40IW_DONE_COUNT) {
i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
ret_code = I40IW_ERR_TIMEOUT;
/*
* read PFPE_CQPERRORCODES register to get the minor
* and major error code
*/
if (cqp->dev->is_pf)
err_code = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CQPERRCODES);
else
err_code = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CQPERRCODES1);
*min_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MINOR_CODE);
*maj_err = RS_32(err_code, I40E_PFPE_CQPERRCODES_CQP_MAJOR_CODE);
goto exit;
}
udelay(I40IW_SLEEP_COUNT);
if (cqp->dev->is_pf)
val = i40iw_rd32(cqp->dev->hw, I40E_PFPE_CCQPSTATUS);
else
val = i40iw_rd32(cqp->dev->hw, I40E_VFPE_CCQPSTATUS1);
} while (!val);
exit:
if (!ret_code)
cqp->process_cqp_sds = i40iw_update_sds_noccq;
return ret_code;
}
/**
* i40iw_sc_cqp_post_sq - post of cqp's sq
* @cqp: struct for cqp hw
*/
void i40iw_sc_cqp_post_sq(struct i40iw_sc_cqp *cqp)
{
if (cqp->dev->is_pf)
i40iw_wr32(cqp->dev->hw, I40E_PFPE_CQPDB, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
else
i40iw_wr32(cqp->dev->hw, I40E_VFPE_CQPDB1, I40IW_RING_GETCURRENT_HEAD(cqp->sq_ring));
i40iw_debug(cqp->dev,
I40IW_DEBUG_WQE,
"%s: HEAD_TAIL[%04d,%04d,%04d]\n",
__func__,
cqp->sq_ring.head,
cqp->sq_ring.tail,
cqp->sq_ring.size);
}
/**
* i40iw_sc_cqp_get_next_send_wqe - get next wqe on cqp sq
* @cqp: struct for cqp hw
* @wqe_idx: we index of cqp ring
*/
u64 *i40iw_sc_cqp_get_next_send_wqe(struct i40iw_sc_cqp *cqp, u64 scratch)
{
u64 *wqe = NULL;
u32 wqe_idx;
enum i40iw_status_code ret_code;
if (I40IW_RING_FULL_ERR(cqp->sq_ring)) {
i40iw_debug(cqp->dev,
I40IW_DEBUG_WQE,
"%s: ring is full head %x tail %x size %x\n",
__func__,
cqp->sq_ring.head,
cqp->sq_ring.tail,
cqp->sq_ring.size);
return NULL;
}
I40IW_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, wqe_idx, ret_code);
cqp->dev->cqp_cmd_stats[OP_REQUESTED_COMMANDS]++;
if (ret_code)
return NULL;
if (!wqe_idx)
cqp->polarity = !cqp->polarity;
wqe = cqp->sq_base[wqe_idx].elem;
cqp->scratch_array[wqe_idx] = scratch;
I40IW_CQP_INIT_WQE(wqe);
return wqe;
}
/**
* i40iw_sc_cqp_destroy - destroy cqp during close
* @cqp: struct for cqp hw
*/
static enum i40iw_status_code i40iw_sc_cqp_destroy(struct i40iw_sc_cqp *cqp)
{
u32 cnt = 0, val = 1;
enum i40iw_status_code ret_code = 0;
u32 cqpstat_addr;
if (cqp->dev->is_pf) {
i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPHIGH, 0);
i40iw_wr32(cqp->dev->hw, I40E_PFPE_CCQPLOW, 0);
cqpstat_addr = I40E_PFPE_CCQPSTATUS;
} else {
i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPHIGH1, 0);
i40iw_wr32(cqp->dev->hw, I40E_VFPE_CCQPLOW1, 0);
cqpstat_addr = I40E_VFPE_CCQPSTATUS1;
}
do {
if (cnt++ > I40IW_DONE_COUNT) {
ret_code = I40IW_ERR_TIMEOUT;
break;
}
udelay(I40IW_SLEEP_COUNT);
val = i40iw_rd32(cqp->dev->hw, cqpstat_addr);
} while (val);
i40iw_free_dma_mem(cqp->dev->hw, &cqp->sdbuf);
return ret_code;
}
/**
* i40iw_sc_ccq_arm - enable intr for control cq
* @ccq: ccq sc struct
*/
static void i40iw_sc_ccq_arm(struct i40iw_sc_cq *ccq)
{
u64 temp_val;
u16 sw_cq_sel;
u8 arm_next_se;
u8 arm_seq_num;
/* write to cq doorbell shadow area */
/* arm next se should always be zero */
get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val);
sw_cq_sel = (u16)RS_64(temp_val, I40IW_CQ_DBSA_SW_CQ_SELECT);
arm_next_se = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_NEXT_SE);
arm_seq_num = (u8)RS_64(temp_val, I40IW_CQ_DBSA_ARM_SEQ_NUM);
arm_seq_num++;
temp_val = LS_64(arm_seq_num, I40IW_CQ_DBSA_ARM_SEQ_NUM) |
LS_64(sw_cq_sel, I40IW_CQ_DBSA_SW_CQ_SELECT) |
LS_64(arm_next_se, I40IW_CQ_DBSA_ARM_NEXT_SE) |
LS_64(1, I40IW_CQ_DBSA_ARM_NEXT);
set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val);
wmb(); /* make sure shadow area is updated before arming */
if (ccq->dev->is_pf)
i40iw_wr32(ccq->dev->hw, I40E_PFPE_CQARM, ccq->cq_uk.cq_id);
else
i40iw_wr32(ccq->dev->hw, I40E_VFPE_CQARM1, ccq->cq_uk.cq_id);
}
/**
* i40iw_sc_ccq_get_cqe_info - get ccq's cq entry
* @ccq: ccq sc struct
* @info: completion q entry to return
*/
static enum i40iw_status_code i40iw_sc_ccq_get_cqe_info(
struct i40iw_sc_cq *ccq,
struct i40iw_ccq_cqe_info *info)
{
u64 qp_ctx, temp, temp1;
u64 *cqe;
struct i40iw_sc_cqp *cqp;
u32 wqe_idx;
u8 polarity;
enum i40iw_status_code ret_code = 0;
if (ccq->cq_uk.avoid_mem_cflct)
cqe = (u64 *)I40IW_GET_CURRENT_EXTENDED_CQ_ELEMENT(&ccq->cq_uk);
else
cqe = (u64 *)I40IW_GET_CURRENT_CQ_ELEMENT(&ccq->cq_uk);
get_64bit_val(cqe, 24, &temp);
polarity = (u8)RS_64(temp, I40IW_CQ_VALID);
if (polarity != ccq->cq_uk.polarity)
return I40IW_ERR_QUEUE_EMPTY;
get_64bit_val(cqe, 8, &qp_ctx);
cqp = (struct i40iw_sc_cqp *)(unsigned long)qp_ctx;
info->error = (bool)RS_64(temp, I40IW_CQ_ERROR);
info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
if (info->error) {
info->maj_err_code = (u16)RS_64(temp, I40IW_CQ_MAJERR);
info->min_err_code = (u16)RS_64(temp, I40IW_CQ_MINERR);
}
wqe_idx = (u32)RS_64(temp, I40IW_CQ_WQEIDX);
info->scratch = cqp->scratch_array[wqe_idx];
get_64bit_val(cqe, 16, &temp1);
info->op_ret_val = (u32)RS_64(temp1, I40IW_CCQ_OPRETVAL);
get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1);
info->op_code = (u8)RS_64(temp1, I40IW_CQPSQ_OPCODE);
info->cqp = cqp;
/* move the head for cq */
I40IW_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code);
if (I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring) == 0)
ccq->cq_uk.polarity ^= 1;
/* update cq tail in cq shadow memory also */
I40IW_RING_MOVE_TAIL(ccq->cq_uk.cq_ring);
set_64bit_val(ccq->cq_uk.shadow_area,
0,
I40IW_RING_GETCURRENT_HEAD(ccq->cq_uk.cq_ring));
wmb(); /* write shadow area before tail */
I40IW_RING_MOVE_TAIL(cqp->sq_ring);
ccq->dev->cqp_cmd_stats[OP_COMPLETED_COMMANDS]++;
return ret_code;
}
/**
* i40iw_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ
* @cqp: struct for cqp hw
* @op_code: cqp opcode for completion
* @info: completion q entry to return
*/
static enum i40iw_status_code i40iw_sc_poll_for_cqp_op_done(
struct i40iw_sc_cqp *cqp,
u8 op_code,
struct i40iw_ccq_cqe_info *compl_info)
{
struct i40iw_ccq_cqe_info info;
struct i40iw_sc_cq *ccq;
enum i40iw_status_code ret_code = 0;
u32 cnt = 0;
memset(&info, 0, sizeof(info));
ccq = cqp->dev->ccq;
while (1) {
if (cnt++ > I40IW_DONE_COUNT)
return I40IW_ERR_TIMEOUT;
if (i40iw_sc_ccq_get_cqe_info(ccq, &info)) {
udelay(I40IW_SLEEP_COUNT);
continue;
}
if (info.error) {
ret_code = I40IW_ERR_CQP_COMPL_ERROR;
break;
}
/* check if opcode is cq create */
if (op_code != info.op_code) {
i40iw_debug(cqp->dev, I40IW_DEBUG_WQE,
"%s: opcode mismatch for my op code 0x%x, returned opcode %x\n",
__func__, op_code, info.op_code);
}
/* success, exit out of the loop */
if (op_code == info.op_code)
break;
}
if (compl_info)
memcpy(compl_info, &info, sizeof(*compl_info));
return ret_code;
}
/**
* i40iw_sc_manage_push_page - Handle push page
* @cqp: struct for cqp hw
* @info: push page info
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_manage_push_page(
struct i40iw_sc_cqp *cqp,
struct i40iw_cqp_manage_push_page_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 header;
if (info->push_idx >= I40IW_MAX_PUSH_PAGE_COUNT)
return I40IW_ERR_INVALID_PUSH_PAGE_INDEX;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, info->qs_handle);
header = LS_64(info->push_idx, I40IW_CQPSQ_MPP_PPIDX) |
LS_64(I40IW_CQP_OP_MANAGE_PUSH_PAGES, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
LS_64(info->free_page, I40IW_CQPSQ_MPP_FREE_PAGE);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_PUSH_PAGES WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_manage_hmc_pm_func_table - manage of function table
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @vf_index: vf index for cqp
* @free_pm_fcn: function number
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u8 vf_index,
bool free_pm_fcn,
bool post_sq)
{
u64 *wqe;
u64 header;
if (vf_index >= I40IW_MAX_VF_PER_PF)
return I40IW_ERR_INVALID_VF_ID;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = LS_64(vf_index, I40IW_CQPSQ_MHMC_VFIDX) |
LS_64(I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, I40IW_CQPSQ_OPCODE) |
LS_64(free_pm_fcn, I40IW_CQPSQ_MHMC_FREEPMFN) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_set_hmc_resource_profile - cqp wqe for hmc profile
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @hmc_profile_type: type of profile to set
* @vf_num: vf number for profile
* @post_sq: flag for cqp db to ring
* @poll_registers: flag to poll register for cqp completion
*/
static enum i40iw_status_code i40iw_sc_set_hmc_resource_profile(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u8 hmc_profile_type,
u8 vf_num, bool post_sq,
bool poll_registers)
{
u64 *wqe;
u64 header;
u32 val, tail, error;
enum i40iw_status_code ret_code = 0;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16,
(LS_64(hmc_profile_type, I40IW_CQPSQ_SHMCRP_HMC_PROFILE) |
LS_64(vf_num, I40IW_CQPSQ_SHMCRP_VFNUM)));
header = LS_64(I40IW_CQP_OP_SET_HMC_RESOURCE_PROFILE, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_HMC_PM_FUNC_TABLE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
if (error)
return I40IW_ERR_CQP_COMPL_ERROR;
if (post_sq) {
i40iw_sc_cqp_post_sq(cqp);
if (poll_registers)
ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000000);
else
ret_code = i40iw_sc_poll_for_cqp_op_done(cqp,
I40IW_CQP_OP_SHMC_PAGES_ALLOCATED,
NULL);
}
return ret_code;
}
/**
* i40iw_sc_manage_hmc_pm_func_table_done - wait for cqp wqe completion for function table
* @cqp: struct for cqp hw
*/
static enum i40iw_status_code i40iw_sc_manage_hmc_pm_func_table_done(struct i40iw_sc_cqp *cqp)
{
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE, NULL);
}
/**
* i40iw_sc_commit_fpm_values_done - wait for cqp eqe completion for fpm commit
* @cqp: struct for cqp hw
*/
static enum i40iw_status_code i40iw_sc_commit_fpm_values_done(struct i40iw_sc_cqp *cqp)
{
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_COMMIT_FPM_VALUES, NULL);
}
/**
* i40iw_sc_commit_fpm_values - cqp wqe for commit fpm values
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @hmc_fn_id: hmc function id
* @commit_fpm_mem; Memory for fpm values
* @post_sq: flag for cqp db to ring
* @wait_type: poll ccq or cqp registers for cqp completion
*/
static enum i40iw_status_code i40iw_sc_commit_fpm_values(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u8 hmc_fn_id,
struct i40iw_dma_mem *commit_fpm_mem,
bool post_sq,
u8 wait_type)
{
u64 *wqe;
u64 header;
u32 tail, val, error;
enum i40iw_status_code ret_code = 0;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, hmc_fn_id);
set_64bit_val(wqe, 32, commit_fpm_mem->pa);
header = LS_64(I40IW_CQP_OP_COMMIT_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "COMMIT_FPM_VALUES WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
if (error)
return I40IW_ERR_CQP_COMPL_ERROR;
if (post_sq) {
i40iw_sc_cqp_post_sq(cqp);
if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
ret_code = i40iw_sc_commit_fpm_values_done(cqp);
}
return ret_code;
}
/**
* i40iw_sc_query_fpm_values_done - poll for cqp wqe completion for query fpm
* @cqp: struct for cqp hw
*/
static enum i40iw_status_code i40iw_sc_query_fpm_values_done(struct i40iw_sc_cqp *cqp)
{
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_QUERY_FPM_VALUES, NULL);
}
/**
* i40iw_sc_query_fpm_values - cqp wqe query fpm values
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @hmc_fn_id: hmc function id
* @query_fpm_mem: memory for return fpm values
* @post_sq: flag for cqp db to ring
* @wait_type: poll ccq or cqp registers for cqp completion
*/
static enum i40iw_status_code i40iw_sc_query_fpm_values(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u8 hmc_fn_id,
struct i40iw_dma_mem *query_fpm_mem,
bool post_sq,
u8 wait_type)
{
u64 *wqe;
u64 header;
u32 tail, val, error;
enum i40iw_status_code ret_code = 0;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, hmc_fn_id);
set_64bit_val(wqe, 32, query_fpm_mem->pa);
header = LS_64(I40IW_CQP_OP_QUERY_FPM_VALUES, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_FPM WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
/* read the tail from CQP_TAIL register */
i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
if (error)
return I40IW_ERR_CQP_COMPL_ERROR;
if (post_sq) {
i40iw_sc_cqp_post_sq(cqp);
if (wait_type == I40IW_CQP_WAIT_POLL_REGS)
ret_code = i40iw_cqp_poll_registers(cqp, tail, I40IW_DONE_COUNT);
else if (wait_type == I40IW_CQP_WAIT_POLL_CQ)
ret_code = i40iw_sc_query_fpm_values_done(cqp);
}
return ret_code;
}
/**
* i40iw_sc_add_arp_cache_entry - cqp wqe add arp cache entry
* @cqp: struct for cqp hw
* @info: arp entry information
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_add_arp_cache_entry(
struct i40iw_sc_cqp *cqp,
struct i40iw_add_arp_cache_entry_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 temp, header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 8, info->reach_max);
temp = info->mac_addr[5] |
LS_64_1(info->mac_addr[4], 8) |
LS_64_1(info->mac_addr[3], 16) |
LS_64_1(info->mac_addr[2], 24) |
LS_64_1(info->mac_addr[1], 32) |
LS_64_1(info->mac_addr[0], 40);
set_64bit_val(wqe, 16, temp);
header = info->arp_index |
LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
LS_64((info->permanent ? 1 : 0), I40IW_CQPSQ_MAT_PERMANENT) |
LS_64(1, I40IW_CQPSQ_MAT_ENTRYVALID) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_ENTRY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_del_arp_cache_entry - dele arp cache entry
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @arp_index: arp index to delete arp entry
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_del_arp_cache_entry(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u16 arp_index,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = arp_index |
LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ARP_CACHE_DEL_ENTRY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_query_arp_cache_entry - cqp wqe to query arp and arp index
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @arp_index: arp index to delete arp entry
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_query_arp_cache_entry(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u16 arp_index,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = arp_index |
LS_64(I40IW_CQP_OP_MANAGE_ARP, I40IW_CQPSQ_OPCODE) |
LS_64(1, I40IW_CQPSQ_MAT_QUERY) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QUERY_ARP_CACHE_ENTRY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_manage_apbvt_entry - for adding and deleting apbvt entries
* @cqp: struct for cqp hw
* @info: info for apbvt entry to add or delete
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_manage_apbvt_entry(
struct i40iw_sc_cqp *cqp,
struct i40iw_apbvt_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, info->port);
header = LS_64(I40IW_CQP_OP_MANAGE_APBVT, I40IW_CQPSQ_OPCODE) |
LS_64(info->add, I40IW_CQPSQ_MAPT_ADDPORT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_APBVT WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_manage_qhash_table_entry - manage quad hash entries
* @cqp: struct for cqp hw
* @info: info for quad hash to manage
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*
* This is called before connection establishment is started. For passive connections, when
* listener is created, it will call with entry type of I40IW_QHASH_TYPE_TCP_SYN with local
* ip address and tcp port. When SYN is received (passive connections) or
* sent (active connections), this routine is called with entry type of
* I40IW_QHASH_TYPE_TCP_ESTABLISHED and quad is passed in info.
*
* When iwarp connection is done and its state moves to RTS, the quad hash entry in
* the hardware will point to iwarp's qp number and requires no calls from the driver.
*/
static enum i40iw_status_code i40iw_sc_manage_qhash_table_entry(
struct i40iw_sc_cqp *cqp,
struct i40iw_qhash_table_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 qw1 = 0;
u64 qw2 = 0;
u64 temp;
struct i40iw_sc_vsi *vsi = info->vsi;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
temp = info->mac_addr[5] |
LS_64_1(info->mac_addr[4], 8) |
LS_64_1(info->mac_addr[3], 16) |
LS_64_1(info->mac_addr[2], 24) |
LS_64_1(info->mac_addr[1], 32) |
LS_64_1(info->mac_addr[0], 40);
set_64bit_val(wqe, 0, temp);
qw1 = LS_64(info->qp_num, I40IW_CQPSQ_QHASH_QPN) |
LS_64(info->dest_port, I40IW_CQPSQ_QHASH_DEST_PORT);
if (info->ipv4_valid) {
set_64bit_val(wqe,
48,
LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
} else {
set_64bit_val(wqe,
56,
LS_64(info->dest_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
LS_64(info->dest_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
set_64bit_val(wqe,
48,
LS_64(info->dest_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
LS_64(info->dest_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
}
qw2 = LS_64(vsi->qos[info->user_pri].qs_handle, I40IW_CQPSQ_QHASH_QS_HANDLE);
if (info->vlan_valid)
qw2 |= LS_64(info->vlan_id, I40IW_CQPSQ_QHASH_VLANID);
set_64bit_val(wqe, 16, qw2);
if (info->entry_type == I40IW_QHASH_TYPE_TCP_ESTABLISHED) {
qw1 |= LS_64(info->src_port, I40IW_CQPSQ_QHASH_SRC_PORT);
if (!info->ipv4_valid) {
set_64bit_val(wqe,
40,
LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR0) |
LS_64(info->src_ip[1], I40IW_CQPSQ_QHASH_ADDR1));
set_64bit_val(wqe,
32,
LS_64(info->src_ip[2], I40IW_CQPSQ_QHASH_ADDR2) |
LS_64(info->src_ip[3], I40IW_CQPSQ_QHASH_ADDR3));
} else {
set_64bit_val(wqe,
32,
LS_64(info->src_ip[0], I40IW_CQPSQ_QHASH_ADDR3));
}
}
set_64bit_val(wqe, 8, qw1);
temp = LS_64(cqp->polarity, I40IW_CQPSQ_QHASH_WQEVALID) |
LS_64(I40IW_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY, I40IW_CQPSQ_QHASH_OPCODE) |
LS_64(info->manage, I40IW_CQPSQ_QHASH_MANAGE) |
LS_64(info->ipv4_valid, I40IW_CQPSQ_QHASH_IPV4VALID) |
LS_64(info->vlan_valid, I40IW_CQPSQ_QHASH_VLANVALID) |
LS_64(info->entry_type, I40IW_CQPSQ_QHASH_ENTRYTYPE);
i40iw_insert_wqe_hdr(wqe, temp);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "MANAGE_QHASH WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_alloc_local_mac_ipaddr_entry - cqp wqe for loc mac entry
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_alloc_local_mac_ipaddr_entry(
struct i40iw_sc_cqp *cqp,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = LS_64(I40IW_CQP_OP_ALLOCATE_LOC_MAC_IP_TABLE_ENTRY, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ALLOCATE_LOCAL_MAC_IPADDR WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_add_local_mac_ipaddr_entry - add mac enry
* @cqp: struct for cqp hw
* @info:mac addr info
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_add_local_mac_ipaddr_entry(
struct i40iw_sc_cqp *cqp,
struct i40iw_local_mac_ipaddr_entry_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 temp, header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
temp = info->mac_addr[5] |
LS_64_1(info->mac_addr[4], 8) |
LS_64_1(info->mac_addr[3], 16) |
LS_64_1(info->mac_addr[2], 24) |
LS_64_1(info->mac_addr[1], 32) |
LS_64_1(info->mac_addr[0], 40);
set_64bit_val(wqe, 32, temp);
header = LS_64(info->entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "ADD_LOCAL_MAC_IPADDR WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_del_local_mac_ipaddr_entry - cqp wqe to dele local mac
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @entry_idx: index of mac entry
* @ ignore_ref_count: to force mac adde delete
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_del_local_mac_ipaddr_entry(
struct i40iw_sc_cqp *cqp,
u64 scratch,
u8 entry_idx,
u8 ignore_ref_count,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = LS_64(entry_idx, I40IW_CQPSQ_MLIPA_IPTABLEIDX) |
LS_64(I40IW_CQP_OP_MANAGE_LOC_MAC_IP_TABLE, I40IW_CQPSQ_OPCODE) |
LS_64(1, I40IW_CQPSQ_MLIPA_FREEENTRY) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID) |
LS_64(ignore_ref_count, I40IW_CQPSQ_MLIPA_IGNORE_REF_CNT);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "DEL_LOCAL_MAC_IPADDR WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_cqp_nop - send a nop wqe
* @cqp: struct for cqp hw
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_cqp_nop(struct i40iw_sc_cqp *cqp,
u64 scratch,
bool post_sq)
{
u64 *wqe;
u64 header;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
header = LS_64(I40IW_CQP_OP_NOP, I40IW_CQPSQ_OPCODE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "NOP WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_ceq_init - initialize ceq
* @ceq: ceq sc structure
* @info: ceq initialization info
*/
static enum i40iw_status_code i40iw_sc_ceq_init(struct i40iw_sc_ceq *ceq,
struct i40iw_ceq_init_info *info)
{
u32 pble_obj_cnt;
if ((info->elem_cnt < I40IW_MIN_CEQ_ENTRIES) ||
(info->elem_cnt > I40IW_MAX_CEQ_ENTRIES))
return I40IW_ERR_INVALID_SIZE;
if (info->ceq_id >= I40IW_MAX_CEQID)
return I40IW_ERR_INVALID_CEQ_ID;
pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
return I40IW_ERR_INVALID_PBLE_INDEX;
ceq->size = sizeof(*ceq);
ceq->ceqe_base = (struct i40iw_ceqe *)info->ceqe_base;
ceq->ceq_id = info->ceq_id;
ceq->dev = info->dev;
ceq->elem_cnt = info->elem_cnt;
ceq->ceq_elem_pa = info->ceqe_pa;
ceq->virtual_map = info->virtual_map;
ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0);
ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0);
ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL);
ceq->tph_en = info->tph_en;
ceq->tph_val = info->tph_val;
ceq->polarity = 1;
I40IW_RING_INIT(ceq->ceq_ring, ceq->elem_cnt);
ceq->dev->ceq[info->ceq_id] = ceq;
return 0;
}
/**
* i40iw_sc_ceq_create - create ceq wqe
* @ceq: ceq sc structure
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_ceq_create(struct i40iw_sc_ceq *ceq,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
cqp = ceq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, ceq->elem_cnt);
set_64bit_val(wqe, 32, (ceq->virtual_map ? 0 : ceq->ceq_elem_pa));
set_64bit_val(wqe, 48, (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0));
set_64bit_val(wqe, 56, LS_64(ceq->tph_val, I40IW_CQPSQ_TPHVAL));
header = ceq->ceq_id |
LS_64(I40IW_CQP_OP_CREATE_CEQ, I40IW_CQPSQ_OPCODE) |
LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_CREATE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_cceq_create_done - poll for control ceq wqe to complete
* @ceq: ceq sc structure
*/
static enum i40iw_status_code i40iw_sc_cceq_create_done(struct i40iw_sc_ceq *ceq)
{
struct i40iw_sc_cqp *cqp;
cqp = ceq->dev->cqp;
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CEQ, NULL);
}
/**
* i40iw_sc_cceq_destroy_done - poll for destroy cceq to complete
* @ceq: ceq sc structure
*/
static enum i40iw_status_code i40iw_sc_cceq_destroy_done(struct i40iw_sc_ceq *ceq)
{
struct i40iw_sc_cqp *cqp;
cqp = ceq->dev->cqp;
cqp->process_cqp_sds = i40iw_update_sds_noccq;
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_CEQ, NULL);
}
/**
* i40iw_sc_cceq_create - create cceq
* @ceq: ceq sc structure
* @scratch: u64 saved to be used during cqp completion
*/
static enum i40iw_status_code i40iw_sc_cceq_create(struct i40iw_sc_ceq *ceq, u64 scratch)
{
enum i40iw_status_code ret_code;
ret_code = i40iw_sc_ceq_create(ceq, scratch, true);
if (!ret_code)
ret_code = i40iw_sc_cceq_create_done(ceq);
return ret_code;
}
/**
* i40iw_sc_ceq_destroy - destroy ceq
* @ceq: ceq sc structure
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_ceq_destroy(struct i40iw_sc_ceq *ceq,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
cqp = ceq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, ceq->elem_cnt);
set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx);
header = ceq->ceq_id |
LS_64(I40IW_CQP_OP_DESTROY_CEQ, I40IW_CQPSQ_OPCODE) |
LS_64(ceq->pbl_chunk_size, I40IW_CQPSQ_CEQ_LPBLSIZE) |
LS_64(ceq->virtual_map, I40IW_CQPSQ_CEQ_VMAP) |
LS_64(ceq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CEQ_DESTROY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_process_ceq - process ceq
* @dev: sc device struct
* @ceq: ceq sc structure
*/
static void *i40iw_sc_process_ceq(struct i40iw_sc_dev *dev, struct i40iw_sc_ceq *ceq)
{
u64 temp;
u64 *ceqe;
struct i40iw_sc_cq *cq = NULL;
u8 polarity;
ceqe = (u64 *)I40IW_GET_CURRENT_CEQ_ELEMENT(ceq);
get_64bit_val(ceqe, 0, &temp);
polarity = (u8)RS_64(temp, I40IW_CEQE_VALID);
if (polarity != ceq->polarity)
return cq;
cq = (struct i40iw_sc_cq *)(unsigned long)LS_64_1(temp, 1);
I40IW_RING_MOVE_TAIL(ceq->ceq_ring);
if (I40IW_RING_GETCURRENT_TAIL(ceq->ceq_ring) == 0)
ceq->polarity ^= 1;
if (dev->is_pf)
i40iw_wr32(dev->hw, I40E_PFPE_CQACK, cq->cq_uk.cq_id);
else
i40iw_wr32(dev->hw, I40E_VFPE_CQACK1, cq->cq_uk.cq_id);
return cq;
}
/**
* i40iw_sc_aeq_init - initialize aeq
* @aeq: aeq structure ptr
* @info: aeq initialization info
*/
static enum i40iw_status_code i40iw_sc_aeq_init(struct i40iw_sc_aeq *aeq,
struct i40iw_aeq_init_info *info)
{
u32 pble_obj_cnt;
if ((info->elem_cnt < I40IW_MIN_AEQ_ENTRIES) ||
(info->elem_cnt > I40IW_MAX_AEQ_ENTRIES))
return I40IW_ERR_INVALID_SIZE;
pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
return I40IW_ERR_INVALID_PBLE_INDEX;
aeq->size = sizeof(*aeq);
aeq->polarity = 1;
aeq->aeqe_base = (struct i40iw_sc_aeqe *)info->aeqe_base;
aeq->dev = info->dev;
aeq->elem_cnt = info->elem_cnt;
aeq->aeq_elem_pa = info->aeq_elem_pa;
I40IW_RING_INIT(aeq->aeq_ring, aeq->elem_cnt);
info->dev->aeq = aeq;
aeq->virtual_map = info->virtual_map;
aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL);
aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0);
aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0);
info->dev->aeq = aeq;
return 0;
}
/**
* i40iw_sc_aeq_create - create aeq
* @aeq: aeq structure ptr
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_aeq_create(struct i40iw_sc_aeq *aeq,
u64 scratch,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
cqp = aeq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, aeq->elem_cnt);
set_64bit_val(wqe, 32,
(aeq->virtual_map ? 0 : aeq->aeq_elem_pa));
set_64bit_val(wqe, 48,
(aeq->virtual_map ? aeq->first_pm_pbl_idx : 0));
header = LS_64(I40IW_CQP_OP_CREATE_AEQ, I40IW_CQPSQ_OPCODE) |
LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_CREATE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_aeq_destroy - destroy aeq during close
* @aeq: aeq structure ptr
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_aeq_destroy(struct i40iw_sc_aeq *aeq,
u64 scratch,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
cqp = aeq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, aeq->elem_cnt);
set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx);
header = LS_64(I40IW_CQP_OP_DESTROY_AEQ, I40IW_CQPSQ_OPCODE) |
LS_64(aeq->pbl_chunk_size, I40IW_CQPSQ_AEQ_LPBLSIZE) |
LS_64(aeq->virtual_map, I40IW_CQPSQ_AEQ_VMAP) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "AEQ_DESTROY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_get_next_aeqe - get next aeq entry
* @aeq: aeq structure ptr
* @info: aeqe info to be returned
*/
static enum i40iw_status_code i40iw_sc_get_next_aeqe(struct i40iw_sc_aeq *aeq,
struct i40iw_aeqe_info *info)
{
u64 temp, compl_ctx;
u64 *aeqe;
u16 wqe_idx;
u8 ae_src;
u8 polarity;
aeqe = (u64 *)I40IW_GET_CURRENT_AEQ_ELEMENT(aeq);
get_64bit_val(aeqe, 0, &compl_ctx);
get_64bit_val(aeqe, 8, &temp);
polarity = (u8)RS_64(temp, I40IW_AEQE_VALID);
if (aeq->polarity != polarity)
return I40IW_ERR_QUEUE_EMPTY;
i40iw_debug_buf(aeq->dev, I40IW_DEBUG_WQE, "AEQ_ENTRY", aeqe, 16);
ae_src = (u8)RS_64(temp, I40IW_AEQE_AESRC);
wqe_idx = (u16)RS_64(temp, I40IW_AEQE_WQDESCIDX);
info->qp_cq_id = (u32)RS_64(temp, I40IW_AEQE_QPCQID);
info->ae_id = (u16)RS_64(temp, I40IW_AEQE_AECODE);
info->tcp_state = (u8)RS_64(temp, I40IW_AEQE_TCPSTATE);
info->iwarp_state = (u8)RS_64(temp, I40IW_AEQE_IWSTATE);
info->q2_data_written = (u8)RS_64(temp, I40IW_AEQE_Q2DATA);
info->aeqe_overflow = (bool)RS_64(temp, I40IW_AEQE_OVERFLOW);
switch (ae_src) {
case I40IW_AE_SOURCE_RQ:
case I40IW_AE_SOURCE_RQ_0011:
info->qp = true;
info->wqe_idx = wqe_idx;
info->compl_ctx = compl_ctx;
break;
case I40IW_AE_SOURCE_CQ:
case I40IW_AE_SOURCE_CQ_0110:
case I40IW_AE_SOURCE_CQ_1010:
case I40IW_AE_SOURCE_CQ_1110:
info->cq = true;
info->compl_ctx = LS_64_1(compl_ctx, 1);
break;
case I40IW_AE_SOURCE_SQ:
case I40IW_AE_SOURCE_SQ_0111:
info->qp = true;
info->sq = true;
info->wqe_idx = wqe_idx;
info->compl_ctx = compl_ctx;
break;
case I40IW_AE_SOURCE_IN_RR_WR:
case I40IW_AE_SOURCE_IN_RR_WR_1011:
info->qp = true;
info->compl_ctx = compl_ctx;
info->in_rdrsp_wr = true;
break;
case I40IW_AE_SOURCE_OUT_RR:
case I40IW_AE_SOURCE_OUT_RR_1111:
info->qp = true;
info->compl_ctx = compl_ctx;
info->out_rdrsp = true;
break;
default:
break;
}
I40IW_RING_MOVE_TAIL(aeq->aeq_ring);
if (I40IW_RING_GETCURRENT_TAIL(aeq->aeq_ring) == 0)
aeq->polarity ^= 1;
return 0;
}
/**
* i40iw_sc_repost_aeq_entries - repost completed aeq entries
* @dev: sc device struct
* @count: allocate count
*/
static enum i40iw_status_code i40iw_sc_repost_aeq_entries(struct i40iw_sc_dev *dev,
u32 count)
{
if (count > I40IW_MAX_AEQ_ALLOCATE_COUNT)
return I40IW_ERR_INVALID_SIZE;
if (dev->is_pf)
i40iw_wr32(dev->hw, I40E_PFPE_AEQALLOC, count);
else
i40iw_wr32(dev->hw, I40E_VFPE_AEQALLOC1, count);
return 0;
}
/**
* i40iw_sc_aeq_create_done - create aeq
* @aeq: aeq structure ptr
*/
static enum i40iw_status_code i40iw_sc_aeq_create_done(struct i40iw_sc_aeq *aeq)
{
struct i40iw_sc_cqp *cqp;
cqp = aeq->dev->cqp;
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_AEQ, NULL);
}
/**
* i40iw_sc_aeq_destroy_done - destroy of aeq during close
* @aeq: aeq structure ptr
*/
static enum i40iw_status_code i40iw_sc_aeq_destroy_done(struct i40iw_sc_aeq *aeq)
{
struct i40iw_sc_cqp *cqp;
cqp = aeq->dev->cqp;
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_DESTROY_AEQ, NULL);
}
/**
* i40iw_sc_ccq_init - initialize control cq
* @cq: sc's cq ctruct
* @info: info for control cq initialization
*/
static enum i40iw_status_code i40iw_sc_ccq_init(struct i40iw_sc_cq *cq,
struct i40iw_ccq_init_info *info)
{
u32 pble_obj_cnt;
if (info->num_elem < I40IW_MIN_CQ_SIZE || info->num_elem > I40IW_MAX_CQ_SIZE)
return I40IW_ERR_INVALID_SIZE;
if (info->ceq_id > I40IW_MAX_CEQID)
return I40IW_ERR_INVALID_CEQ_ID;
pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
return I40IW_ERR_INVALID_PBLE_INDEX;
cq->cq_pa = info->cq_pa;
cq->cq_uk.cq_base = info->cq_base;
cq->shadow_area_pa = info->shadow_area_pa;
cq->cq_uk.shadow_area = info->shadow_area;
cq->shadow_read_threshold = info->shadow_read_threshold;
cq->dev = info->dev;
cq->ceq_id = info->ceq_id;
cq->cq_uk.cq_size = info->num_elem;
cq->cq_type = I40IW_CQ_TYPE_CQP;
cq->ceqe_mask = info->ceqe_mask;
I40IW_RING_INIT(cq->cq_uk.cq_ring, info->num_elem);
cq->cq_uk.cq_id = 0; /* control cq is id 0 always */
cq->ceq_id_valid = info->ceq_id_valid;
cq->tph_en = info->tph_en;
cq->tph_val = info->tph_val;
cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct;
cq->pbl_list = info->pbl_list;
cq->virtual_map = info->virtual_map;
cq->pbl_chunk_size = info->pbl_chunk_size;
cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
cq->cq_uk.polarity = true;
/* following are only for iw cqs so initialize them to zero */
cq->cq_uk.cqe_alloc_reg = NULL;
info->dev->ccq = cq;
return 0;
}
/**
* i40iw_sc_ccq_create_done - poll cqp for ccq create
* @ccq: ccq sc struct
*/
static enum i40iw_status_code i40iw_sc_ccq_create_done(struct i40iw_sc_cq *ccq)
{
struct i40iw_sc_cqp *cqp;
cqp = ccq->dev->cqp;
return i40iw_sc_poll_for_cqp_op_done(cqp, I40IW_CQP_OP_CREATE_CQ, NULL);
}
/**
* i40iw_sc_ccq_create - create control cq
* @ccq: ccq sc struct
* @scratch: u64 saved to be used during cqp completion
* @check_overflow: overlow flag for ccq
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_ccq_create(struct i40iw_sc_cq *ccq,
u64 scratch,
bool check_overflow,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
enum i40iw_status_code ret_code;
cqp = ccq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
set_64bit_val(wqe, 16,
LS_64(ccq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
set_64bit_val(wqe, 32, (ccq->virtual_map ? 0 : ccq->cq_pa));
set_64bit_val(wqe, 40, ccq->shadow_area_pa);
set_64bit_val(wqe, 48,
(ccq->virtual_map ? ccq->first_pm_pbl_idx : 0));
set_64bit_val(wqe, 56,
LS_64(ccq->tph_val, I40IW_CQPSQ_TPHVAL));
header = ccq->cq_uk.cq_id |
LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
LS_64(ccq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
LS_64(ccq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_CREATE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq) {
i40iw_sc_cqp_post_sq(cqp);
ret_code = i40iw_sc_ccq_create_done(ccq);
if (ret_code)
return ret_code;
}
cqp->process_cqp_sds = i40iw_cqp_sds_cmd;
return 0;
}
/**
* i40iw_sc_ccq_destroy - destroy ccq during close
* @ccq: ccq sc struct
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_ccq_destroy(struct i40iw_sc_cq *ccq,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
enum i40iw_status_code ret_code = 0;
u32 tail, val, error;
cqp = ccq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 0, ccq->cq_uk.cq_size);
set_64bit_val(wqe, 8, RS_64_1(ccq, 1));
set_64bit_val(wqe, 40, ccq->shadow_area_pa);
header = ccq->cq_uk.cq_id |
LS_64((ccq->ceq_id_valid ? ccq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
LS_64(ccq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
LS_64(ccq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
LS_64(ccq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(ccq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CCQ_DESTROY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
i40iw_get_cqp_reg_info(cqp, &val, &tail, &error);
if (error)
return I40IW_ERR_CQP_COMPL_ERROR;
if (post_sq) {
i40iw_sc_cqp_post_sq(cqp);
ret_code = i40iw_cqp_poll_registers(cqp, tail, 1000);
}
cqp->process_cqp_sds = i40iw_update_sds_noccq;
return ret_code;
}
/**
* i40iw_sc_cq_init - initialize completion q
* @cq: cq struct
* @info: cq initialization info
*/
static enum i40iw_status_code i40iw_sc_cq_init(struct i40iw_sc_cq *cq,
struct i40iw_cq_init_info *info)
{
u32 __iomem *cqe_alloc_reg = NULL;
enum i40iw_status_code ret_code;
u32 pble_obj_cnt;
u32 arm_offset;
pble_obj_cnt = info->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if (info->virtual_map && (info->first_pm_pbl_idx >= pble_obj_cnt))
return I40IW_ERR_INVALID_PBLE_INDEX;
cq->cq_pa = info->cq_base_pa;
cq->dev = info->dev;
cq->ceq_id = info->ceq_id;
arm_offset = (info->dev->is_pf) ? I40E_PFPE_CQARM : I40E_VFPE_CQARM1;
if (i40iw_get_hw_addr(cq->dev))
cqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(cq->dev) +
arm_offset);
info->cq_uk_init_info.cqe_alloc_reg = cqe_alloc_reg;
ret_code = i40iw_cq_uk_init(&cq->cq_uk, &info->cq_uk_init_info);
if (ret_code)
return ret_code;
cq->virtual_map = info->virtual_map;
cq->pbl_chunk_size = info->pbl_chunk_size;
cq->ceqe_mask = info->ceqe_mask;
cq->cq_type = (info->type) ? info->type : I40IW_CQ_TYPE_IWARP;
cq->shadow_area_pa = info->shadow_area_pa;
cq->shadow_read_threshold = info->shadow_read_threshold;
cq->ceq_id_valid = info->ceq_id_valid;
cq->tph_en = info->tph_en;
cq->tph_val = info->tph_val;
cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
return 0;
}
/**
* i40iw_sc_cq_create - create completion q
* @cq: cq struct
* @scratch: u64 saved to be used during cqp completion
* @check_overflow: flag for overflow check
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_cq_create(struct i40iw_sc_cq *cq,
u64 scratch,
bool check_overflow,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
if (cq->cq_uk.cq_id > I40IW_MAX_CQID)
return I40IW_ERR_INVALID_CQ_ID;
if (cq->ceq_id > I40IW_MAX_CEQID)
return I40IW_ERR_INVALID_CEQ_ID;
cqp = cq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
set_64bit_val(wqe, 8, RS_64_1(cq, 1));
set_64bit_val(wqe,
16,
LS_64(cq->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
set_64bit_val(wqe, 40, cq->shadow_area_pa);
set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
header = cq->cq_uk.cq_id |
LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
LS_64(I40IW_CQP_OP_CREATE_CQ, I40IW_CQPSQ_OPCODE) |
LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_CREATE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_cq_destroy - destroy completion q
* @cq: cq struct
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_cq_destroy(struct i40iw_sc_cq *cq,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
cqp = cq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 0, cq->cq_uk.cq_size);
set_64bit_val(wqe, 8, RS_64_1(cq, 1));
set_64bit_val(wqe, 40, cq->shadow_area_pa);
set_64bit_val(wqe, 48, (cq->virtual_map ? cq->first_pm_pbl_idx : 0));
header = cq->cq_uk.cq_id |
LS_64((cq->ceq_id_valid ? cq->ceq_id : 0), I40IW_CQPSQ_CQ_CEQID) |
LS_64(I40IW_CQP_OP_DESTROY_CQ, I40IW_CQPSQ_OPCODE) |
LS_64(cq->pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
LS_64(cq->virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
LS_64(cq->ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_DESTROY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_cq_modify - modify a Completion Queue
* @cq: cq struct
* @info: modification info struct
* @scratch:
* @post_sq: flag to post to sq
*/
static enum i40iw_status_code i40iw_sc_cq_modify(struct i40iw_sc_cq *cq,
struct i40iw_modify_cq_info *info,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
u32 cq_size, ceq_id, first_pm_pbl_idx;
u8 pbl_chunk_size;
bool virtual_map, ceq_id_valid, check_overflow;
u32 pble_obj_cnt;
if (info->ceq_valid && (info->ceq_id > I40IW_MAX_CEQID))
return I40IW_ERR_INVALID_CEQ_ID;
pble_obj_cnt = cq->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if (info->cq_resize && info->virtual_map &&
(info->first_pm_pbl_idx >= pble_obj_cnt))
return I40IW_ERR_INVALID_PBLE_INDEX;
cqp = cq->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
cq->pbl_list = info->pbl_list;
cq->cq_pa = info->cq_pa;
cq->first_pm_pbl_idx = info->first_pm_pbl_idx;
cq_size = info->cq_resize ? info->cq_size : cq->cq_uk.cq_size;
if (info->ceq_change) {
ceq_id_valid = true;
ceq_id = info->ceq_id;
} else {
ceq_id_valid = cq->ceq_id_valid;
ceq_id = ceq_id_valid ? cq->ceq_id : 0;
}
virtual_map = info->cq_resize ? info->virtual_map : cq->virtual_map;
first_pm_pbl_idx = (info->cq_resize ?
(info->virtual_map ? info->first_pm_pbl_idx : 0) :
(cq->virtual_map ? cq->first_pm_pbl_idx : 0));
pbl_chunk_size = (info->cq_resize ?
(info->virtual_map ? info->pbl_chunk_size : 0) :
(cq->virtual_map ? cq->pbl_chunk_size : 0));
check_overflow = info->check_overflow_change ? info->check_overflow :
cq->check_overflow;
cq->cq_uk.cq_size = cq_size;
cq->ceq_id_valid = ceq_id_valid;
cq->ceq_id = ceq_id;
cq->virtual_map = virtual_map;
cq->first_pm_pbl_idx = first_pm_pbl_idx;
cq->pbl_chunk_size = pbl_chunk_size;
cq->check_overflow = check_overflow;
set_64bit_val(wqe, 0, cq_size);
set_64bit_val(wqe, 8, RS_64_1(cq, 1));
set_64bit_val(wqe, 16,
LS_64(info->shadow_read_threshold, I40IW_CQPSQ_CQ_SHADOW_READ_THRESHOLD));
set_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));
set_64bit_val(wqe, 40, cq->shadow_area_pa);
set_64bit_val(wqe, 48, (cq->virtual_map ? first_pm_pbl_idx : 0));
set_64bit_val(wqe, 56, LS_64(cq->tph_val, I40IW_CQPSQ_TPHVAL));
header = cq->cq_uk.cq_id |
LS_64(ceq_id, I40IW_CQPSQ_CQ_CEQID) |
LS_64(I40IW_CQP_OP_MODIFY_CQ, I40IW_CQPSQ_OPCODE) |
LS_64(info->cq_resize, I40IW_CQPSQ_CQ_CQRESIZE) |
LS_64(pbl_chunk_size, I40IW_CQPSQ_CQ_LPBLSIZE) |
LS_64(check_overflow, I40IW_CQPSQ_CQ_CHKOVERFLOW) |
LS_64(virtual_map, I40IW_CQPSQ_CQ_VIRTMAP) |
LS_64(cq->ceqe_mask, I40IW_CQPSQ_CQ_ENCEQEMASK) |
LS_64(ceq_id_valid, I40IW_CQPSQ_CQ_CEQIDVALID) |
LS_64(cq->tph_en, I40IW_CQPSQ_TPHEN) |
LS_64(cq->cq_uk.avoid_mem_cflct, I40IW_CQPSQ_CQ_AVOIDMEMCNFLCT) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "CQ_MODIFY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_init - initialize qp
* @qp: sc qp
* @info: initialization qp info
*/
static enum i40iw_status_code i40iw_sc_qp_init(struct i40iw_sc_qp *qp,
struct i40iw_qp_init_info *info)
{
u32 __iomem *wqe_alloc_reg = NULL;
enum i40iw_status_code ret_code;
u32 pble_obj_cnt;
u8 wqe_size;
u32 offset;
qp->dev = info->pd->dev;
qp->vsi = info->vsi;
qp->sq_pa = info->sq_pa;
qp->rq_pa = info->rq_pa;
qp->hw_host_ctx_pa = info->host_ctx_pa;
qp->q2_pa = info->q2_pa;
qp->shadow_area_pa = info->shadow_area_pa;
qp->q2_buf = info->q2;
qp->pd = info->pd;
qp->hw_host_ctx = info->host_ctx;
offset = (qp->pd->dev->is_pf) ? I40E_PFPE_WQEALLOC : I40E_VFPE_WQEALLOC1;
if (i40iw_get_hw_addr(qp->pd->dev))
wqe_alloc_reg = (u32 __iomem *)(i40iw_get_hw_addr(qp->pd->dev) +
offset);
info->qp_uk_init_info.wqe_alloc_reg = wqe_alloc_reg;
info->qp_uk_init_info.abi_ver = qp->pd->abi_ver;
ret_code = i40iw_qp_uk_init(&qp->qp_uk, &info->qp_uk_init_info);
if (ret_code)
return ret_code;
qp->virtual_map = info->virtual_map;
pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[I40IW_HMC_IW_PBLE].cnt;
if ((info->virtual_map && (info->sq_pa >= pble_obj_cnt)) ||
(info->virtual_map && (info->rq_pa >= pble_obj_cnt)))
return I40IW_ERR_INVALID_PBLE_INDEX;
qp->llp_stream_handle = (void *)(-1);
qp->qp_type = (info->type) ? info->type : I40IW_QP_TYPE_IWARP;
qp->hw_sq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.sq_ring.size,
false);
i40iw_debug(qp->dev, I40IW_DEBUG_WQE, "%s: hw_sq_size[%04d] sq_ring.size[%04d]\n",
__func__, qp->hw_sq_size, qp->qp_uk.sq_ring.size);
switch (qp->pd->abi_ver) {
case 4:
ret_code = i40iw_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt,
&wqe_size);
if (ret_code)
return ret_code;
break;
case 5: /* fallthrough until next ABI version */
default:
if (qp->qp_uk.max_rq_frag_cnt > I40IW_MAX_WQ_FRAGMENT_COUNT)
return I40IW_ERR_INVALID_FRAG_COUNT;
wqe_size = I40IW_MAX_WQE_SIZE_RQ;
break;
}
qp->hw_rq_size = i40iw_get_encoded_wqe_size(qp->qp_uk.rq_size *
(wqe_size / I40IW_QP_WQE_MIN_SIZE), false);
i40iw_debug(qp->dev, I40IW_DEBUG_WQE,
"%s: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n",
__func__, qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size);
qp->sq_tph_val = info->sq_tph_val;
qp->rq_tph_val = info->rq_tph_val;
qp->sq_tph_en = info->sq_tph_en;
qp->rq_tph_en = info->rq_tph_en;
qp->rcv_tph_en = info->rcv_tph_en;
qp->xmit_tph_en = info->xmit_tph_en;
qp->qs_handle = qp->vsi->qos[qp->user_pri].qs_handle;
qp->exception_lan_queue = qp->pd->dev->exception_lan_queue;
return 0;
}
/**
* i40iw_sc_qp_create - create qp
* @qp: sc qp
* @info: qp create info
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_qp_create(
struct i40iw_sc_qp *qp,
struct i40iw_create_qp_info *info,
u64 scratch,
bool post_sq)
{
struct i40iw_sc_cqp *cqp;
u64 *wqe;
u64 header;
if ((qp->qp_uk.qp_id < I40IW_MIN_IW_QP_ID) ||
(qp->qp_uk.qp_id > I40IW_MAX_IW_QP_ID))
return I40IW_ERR_INVALID_QP_ID;
cqp = qp->pd->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
set_64bit_val(wqe, 40, qp->shadow_area_pa);
header = qp->qp_uk.qp_id |
LS_64(I40IW_CQP_OP_CREATE_QP, I40IW_CQPSQ_OPCODE) |
LS_64((info->ord_valid ? 1 : 0), I40IW_CQPSQ_QP_ORDVALID) |
LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_CREATE WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_modify - modify qp cqp wqe
* @qp: sc qp
* @info: modify qp info
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_qp_modify(
struct i40iw_sc_qp *qp,
struct i40iw_modify_qp_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
u8 term_actions = 0;
u8 term_len = 0;
cqp = qp->pd->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
if (info->next_iwarp_state == I40IW_QP_STATE_TERMINATE) {
if (info->dont_send_fin)
term_actions += I40IWQP_TERM_SEND_TERM_ONLY;
if (info->dont_send_term)
term_actions += I40IWQP_TERM_SEND_FIN_ONLY;
if ((term_actions == I40IWQP_TERM_SEND_TERM_AND_FIN) ||
(term_actions == I40IWQP_TERM_SEND_TERM_ONLY))
term_len = info->termlen;
}
set_64bit_val(wqe,
8,
LS_64(term_len, I40IW_CQPSQ_QP_TERMLEN));
set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
set_64bit_val(wqe, 40, qp->shadow_area_pa);
header = qp->qp_uk.qp_id |
LS_64(I40IW_CQP_OP_MODIFY_QP, I40IW_CQPSQ_OPCODE) |
LS_64(info->ord_valid, I40IW_CQPSQ_QP_ORDVALID) |
LS_64(info->tcp_ctx_valid, I40IW_CQPSQ_QP_TOECTXVALID) |
LS_64(info->cached_var_valid, I40IW_CQPSQ_QP_CACHEDVARVALID) |
LS_64(qp->virtual_map, I40IW_CQPSQ_QP_VQ) |
LS_64(info->cq_num_valid, I40IW_CQPSQ_QP_CQNUMVALID) |
LS_64(info->force_loopback, I40IW_CQPSQ_QP_FORCELOOPBACK) |
LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
LS_64(info->static_rsrc, I40IW_CQPSQ_QP_STATRSRC) |
LS_64(info->remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
LS_64(term_actions, I40IW_CQPSQ_QP_TERMACT) |
LS_64(info->reset_tcp_conn, I40IW_CQPSQ_QP_RESETCON) |
LS_64(info->arp_cache_idx_valid, I40IW_CQPSQ_QP_ARPTABIDXVALID) |
LS_64(info->next_iwarp_state, I40IW_CQPSQ_QP_NEXTIWSTATE) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_MODIFY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_destroy - cqp destroy qp
* @qp: sc qp
* @scratch: u64 saved to be used during cqp completion
* @remove_hash_idx: flag if to remove hash idx
* @ignore_mw_bnd: memory window bind flag
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_qp_destroy(
struct i40iw_sc_qp *qp,
u64 scratch,
bool remove_hash_idx,
bool ignore_mw_bnd,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
i40iw_qp_rem_qos(qp);
cqp = qp->pd->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, qp->hw_host_ctx_pa);
set_64bit_val(wqe, 40, qp->shadow_area_pa);
header = qp->qp_uk.qp_id |
LS_64(I40IW_CQP_OP_DESTROY_QP, I40IW_CQPSQ_OPCODE) |
LS_64(qp->qp_type, I40IW_CQPSQ_QP_QPTYPE) |
LS_64(ignore_mw_bnd, I40IW_CQPSQ_QP_IGNOREMWBOUND) |
LS_64(remove_hash_idx, I40IW_CQPSQ_QP_REMOVEHASHENTRY) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_DESTROY WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_flush_wqes - flush qp's wqe
* @qp: sc qp
* @info: dlush information
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_qp_flush_wqes(
struct i40iw_sc_qp *qp,
struct i40iw_qp_flush_info *info,
u64 scratch,
bool post_sq)
{
u64 temp = 0;
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
bool flush_sq = false, flush_rq = false;
if (info->rq && !qp->flush_rq)
flush_rq = true;
if (info->sq && !qp->flush_sq)
flush_sq = true;
qp->flush_sq |= flush_sq;
qp->flush_rq |= flush_rq;
if (!flush_sq && !flush_rq) {
if (info->ae_code != I40IW_AE_LLP_RECEIVED_MPA_CRC_ERROR)
return 0;
}
cqp = qp->pd->dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
if (info->userflushcode) {
if (flush_rq) {
temp |= LS_64(info->rq_minor_code, I40IW_CQPSQ_FWQE_RQMNERR) |
LS_64(info->rq_major_code, I40IW_CQPSQ_FWQE_RQMJERR);
}
if (flush_sq) {
temp |= LS_64(info->sq_minor_code, I40IW_CQPSQ_FWQE_SQMNERR) |
LS_64(info->sq_major_code, I40IW_CQPSQ_FWQE_SQMJERR);
}
}
set_64bit_val(wqe, 16, temp);
temp = (info->generate_ae) ?
info->ae_code | LS_64(info->ae_source, I40IW_CQPSQ_FWQE_AESOURCE) : 0;
set_64bit_val(wqe, 8, temp);
header = qp->qp_uk.qp_id |
LS_64(I40IW_CQP_OP_FLUSH_WQES, I40IW_CQPSQ_OPCODE) |
LS_64(info->generate_ae, I40IW_CQPSQ_FWQE_GENERATE_AE) |
LS_64(info->userflushcode, I40IW_CQPSQ_FWQE_USERFLCODE) |
LS_64(flush_sq, I40IW_CQPSQ_FWQE_FLUSHSQ) |
LS_64(flush_rq, I40IW_CQPSQ_FWQE_FLUSHRQ) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(cqp->dev, I40IW_DEBUG_WQE, "QP_FLUSH WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_upload_context - upload qp's context
* @dev: sc device struct
* @info: upload context info ptr for return
* @scratch: u64 saved to be used during cqp completion
* @post_sq: flag for cqp db to ring
*/
static enum i40iw_status_code i40iw_sc_qp_upload_context(
struct i40iw_sc_dev *dev,
struct i40iw_upload_context_info *info,
u64 scratch,
bool post_sq)
{
u64 *wqe;
struct i40iw_sc_cqp *cqp;
u64 header;
cqp = dev->cqp;
wqe = i40iw_sc_cqp_get_next_send_wqe(cqp, scratch);
if (!wqe)
return I40IW_ERR_RING_FULL;
set_64bit_val(wqe, 16, info->buf_pa);
header = LS_64(info->qp_id, I40IW_CQPSQ_UCTX_QPID) |
LS_64(I40IW_CQP_OP_UPLOAD_CONTEXT, I40IW_CQPSQ_OPCODE) |
LS_64(info->qp_type, I40IW_CQPSQ_UCTX_QPTYPE) |
LS_64(info->raw_format, I40IW_CQPSQ_UCTX_RAWFORMAT) |
LS_64(info->freeze_qp, I40IW_CQPSQ_UCTX_FREEZEQP) |
LS_64(cqp->polarity, I40IW_CQPSQ_WQEVALID);
i40iw_insert_wqe_hdr(wqe, header);
i40iw_debug_buf(dev, I40IW_DEBUG_WQE, "QP_UPLOAD_CTX WQE",
wqe, I40IW_CQP_WQE_SIZE * 8);
if (post_sq)
i40iw_sc_cqp_post_sq(cqp);
return 0;
}
/**
* i40iw_sc_qp_setctx - set qp's context
* @qp: sc qp
* @qp_ctx: context ptr
* @info: ctx info
*/
static enum i40iw_status_code i40iw_sc_qp_setctx(
struct i40iw_sc_qp *qp,
u64 *qp_ctx,
struct i40iw_qp_host_ctx_info *info)
{
struct i40iwarp_offload_info *iw;
struct i40iw_tcp_offload_info *tcp;
struct i40iw_sc_vsi *vsi;
struct i40iw_sc_dev *dev;
u64 qw0, qw3, qw7 = 0;
iw = info->iwarp_info;
tcp = info->tcp_info;
vsi = qp->vsi;
dev = qp->dev;
if (info->add_to_qoslist) {
qp->user_pri = info->user_pri;
i40iw_qp_add_qos(qp);
i40iw_debug(qp->dev, I40IW_DEBUG_DCB, "%s qp[%d] UP[%d] qset[%d]\n",
__func__, qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle);
}
qw0 = LS_64(qp->qp_uk.rq_wqe_size, I40IWQPC_RQWQESIZE) |
LS_64(info->err_rq_idx_valid, I40IWQPC_ERR_RQ_IDX_VALID) |
LS_64(qp->rcv_tph_en, I40IWQPC_RCVTPHEN) |
LS_64(qp->xmit_tph_en, I40IWQPC_XMITTPHEN) |
LS_64(qp->rq_tph_en, I40IWQPC_RQTPHEN) |
LS_64(qp->sq_tph_en, I40IWQPC_SQTPHEN) |
LS_64(info->push_idx, I40IWQPC_PPIDX) |
LS_64(info->push_mode_en, I40IWQPC_PMENA);
set_64bit_val(qp_ctx, 8, qp->sq_pa);
set_64bit_val(qp_ctx, 16, qp->rq_pa);
qw3 = LS_64(qp->src_mac_addr_idx, I40IWQPC_SRCMACADDRIDX) |
LS_64(qp->hw_rq_size, I40IWQPC_RQSIZE) |
LS_64(qp->hw_sq_size, I40IWQPC_SQSIZE);
set_64bit_val(qp_ctx,
128,
LS_64(info->err_rq_idx, I40IWQPC_ERR_RQ_IDX));
set_64bit_val(qp_ctx,
136,
LS_64(info->send_cq_num, I40IWQPC_TXCQNUM) |
LS_64(info->rcv_cq_num, I40IWQPC_RXCQNUM));
set_64bit_val(qp_ctx,
168,
LS_64(info->qp_compl_ctx, I40IWQPC_QPCOMPCTX));
set_64bit_val(qp_ctx,
176,
LS_64(qp->sq_tph_val, I40IWQPC_SQTPHVAL) |
LS_64(qp->rq_tph_val, I40IWQPC_RQTPHVAL) |
LS_64(qp->qs_handle, I40IWQPC_QSHANDLE) |
LS_64(qp->exception_lan_queue, I40IWQPC_EXCEPTION_LAN_QUEUE));
if (info->iwarp_info_valid) {
qw0 |= LS_64(iw->ddp_ver, I40IWQPC_DDP_VER) |
LS_64(iw->rdmap_ver, I40IWQPC_RDMAP_VER);
qw7 |= LS_64(iw->pd_id, I40IWQPC_PDIDX);
set_64bit_val(qp_ctx,
144,
LS_64(qp->q2_pa, I40IWQPC_Q2ADDR) |
LS_64(vsi->fcn_id, I40IWQPC_STAT_INDEX));
set_64bit_val(qp_ctx,
152,
LS_64(iw->last_byte_sent, I40IWQPC_LASTBYTESENT));
set_64bit_val(qp_ctx,
160,
LS_64(iw->ord_size, I40IWQPC_ORDSIZE) |
LS_64(iw->ird_size, I40IWQPC_IRDSIZE) |
LS_64(iw->wr_rdresp_en, I40IWQPC_WRRDRSPOK) |
LS_64(iw->rd_enable, I40IWQPC_RDOK) |
LS_64(iw->snd_mark_en, I40IWQPC_SNDMARKERS) |
LS_64(iw->bind_en, I40IWQPC_BINDEN) |
LS_64(iw->fast_reg_en, I40IWQPC_FASTREGEN) |
LS_64(iw->priv_mode_en, I40IWQPC_PRIVEN) |
LS_64((((vsi->stats_fcn_id_alloc) &&
(dev->is_pf) && (vsi->fcn_id >= I40IW_FIRST_NON_PF_STAT)) ? 1 : 0),
I40IWQPC_USESTATSINSTANCE