)]}'
{
  "commit": "1d90b503befedf7aec12b9d10c6783b3c8587bb3",
  "tree": "5d7095fadb47811a60a2a68c4bb1a78c1c182fa1",
  "parents": [
    "43b365ed3fc7e0f4b8c4f426f4c8e698e63ff031",
    "eede67deb547e6207590272b86c380d90d3211d1"
  ],
  "author": {
    "name": "Bjorn Helgaas",
    "email": "bhelgaas@google.com",
    "time": "Wed Jun 04 10:50:42 2025 -0500"
  },
  "committer": {
    "name": "Bjorn Helgaas",
    "email": "bhelgaas@google.com",
    "time": "Wed Jun 04 10:50:42 2025 -0500"
  },
  "message": "Merge branch \u0027pci/controller/qcom\u0027\n\n- Add OF support for parsing DT \u0027eq-presets-\u003cN\u003egts\u0027 property for lane\n  equalization presets (Krishna Chaitanya Chundru)\n\n- Read Maximum Link Width from the Link Capabilities register if DT lacks\n  \u0027num-lanes\u0027 property (Krishna Chaitanya Chundru)\n\n- Add Physical Layer 64 GT/s Capability ID and register offsets for 8, 32,\n  and 64 GT/s lane equalization registers (Krishna Chaitanya Chundru)\n\n- Add generic dwc support for configuring lane equalization presets\n  (Krishna Chaitanya Chundru)\n\n- Add DT and driver support for PCIe on IPQ5018 SoC (Nitheesh Sekar)\n\n* pci/controller/qcom:\n  PCI: qcom: Add support for IPQ5018\n  dt-bindings: PCI: qcom: Add IPQ5018 SoC\n  PCI: dwc: Add support for configuring lane equalization presets\n  PCI: Add lane equalization register offsets\n  PCI: dwc: Update pci-\u003enum_lanes to maximum supported link width\n  PCI: of: Add of_pci_get_equalization_presets() API\n\n[ upstream commit: 05cf00aa05afed0d6808cce6654ef8be457fb6bb ]\n",
  "tree_diff": []
}