Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux
Pull clk updates from Stephen Boyd:
"We've finally gotten rid of the struct clk_ops::round_rate() code
after months of effort from Brian Masney. Now the only option is to
use determine_rate(), which is good because that takes a struct
argument instead of just a couple unsigned longs, allowing us to
easily modify the way we determine and set rates in the clk tree.
Beyond that core framework change we've got the typical pile of new
SoC clk driver additions, fixes for clk data and/or adding missing
clks because the consumer driver using those clks wasn't ready, etc.
The usual suspects are all here: Qualcomm, Samsung, Mediatek, and
Rockchip along with some newcomers making RISC-V SoCs like ESWIN's
eic700 and Tenstorrent's Atlantis. The clk driver side of this looks
pretty normal.
Core:
- Remove the round_rate() clk op (yay!)
New Drivers:
- ESWIN eic700 SoC clk support
- Econet EN751221 SoC clock/reset support
- Global TCSR, RPMh, and display clock controller support for the
Qualcomm Eliza platform
- TCSR, the multiple global, and the RPMh clock controller support
for the Qualcomm Nord platform
- GPU clock controller support for Qualcomm SM8750
- Video and GPU clock controller support for Qualcomm Glymur
- Global clock controller support for Qualcomm IPQ5210
- Axis ARTPEC-9: Add new PLL clocks and new drivers for eight clock
controllers on the SoC
- ExynosAutov920: Add G3D (GPU) clock controller
- Clock driver for the Rockchip RV1103B SoC
- Initial support for the Renesas RZ/G3L (R9A08G046) SoC
- Clock and reset controllers (e.g. PRCM) in the Tenstorrent Atlantis SoC"
* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (132 commits)
clk: visconti: pll: initialize clk_init_data to zero
clk: fsl-sai: Add MCLK generation support
clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()
dt-bindings: clock: fsl-sai: Document clock-cells = <1> support
clk: fsl-sai: Add i.MX8M support with 8 byte register offset
clk: fsl-sai: Sort the headers
dt-bindings: clock: fsl-sai: Document i.MX8M support
clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC
clk: qcom: rpmh: Add support for Nord rpmh clocks
clk: qcom: Add TCSR clock driver for Nord SoC
dt-bindings: clock: qcom: Add Nord Global Clock Controller
dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs
dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller
clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON
clk: qcom: Constify list of critical CBCR registers
clk: qcom: Constify qcom_cc_driver_data
clk: qcom: videocc-glymur: Constify qcom_cc_desc
clk: qcom: Add a driver for SM8750 GPU clocks
dt-bindings: clock: qcom: Add SM8750 GPU clocks
clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
...
[ upstream commit: 4ee64205ffaa587e8114d84a67ac721399ccb369 ]
diff --git a/Bindings/clock/airoha,en7523-scu.yaml b/Bindings/clock/airoha,en7523-scu.yaml
index a847136..eb24a56 100644
--- a/Bindings/clock/airoha,en7523-scu.yaml
+++ b/Bindings/clock/airoha,en7523-scu.yaml
@@ -32,6 +32,7 @@
- enum:
- airoha,en7523-scu
- airoha,en7581-scu
+ - econet,en751221-scu
reg:
items:
@@ -67,7 +68,9 @@
- if:
properties:
compatible:
- const: airoha,en7581-scu
+ enum:
+ - airoha,en7581-scu
+ - econet,en751221-scu
then:
properties:
reg:
@@ -98,3 +101,4 @@
#reset-cells = <1>;
};
};
+
diff --git a/Bindings/clock/baikal,bt1-ccu-div.yaml b/Bindings/clock/baikal,bt1-ccu-div.yaml
deleted file mode 100644
index 30252c95..0000000
--- a/Bindings/clock/baikal,bt1-ccu-div.yaml
+++ /dev/null
@@ -1,196 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-div.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Baikal-T1 Clock Control Unit Dividers
-
-maintainers:
- - Serge Semin <fancer.lancer@gmail.com>
-
-description: |
- Clocks Control Unit is the core of Baikal-T1 SoC System Controller
- responsible for the chip subsystems clocking and resetting. The CCU is
- connected with an external fixed rate oscillator, which signal is transformed
- into clocks of various frequencies and then propagated to either individual
- IP-blocks or to groups of blocks (clock domains). The transformation is done
- by means of an embedded into CCU PLLs and gateable/non-gateable dividers. The
- later ones are described in this binding. Each clock domain can be also
- individually reset by using the domain clocks divider configuration
- registers. Baikal-T1 CCU is logically divided into the next components:
- 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
- in general can provide any frequency supported by the CCU PLLs).
- 2) PLLs clocks generators (PLLs).
- 3) AXI-bus clock dividers (AXI) - described in this binding file.
- 4) System devices reference clock dividers (SYS) - described in this binding
- file.
- which are connected with each other as shown on the next figure:
-
- +---------------+
- | Baikal-T1 CCU |
- | +----+------|- MIPS P5600 cores
- | +-|PLLs|------|- DDR controller
- | | +----+ |
- +----+ | | | | |
- |XTAL|--|-+ | | +---+-|
- +----+ | | | +-|AXI|-|- AXI-bus
- | | | +---+-|
- | | | |
- | | +----+---+-|- APB-bus
- | +-------|SYS|-|- Low-speed Devices
- | +---+-|- High-speed Devices
- +---------------+
-
- Each sub-block is represented as a separate DT node and has an individual
- driver to be bound with.
-
- In order to create signals of wide range frequencies the external oscillator
- output is primarily connected to a set of CCU PLLs. Some of PLLs CLKOUT are
- then passed over CCU dividers to create signals required for the target clock
- domain (like AXI-bus or System Device consumers). The dividers have the
- following structure:
-
- +--------------+
- CLKIN --|->+----+ 1|\ |
- SETCLK--|--|/DIV|->| | |
- CLKDIV--|--| | | |-|->CLKLOUT
- LOCK----|--+----+ | | |
- | |/ |
- | | |
- EN------|-----------+ |
- RST-----|--------------|->RSTOUT
- +--------------+
-
- where CLKIN is the reference clock coming either from CCU PLLs or from an
- external clock oscillator, SETCLK - a command to update the output clock in
- accordance with a set divider, CLKDIV - clocks divider, LOCK - a signal of
- the output clock stabilization, EN - enable/disable the divider block,
- RST/RSTOUT - reset clocks domain signal. Depending on the consumer IP-core
- peculiarities the dividers may lack of some functionality depicted on the
- figure above (like EN, CLKDIV/LOCK/SETCLK). In this case the corresponding
- clock provider just doesn't expose either switching functions, or the rate
- configuration, or both of them.
-
- The clock dividers, which output clock is then consumed by the SoC individual
- devices, are united into a single clocks provider called System Devices CCU.
- Similarly the dividers with output clocks utilized as AXI-bus reference clocks
- are called AXI-bus CCU. Both of them use the common clock bindings with no
- custom properties. The list of exported clocks and reset signals can be found
- in the files: 'include/dt-bindings/clock/bt1-ccu.h' and
- 'include/dt-bindings/reset/bt1-ccu.h'. Since System Devices and AXI-bus CCU
- are a part of the Baikal-T1 SoC System Controller their DT nodes are supposed
- to be a children of later one.
-
-if:
- properties:
- compatible:
- contains:
- const: baikal,bt1-ccu-axi
-
-then:
- properties:
- clocks:
- items:
- - description: CCU SATA PLL output clock
- - description: CCU PCIe PLL output clock
- - description: CCU Ethernet PLL output clock
-
- clock-names:
- items:
- - const: sata_clk
- - const: pcie_clk
- - const: eth_clk
-
-else:
- properties:
- clocks:
- items:
- - description: External reference clock
- - description: CCU SATA PLL output clock
- - description: CCU PCIe PLL output clock
- - description: CCU Ethernet PLL output clock
-
- clock-names:
- items:
- - const: ref_clk
- - const: sata_clk
- - const: pcie_clk
- - const: eth_clk
-
-properties:
- compatible:
- enum:
- - baikal,bt1-ccu-axi
- - baikal,bt1-ccu-sys
-
- reg:
- maxItems: 1
-
- "#clock-cells":
- const: 1
-
- "#reset-cells":
- const: 1
-
- clocks:
- minItems: 3
- maxItems: 4
-
- clock-names:
- minItems: 3
- maxItems: 4
-
-additionalProperties: false
-
-required:
- - compatible
- - "#clock-cells"
- - clocks
- - clock-names
-
-examples:
- # AXI-bus Clock Control Unit node:
- - |
- #include <dt-bindings/clock/bt1-ccu.h>
-
- clock-controller@1f04d030 {
- compatible = "baikal,bt1-ccu-axi";
- reg = <0x1f04d030 0x030>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clocks = <&ccu_pll CCU_SATA_PLL>,
- <&ccu_pll CCU_PCIE_PLL>,
- <&ccu_pll CCU_ETH_PLL>;
- clock-names = "sata_clk", "pcie_clk", "eth_clk";
- };
- # System Devices Clock Control Unit node:
- - |
- #include <dt-bindings/clock/bt1-ccu.h>
-
- clock-controller@1f04d060 {
- compatible = "baikal,bt1-ccu-sys";
- reg = <0x1f04d060 0x0a0>;
- #clock-cells = <1>;
- #reset-cells = <1>;
-
- clocks = <&clk25m>,
- <&ccu_pll CCU_SATA_PLL>,
- <&ccu_pll CCU_PCIE_PLL>,
- <&ccu_pll CCU_ETH_PLL>;
- clock-names = "ref_clk", "sata_clk", "pcie_clk",
- "eth_clk";
- };
- # Required Clock Control Unit PLL node:
- - |
- ccu_pll: clock-controller@1f04d000 {
- compatible = "baikal,bt1-ccu-pll";
- reg = <0x1f04d000 0x028>;
- #clock-cells = <1>;
-
- clocks = <&clk25m>;
- clock-names = "ref_clk";
- };
-...
diff --git a/Bindings/clock/baikal,bt1-ccu-pll.yaml b/Bindings/clock/baikal,bt1-ccu-pll.yaml
deleted file mode 100644
index 7f8d982..0000000
--- a/Bindings/clock/baikal,bt1-ccu-pll.yaml
+++ /dev/null
@@ -1,131 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/clock/baikal,bt1-ccu-pll.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Baikal-T1 Clock Control Unit PLL
-
-maintainers:
- - Serge Semin <fancer.lancer@gmail.com>
-
-description: |
- Clocks Control Unit is the core of Baikal-T1 SoC System Controller
- responsible for the chip subsystems clocking and resetting. The CCU is
- connected with an external fixed rate oscillator, which signal is transformed
- into clocks of various frequencies and then propagated to either individual
- IP-blocks or to groups of blocks (clock domains). The transformation is done
- by means of PLLs and gateable/non-gateable dividers embedded into the CCU.
- It's logically divided into the next components:
- 1) External oscillator (normally XTAL's 25 MHz crystal oscillator, but
- in general can provide any frequency supported by the CCU PLLs).
- 2) PLLs clocks generators (PLLs) - described in this binding file.
- 3) AXI-bus clock dividers (AXI).
- 4) System devices reference clock dividers (SYS).
- which are connected with each other as shown on the next figure:
-
- +---------------+
- | Baikal-T1 CCU |
- | +----+------|- MIPS P5600 cores
- | +-|PLLs|------|- DDR controller
- | | +----+ |
- +----+ | | | | |
- |XTAL|--|-+ | | +---+-|
- +----+ | | | +-|AXI|-|- AXI-bus
- | | | +---+-|
- | | | |
- | | +----+---+-|- APB-bus
- | +-------|SYS|-|- Low-speed Devices
- | +---+-|- High-speed Devices
- +---------------+
-
- Each CCU sub-block is represented as a separate dts-node and has an
- individual driver to be bound with.
-
- In order to create signals of wide range frequencies the external oscillator
- output is primarily connected to a set of CCU PLLs. There are five PLLs
- to create a clock for the MIPS P5600 cores, the embedded DDR controller,
- SATA, Ethernet and PCIe domains. The last three domains though named by the
- biggest system interfaces in fact include nearly all of the rest SoC
- peripherals. Each of the PLLs is based on True Circuits TSMC CLN28HPM core
- with an interface wrapper (so called safe PLL' clocks switcher) to simplify
- the PLL configuration procedure. The PLLs work as depicted on the next
- diagram:
-
- +--------------------------+
- | |
- +-->+---+ +---+ +---+ | +---+ 0|\
- CLKF--->|/NF|--->|PFD|...|VCO|-+->|/OD|--->| |
- +---+ +->+---+ +---+ /->+---+ | |--->CLKOUT
- CLKOD---------C----------------+ 1| |
- +--------C--------------------------->|/
- | | ^
- Rclk-+->+---+ | |
- CLKR--->|/NR|-+ |
- +---+ |
- BYPASS--------------------------------------+
- BWADJ--->
-
- where Rclk is the reference clock coming from XTAL, NR - reference clock
- divider, NF - PLL clock multiplier, OD - VCO output clock divider, CLKOUT -
- output clock, BWADJ is the PLL bandwidth adjustment parameter. At this moment
- the binding supports the PLL dividers configuration in accordance with a
- requested rate, while bypassing and bandwidth adjustment settings can be
- added in future if it gets to be necessary.
-
- The PLLs CLKOUT is then either directly connected with the corresponding
- clocks consumer (like P5600 cores or DDR controller) or passed over a CCU
- divider to create a signal required for the clock domain.
-
- The CCU PLL dts-node uses the common clock bindings with no custom
- parameters. The list of exported clocks can be found in
- 'include/dt-bindings/clock/bt1-ccu.h'. Since CCU PLL is a part of the
- Baikal-T1 SoC System Controller its DT node is supposed to be a child of
- later one.
-
-properties:
- compatible:
- const: baikal,bt1-ccu-pll
-
- reg:
- maxItems: 1
-
- "#clock-cells":
- const: 1
-
- clocks:
- description: External reference clock
- maxItems: 1
-
- clock-names:
- const: ref_clk
-
-additionalProperties: false
-
-required:
- - compatible
- - "#clock-cells"
- - clocks
- - clock-names
-
-examples:
- # Clock Control Unit PLL node:
- - |
- clock-controller@1f04d000 {
- compatible = "baikal,bt1-ccu-pll";
- reg = <0x1f04d000 0x028>;
- #clock-cells = <1>;
-
- clocks = <&clk25m>;
- clock-names = "ref_clk";
- };
- # Required external oscillator:
- - |
- clk25m: clock-oscillator-25m {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "clk25m";
- };
-...
diff --git a/Bindings/clock/eswin,eic7700-clock.yaml b/Bindings/clock/eswin,eic7700-clock.yaml
new file mode 100644
index 0000000..3125ae5
--- /dev/null
+++ b/Bindings/clock/eswin,eic7700-clock.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/eswin,eic7700-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Eswin EIC7700 SoC clock controller
+
+maintainers:
+ - Yifeng Huang <huangyifeng@eswincomputing.com>
+ - Xuyang Dong <dongxuyang@eswincomputing.com>
+
+description:
+ The clock controller generates and supplies clock to all the modules
+ for eic7700 SoC.
+
+properties:
+ compatible:
+ const: eswin,eic7700-clock
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: External 24MHz oscillator clock
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@51828000 {
+ compatible = "eswin,eic7700-clock";
+ reg = <0x51828000 0x300>;
+ clocks = <&xtal24m>;
+ #clock-cells = <1>;
+ };
diff --git a/Bindings/clock/fsl,sai-clock.yaml b/Bindings/clock/fsl,sai-clock.yaml
index 3bca9d1..041a63f 100644
--- a/Bindings/clock/fsl,sai-clock.yaml
+++ b/Bindings/clock/fsl,sai-clock.yaml
@@ -10,10 +10,10 @@
- Michael Walle <michael@walle.cc>
description: |
- It is possible to use the BCLK pin of a SAI module as a generic clock
- output. Some SoC are very constrained in their pin multiplexer
- configuration. Eg. pins can only be changed groups. For example, on the
- LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
+ It is possible to use the BCLK or MCLK pin of a SAI module as a generic
+ clock output. Some SoC are very constrained in their pin multiplexer
+ configuration. E.g. pins can only be changed in groups. For example, on
+ the LS1028A SoC you can only enable SAIs in pairs. If you use only one SAI,
the second pins are wasted. Using this binding it is possible to use the
clock of the second SAI as a MCLK clock for an audio codec, for example.
@@ -21,16 +21,45 @@
properties:
compatible:
- const: fsl,vf610-sai-clock
+ oneOf:
+ - items:
+ - enum:
+ - fsl,imx8mm-sai-clock
+ - fsl,imx8mn-sai-clock
+ - fsl,imx8mp-sai-clock
+ - const: fsl,imx8mq-sai-clock
+ - items:
+ - enum:
+ - fsl,imx8mq-sai-clock
+ - fsl,vf610-sai-clock
reg:
maxItems: 1
clocks:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
+
+ clock-names:
+ minItems: 1
+ items:
+ - const: bus
+ - const: mclk1
'#clock-cells':
- const: 0
+ maximum: 1
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,vf610-sai-clock
+ then:
+ properties:
+ clocks:
+ maxItems: 1
+ clock-names: false
required:
- compatible
diff --git a/Bindings/clock/imx6q-clock.yaml b/Bindings/clock/imx6q-clock.yaml
index cd3c04c..0e6febe 100644
--- a/Bindings/clock/imx6q-clock.yaml
+++ b/Bindings/clock/imx6q-clock.yaml
@@ -29,20 +29,24 @@
const: 1
clocks:
+ minItems: 5
items:
- description: 24m osc
- description: 32k osc
- description: ckih1 clock input
- description: anaclk1 clock input
- description: anaclk2 clock input
+ - description: clock input from enet ref pad
clock-names:
+ minItems: 5
items:
- const: osc
- const: ckil
- const: ckih1
- const: anaclk1
- const: anaclk2
+ - const: enet_ref_pad
fsl,pmic-stby-poweroff:
$ref: /schemas/types.yaml#/definitions/flag
diff --git a/Bindings/clock/imx6ul-clock.yaml b/Bindings/clock/imx6ul-clock.yaml
index d57e18a..0350027 100644
--- a/Bindings/clock/imx6ul-clock.yaml
+++ b/Bindings/clock/imx6ul-clock.yaml
@@ -29,18 +29,22 @@
const: 1
clocks:
+ minItems: 4
items:
- description: 32k osc
- description: 24m osc
- description: ipp_di0 clock input
- description: ipp_di1 clock input
+ - description: clock input from enet1 ref pad
clock-names:
+ minItems: 4
items:
- const: ckil
- const: osc
- const: ipp_di0
- const: ipp_di1
+ - const: enet1_ref_pad
required:
- compatible
diff --git a/Bindings/clock/qcom,eliza-dispcc.yaml b/Bindings/clock/qcom,eliza-dispcc.yaml
new file mode 100644
index 0000000..0935ec1
--- /dev/null
+++ b/Bindings/clock/qcom,eliza-dispcc.yaml
@@ -0,0 +1,96 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,eliza-dispcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Display Clock & Reset Controller for Qualcomm Eliza SoC
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Konrad Dybcio <konradybcio@kernel.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
+
+description: |
+ Display clock control module provides the clocks, resets and power
+ domains on Qualcomm Eliza SoC platform.
+
+ See also:
+ - include/dt-bindings/clock/qcom,eliza-dispcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,eliza-dispcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board Always On XO source
+ - description: Display's AHB clock
+ - description: sleep clock
+ - description: Byte clock from DSI PHY0
+ - description: Pixel clock from DSI PHY0
+ - description: Byte clock from DSI PHY1
+ - description: Pixel clock from DSI PHY1
+ - description: Link clock from DP PHY0
+ - description: VCO DIV clock from DP PHY0
+ - description: Link clock from DP PHY1
+ - description: VCO DIV clock from DP PHY1
+ - description: Link clock from DP PHY2
+ - description: VCO DIV clock from DP PHY2
+ - description: Link clock from DP PHY3
+ - description: VCO DIV clock from DP PHY3
+ - description: HDMI link clock from HDMI PHY
+
+ power-domains:
+ maxItems: 1
+
+ required-opps:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,dsi-phy-28nm.h>
+ #include <dt-bindings/clock/qcom,eliza-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
+ clock-controller@af00000 {
+ compatible = "qcom,eliza-dispcc";
+ reg = <0x0af00000 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <&dsi0_phy DSI_BYTE_PLL_CLK>,
+ <&dsi0_phy DSI_PIXEL_PLL_CLK>,
+ <&dsi1_phy DSI_BYTE_PLL_CLK>,
+ <&dsi1_phy DSI_PIXEL_PLL_CLK>,
+ <&dp0_phy 0>,
+ <&dp0_phy 1>,
+ <&dp1_phy 0>,
+ <&dp1_phy 1>,
+ <&dp2_phy 0>,
+ <&dp2_phy 1>,
+ <&dp3_phy 0>,
+ <&dp3_phy 1>,
+ <&hdmi_phy>;
+
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+...
diff --git a/Bindings/clock/qcom,glymur-dispcc.yaml b/Bindings/clock/qcom,glymur-dispcc.yaml
index 45f027c..9de4ba7 100644
--- a/Bindings/clock/qcom,glymur-dispcc.yaml
+++ b/Bindings/clock/qcom,glymur-dispcc.yaml
@@ -4,14 +4,14 @@
$id: http://devicetree.org/schemas/clock/qcom,glymur-dispcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Display Clock & Reset Controller on GLYMUR
+title: Qualcomm Display Clock & Reset Controller on Glymur SoC
maintainers:
- Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm display clock control module which supports the clocks, resets and
- power domains for the MDSS instances on GLYMUR SoC.
+ power domains for the MDSS instances on Glymur SoC.
See also:
include/dt-bindings/clock/qcom,dispcc-glymur.h
diff --git a/Bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
index 817d511..de338c0 100644
--- a/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
+++ b/Bindings/clock/qcom,ipq9574-cmn-pll.yaml
@@ -26,6 +26,8 @@
enum:
- qcom,ipq5018-cmn-pll
- qcom,ipq5424-cmn-pll
+ - qcom,ipq6018-cmn-pll
+ - qcom,ipq8074-cmn-pll
- qcom,ipq9574-cmn-pll
reg:
diff --git a/Bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Bindings/clock/qcom,kaanapali-gxclkctl.yaml
index 5490a97..466c884 100644
--- a/Bindings/clock/qcom,kaanapali-gxclkctl.yaml
+++ b/Bindings/clock/qcom,kaanapali-gxclkctl.yaml
@@ -20,7 +20,9 @@
properties:
compatible:
enum:
+ - qcom,glymur-gxclkctl
- qcom,kaanapali-gxclkctl
+ - qcom,sm8750-gxclkctl
power-domains:
description:
diff --git a/Bindings/clock/qcom,milos-gcc.yaml b/Bindings/clock/qcom,milos-gcc.yaml
index 60f1c8ca..c65a6ad 100644
--- a/Bindings/clock/qcom,milos-gcc.yaml
+++ b/Bindings/clock/qcom,milos-gcc.yaml
@@ -35,9 +35,14 @@
- description: UFS Phy Tx symbol 0 clock source
- description: USB3 Phy wrapper pipe clock source
+ power-domains:
+ items:
+ - description: CX domain
+
required:
- compatible
- clocks
+ - power-domains
- '#power-domain-cells'
allOf:
@@ -48,6 +53,7 @@
examples:
- |
#include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/power/qcom,rpmhpd.h>
clock-controller@100000 {
compatible = "qcom,milos-gcc";
reg = <0x00100000 0x1f4200>;
@@ -59,6 +65,7 @@
<&ufs_mem_phy 1>,
<&ufs_mem_phy 2>,
<&usb_1_qmpphy>;
+ power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
#reset-cells = <1>;
#power-domain-cells = <1>;
diff --git a/Bindings/clock/qcom,nord-gcc.yaml b/Bindings/clock/qcom,nord-gcc.yaml
new file mode 100644
index 0000000..e351367
--- /dev/null
+++ b/Bindings/clock/qcom,nord-gcc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-gcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: PCIE A Pipe clock source
+ - description: PCIE B Pipe clock source
+ - description: PCIE C Pipe clock source
+ - description: PCIE D Pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,nord-gcc";
+ reg = <0x00100000 0x1f4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&pcie_a_pipe_clk>,
+ <&pcie_b_pipe_clk>,
+ <&pcie_c_pipe_clk>,
+ <&pcie_d_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Bindings/clock/qcom,nord-negcc.yaml b/Bindings/clock/qcom,nord-negcc.yaml
new file mode 100644
index 0000000..749389f
--- /dev/null
+++ b/Bindings/clock/qcom,nord-negcc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-negcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North East Clock & Reset Controller on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also: include/dt-bindings/clock/qcom,nord-negcc.h
+
+properties:
+ compatible:
+ const: qcom,nord-negcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: UFS Phy Rx symbol 0 clock source
+ - description: UFS Phy Rx symbol 1 clock source
+ - description: UFS Phy Tx symbol 0 clock source
+ - description: USB3 Phy sec wrapper pipe clock source
+ - description: USB3 Phy wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8900000 {
+ compatible = "qcom,nord-negcc";
+ reg = <0x08900000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>,
+ <&ufs_phy_rx_symbol_0_clk>,
+ <&ufs_phy_rx_symbol_1_clk>,
+ <&ufs_phy_tx_symbol_0_clk>,
+ <&usb3_phy_sec_pipe_clk>,
+ <&usb3_phy_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Bindings/clock/qcom,nord-nwgcc.yaml b/Bindings/clock/qcom,nord-nwgcc.yaml
new file mode 100644
index 0000000..ce33f96
--- /dev/null
+++ b/Bindings/clock/qcom,nord-nwgcc.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,nord-nwgcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global North West and South East Clock & Reset Controller
+ on Nord SoC
+
+maintainers:
+ - Taniya Das <taniya.das@oss.qualcomm.com>
+
+description: |
+ Qualcomm global clock control (NW, SE) module provides the clocks, resets
+ and power domains on Nord SoC.
+
+ See also:
+ include/dt-bindings/clock/qcom,nord-nwgcc.h
+ include/dt-bindings/clock/qcom,nord-segcc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,nord-nwgcc
+ - qcom,nord-segcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+
+required:
+ - compatible
+ - clocks
+ - '#power-domain-cells'
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@8b00000 {
+ compatible = "qcom,nord-nwgcc";
+ reg = <0x08b00000 0xf4200>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
+...
diff --git a/Bindings/clock/qcom,rpmhcc.yaml b/Bindings/clock/qcom,rpmhcc.yaml
index 9690169..a2c404a 100644
--- a/Bindings/clock/qcom,rpmhcc.yaml
+++ b/Bindings/clock/qcom,rpmhcc.yaml
@@ -21,6 +21,7 @@
- qcom,glymur-rpmh-clk
- qcom,kaanapali-rpmh-clk
- qcom,milos-rpmh-clk
+ - qcom,nord-rpmh-clk
- qcom,qcs615-rpmh-clk
- qcom,qdu1000-rpmh-clk
- qcom,sa8775p-rpmh-clk
diff --git a/Bindings/clock/qcom,sm8450-gpucc.yaml b/Bindings/clock/qcom,sm8450-gpucc.yaml
index 6feaa32..fdbdf60 100644
--- a/Bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Bindings/clock/qcom,sm8450-gpucc.yaml
@@ -8,12 +8,14 @@
maintainers:
- Konrad Dybcio <konradybcio@kernel.org>
+ - Taniya Das <taniya.das@oss.qualcomm.com>
description: |
Qualcomm graphics clock control module provides the clocks, resets and power
domains on Qualcomm SoCs.
- See also::
+ See also:
+ include/dt-bindings/clock/qcom,glymur-gpucc.h
include/dt-bindings/clock/qcom,kaanapali-gpucc.h
include/dt-bindings/clock/qcom,milos-gpucc.h
include/dt-bindings/clock/qcom,sar2130p-gpucc.h
@@ -22,11 +24,13 @@
include/dt-bindings/clock/qcom,sm8550-gpucc.h
include/dt-bindings/reset/qcom,sm8450-gpucc.h
include/dt-bindings/reset/qcom,sm8650-gpucc.h
+ include/dt-bindings/reset/qcom,sm8750-gpucc.h
include/dt-bindings/reset/qcom,x1e80100-gpucc.h
properties:
compatible:
enum:
+ - qcom,glymur-gpucc
- qcom,kaanapali-gpucc
- qcom,milos-gpucc
- qcom,sar2130p-gpucc
@@ -35,6 +39,7 @@
- qcom,sm8475-gpucc
- qcom,sm8550-gpucc
- qcom,sm8650-gpucc
+ - qcom,sm8750-gpucc
- qcom,x1e80100-gpucc
- qcom,x1p42100-gpucc
@@ -44,6 +49,16 @@
- description: GPLL0 main branch source
- description: GPLL0 div branch source
+ power-domains:
+ items:
+ - description: A phandle to the MX power-domain
+ - description: A phandle to the CX power-domain
+
+ required-opps:
+ items:
+ - description: A phandle to an OPP node describing MX performance points
+ - description: A phandle to an OPP node describing CX performance points
+
required:
- compatible
- clocks
@@ -51,6 +66,16 @@
allOf:
- $ref: qcom,gcc.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8750-gpucc
+ then:
+ required:
+ - power-domains
+ - required-opps
unevaluatedProperties: false
diff --git a/Bindings/clock/qcom,sm8450-videocc.yaml b/Bindings/clock/qcom,sm8450-videocc.yaml
index e6beebd..7bbf120 100644
--- a/Bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Bindings/clock/qcom,sm8450-videocc.yaml
@@ -15,6 +15,7 @@
domains on SM8450.
See also:
+ include/dt-bindings/clock/qcom,glymur-videocc.h
include/dt-bindings/clock/qcom,kaanapali-videocc.h
include/dt-bindings/clock/qcom,sm8450-videocc.h
include/dt-bindings/clock/qcom,sm8650-videocc.h
@@ -23,6 +24,7 @@
properties:
compatible:
enum:
+ - qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8475-videocc
@@ -63,6 +65,7 @@
compatible:
contains:
enum:
+ - qcom,glymur-videocc
- qcom,kaanapali-videocc
- qcom,sm8450-videocc
- qcom,sm8550-videocc
diff --git a/Bindings/clock/qcom,sm8550-tcsr.yaml b/Bindings/clock/qcom,sm8550-tcsr.yaml
index ae9aef0..1ccdf4b 100644
--- a/Bindings/clock/qcom,sm8550-tcsr.yaml
+++ b/Bindings/clock/qcom,sm8550-tcsr.yaml
@@ -17,6 +17,7 @@
See also:
- include/dt-bindings/clock/qcom,eliza-tcsr.h
- include/dt-bindings/clock/qcom,glymur-tcsr.h
+ - include/dt-bindings/clock/qcom,nord-tcsrcc.h
- include/dt-bindings/clock/qcom,sm8550-tcsr.h
- include/dt-bindings/clock/qcom,sm8650-tcsr.h
- include/dt-bindings/clock/qcom,sm8750-tcsr.h
@@ -29,6 +30,7 @@
- qcom,glymur-tcsr
- qcom,kaanapali-tcsr
- qcom,milos-tcsr
+ - qcom,nord-tcsrcc
- qcom,sar2130p-tcsr
- qcom,sm8550-tcsr
- qcom,sm8650-tcsr
diff --git a/Bindings/clock/samsung,exynosautov920-clock.yaml b/Bindings/clock/samsung,exynosautov920-clock.yaml
index 1318720..6b1fc61a 100644
--- a/Bindings/clock/samsung,exynosautov920-clock.yaml
+++ b/Bindings/clock/samsung,exynosautov920-clock.yaml
@@ -35,6 +35,7 @@
- samsung,exynosautov920-cmu-cpucl0
- samsung,exynosautov920-cmu-cpucl1
- samsung,exynosautov920-cmu-cpucl2
+ - samsung,exynosautov920-cmu-g3d
- samsung,exynosautov920-cmu-hsi0
- samsung,exynosautov920-cmu-hsi1
- samsung,exynosautov920-cmu-hsi2
@@ -287,6 +288,26 @@
- const: oscclk
- const: noc
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynosautov920-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (38.4 MHz)
+ - description: CMU_G3D SWITCH clock (from CMU_TOP)
+ - description: CMU_G3D NOCP clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: switch
+ - const: nocp
+
required:
- compatible
- "#clock-cells"
diff --git a/Bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml b/Bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
new file mode 100644
index 0000000..7fa1652
--- /dev/null
+++ b/Bindings/clock/tenstorrent,atlantis-prcm-rcpu.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/tenstorrent,atlantis-prcm-rcpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Tenstorrent Atlantis PRCM (Power, Reset, Clock Management) Module
+
+maintainers:
+ - Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
+
+description:
+ Multifunctional register block found in Tenstorrent Atlantis SoC whose main
+ function is to control clocks and resets. This block is instantiated multiple
+ times in the SoC, each block controls clock and resets for a different
+ subsystem. RCPU prcm serves low speed IO interfaces.
+
+properties:
+ compatible:
+ enum:
+ - tenstorrent,atlantis-prcm-rcpu
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+ description:
+ See <dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h> for valid indices.
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@a8000000 {
+ compatible = "tenstorrent,atlantis-prcm-rcpu";
+ reg = <0xa8000000 0x10000>;
+ clocks = <&osc_24m>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/mfd/syscon.yaml b/Bindings/mfd/syscon.yaml
index e57add2..e228670 100644
--- a/Bindings/mfd/syscon.yaml
+++ b/Bindings/mfd/syscon.yaml
@@ -61,6 +61,7 @@
- cirrus,ep7209-syscon2
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
+ - econet,en751221-chip-scu
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
@@ -173,6 +174,7 @@
- cirrus,ep7209-syscon2
- cirrus,ep7209-syscon3
- cnxt,cx92755-uc
+ - econet,en751221-chip-scu
- freecom,fsg-cs2-system-controller
- fsl,imx93-aonmix-ns-syscfg
- fsl,imx93-wakeupmix-syscfg
diff --git a/include/dt-bindings/clock/bt1-ccu.h b/include/dt-bindings/clock/bt1-ccu.h
deleted file mode 100644
index 5f166d2..0000000
--- a/include/dt-bindings/clock/bt1-ccu.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-/*
- * Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
- *
- * Baikal-T1 CCU clock indices
- */
-#ifndef __DT_BINDINGS_CLOCK_BT1_CCU_H
-#define __DT_BINDINGS_CLOCK_BT1_CCU_H
-
-#define CCU_CPU_PLL 0
-#define CCU_SATA_PLL 1
-#define CCU_DDR_PLL 2
-#define CCU_PCIE_PLL 3
-#define CCU_ETH_PLL 4
-
-#define CCU_AXI_MAIN_CLK 0
-#define CCU_AXI_DDR_CLK 1
-#define CCU_AXI_SATA_CLK 2
-#define CCU_AXI_GMAC0_CLK 3
-#define CCU_AXI_GMAC1_CLK 4
-#define CCU_AXI_XGMAC_CLK 5
-#define CCU_AXI_PCIE_M_CLK 6
-#define CCU_AXI_PCIE_S_CLK 7
-#define CCU_AXI_USB_CLK 8
-#define CCU_AXI_HWA_CLK 9
-#define CCU_AXI_SRAM_CLK 10
-
-#define CCU_SYS_SATA_REF_CLK 0
-#define CCU_SYS_APB_CLK 1
-#define CCU_SYS_GMAC0_TX_CLK 2
-#define CCU_SYS_GMAC0_PTP_CLK 3
-#define CCU_SYS_GMAC1_TX_CLK 4
-#define CCU_SYS_GMAC1_PTP_CLK 5
-#define CCU_SYS_XGMAC_REF_CLK 6
-#define CCU_SYS_XGMAC_PTP_CLK 7
-#define CCU_SYS_USB_CLK 8
-#define CCU_SYS_PVT_CLK 9
-#define CCU_SYS_HWA_CLK 10
-#define CCU_SYS_UART_CLK 11
-#define CCU_SYS_I2C1_CLK 12
-#define CCU_SYS_I2C2_CLK 13
-#define CCU_SYS_GPIO_CLK 14
-#define CCU_SYS_TIMER0_CLK 15
-#define CCU_SYS_TIMER1_CLK 16
-#define CCU_SYS_TIMER2_CLK 17
-#define CCU_SYS_WDT_CLK 18
-
-#endif /* __DT_BINDINGS_CLOCK_BT1_CCU_H */
diff --git a/include/dt-bindings/clock/econet,en751221-scu.h b/include/dt-bindings/clock/econet,en751221-scu.h
new file mode 100644
index 0000000..318ec8a
--- /dev/null
+++ b/include/dt-bindings/clock/econet,en751221-scu.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+#define _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_
+
+#define EN751221_CLK_PCIE 0
+#define EN751221_CLK_SPI 1
+#define EN751221_CLK_BUS 2
+#define EN751221_CLK_CPU 3
+#define EN751221_CLK_GSW 4
+
+#endif /* _DT_BINDINGS_CLOCK_ECONET_EN751221_SCU_H_ */
diff --git a/include/dt-bindings/clock/eswin,eic7700-clock.h b/include/dt-bindings/clock/eswin,eic7700-clock.h
new file mode 100644
index 0000000..d7ef697
--- /dev/null
+++ b/include/dt-bindings/clock/eswin,eic7700-clock.h
@@ -0,0 +1,285 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright 2026, Beijing ESWIN Computing Technology Co., Ltd..
+ * All rights reserved.
+ *
+ * Device Tree binding constants for EIC7700 clock controller.
+ *
+ * Authors:
+ * Yifeng Huang <huangyifeng@eswincomputing.com>
+ * Xuyang Dong <dongxuyang@eswincomputing.com>
+ */
+
+#ifndef _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+#define _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_
+
+#define EIC7700_CLK_XTAL_32K 0
+#define EIC7700_CLK_PLL_CPU 1
+#define EIC7700_CLK_SPLL0_FOUT1 2
+#define EIC7700_CLK_SPLL0_FOUT2 3
+#define EIC7700_CLK_SPLL0_FOUT3 4
+#define EIC7700_CLK_SPLL1_FOUT1 5
+#define EIC7700_CLK_SPLL1_FOUT2 6
+#define EIC7700_CLK_SPLL1_FOUT3 7
+#define EIC7700_CLK_SPLL2_FOUT1 8
+#define EIC7700_CLK_SPLL2_FOUT2 9
+#define EIC7700_CLK_SPLL2_FOUT3 10
+#define EIC7700_CLK_VPLL_FOUT1 11
+#define EIC7700_CLK_VPLL_FOUT2 12
+#define EIC7700_CLK_VPLL_FOUT3 13
+#define EIC7700_CLK_APLL_FOUT1 14
+#define EIC7700_CLK_APLL_FOUT2 15
+#define EIC7700_CLK_APLL_FOUT3 16
+#define EIC7700_CLK_EXT_MCLK 17
+#define EIC7700_CLK_LPDDR_REF_BAK 18
+#define EIC7700_CLK_MUX_CPU_ROOT_3MUX1_GFREE 19
+#define EIC7700_CLK_MUX_CPU_ACLK_2MUX1_GFREE 20
+#define EIC7700_CLK_MUX_DSP_ACLK_ROOT_2MUX1_GFREE 21
+#define EIC7700_CLK_MUX_D2D_ACLK_ROOT_2MUX1_GFREE 22
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_0 23
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_1 24
+#define EIC7700_CLK_MUX_MSHCORE_ROOT_3MUX1_2 25
+#define EIC7700_CLK_MUX_NPU_LLCLK_3MUX1_GFREE 26
+#define EIC7700_CLK_MUX_NPU_CORE_3MUX1_GFREE 27
+#define EIC7700_CLK_MUX_VI_ACLK_ROOT_2MUX1_GFREE 28
+#define EIC7700_CLK_MUX_VI_DVP_ROOT_2MUX1_GFREE 29
+#define EIC7700_CLK_MUX_VI_DIG_ISP_ROOT_2MUX1_GFREE 30
+#define EIC7700_CLK_MUX_VO_ACLK_ROOT_2MUX1_GFREE 31
+#define EIC7700_CLK_MUX_VO_PIXEL_ROOT_2MUX1 32
+#define EIC7700_CLK_MUX_VCDEC_ROOT_2MUX1_GFREE 33
+#define EIC7700_CLK_MUX_VCACLK_ROOT_2MUX1_GFREE 34
+#define EIC7700_CLK_MUX_SATA_PHY_2MUX1 35
+#define EIC7700_CLK_MUX_BOOTSPI_CLK_2MUX1_GFREE 36
+#define EIC7700_CLK_MUX_SCPU_CORE_CLK_2MUX1_GFREE 37
+#define EIC7700_CLK_MUX_LPCPU_CORE_CLK_2MUX1_GFREE 38
+#define EIC7700_CLK_MUX_VO_MCLK_2MUX_EXT_MCLK 39
+#define EIC7700_CLK_MUX_SYSCFG_CLK_ROOT_2MUX1_GFREE 40
+#define EIC7700_CLK_MUX_AONDMA_AXI2MUX1_GFREE 41
+#define EIC7700_CLK_MUX_RMII_REF_2MUX 42
+#define EIC7700_CLK_MUX_ETH_CORE_2MUX1 43
+#define EIC7700_CLK_MUX_VI_DW_ROOT_2MUX1 44
+#define EIC7700_CLK_MUX_NPU_E31_3MUX1_GFREE 45
+#define EIC7700_CLK_MUX_DDR_ACLK_ROOT_2MUX1_GFREE 46
+#define EIC7700_CLK_DIV_SYS_CFG_DYNM 47
+#define EIC7700_CLK_DIV_NOC_NSP_DYNM 48
+#define EIC7700_CLK_DIV_BOOTSPI_DYNM 49
+#define EIC7700_CLK_DIV_SCPU_CORE_DYNM 50
+#define EIC7700_CLK_DIV_LPCPU_CORE_DYNM 51
+#define EIC7700_CLK_DIV_GPU_ACLK_DYNM 52
+#define EIC7700_CLK_DIV_DSP_ACLK_DYNM 53
+#define EIC7700_CLK_DIV_D2D_ACLK_DYNM 54
+#define EIC7700_CLK_DIV_HSP_ACLK_DYNM 55
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_0 56
+#define EIC7700_CLK_DIV_ETH_TXCLK_DYNM_1 57
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_0 58
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_1 59
+#define EIC7700_CLK_DIV_MSHC_CORE_DYNM_2 60
+#define EIC7700_CLK_DIV_PCIE_ACLK_DYNM 61
+#define EIC7700_CLK_DIV_NPU_ACLK_DYNM 62
+#define EIC7700_CLK_DIV_NPU_LLC_SRC0_DYNM 63
+#define EIC7700_CLK_DIV_NPU_LLC_SRC1_DYNM 64
+#define EIC7700_CLK_DIV_NPU_CORECLK_DYNM 65
+#define EIC7700_CLK_DIV_VI_ACLK_DYNM 66
+#define EIC7700_CLK_DIV_VI_DVP_DYNM 67
+#define EIC7700_CLK_DIV_VI_DIG_ISP_DYNM 68
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_0 69
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_1 70
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_2 71
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_3 72
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_4 73
+#define EIC7700_CLK_DIV_VI_SHUTTER_DYNM_5 74
+#define EIC7700_CLK_DIV_VO_ACLK_DYNM 75
+#define EIC7700_CLK_DIV_IESMCLK_DYNM 76
+#define EIC7700_CLK_DIV_VO_PIXEL_DYNM 77
+#define EIC7700_CLK_DIV_VO_MCLK_DYNM 78
+#define EIC7700_CLK_DIV_VC_ACLK_DYNM 79
+#define EIC7700_CLK_DIV_JD_DYNM 80
+#define EIC7700_CLK_DIV_JE_DYNM 81
+#define EIC7700_CLK_DIV_VE_DYNM 82
+#define EIC7700_CLK_DIV_VD_DYNM 83
+#define EIC7700_CLK_DIV_G2D_DYNM 84
+#define EIC7700_CLK_DIV_AONDMA_AXI_DYNM 85
+#define EIC7700_CLK_DIV_CRYPTO_DYNM 86
+#define EIC7700_CLK_DIV_VI_DW_DYNM 87
+#define EIC7700_CLK_DIV_NPU_E31_DYNM 88
+#define EIC7700_CLK_DIV_SATA_PHY_REF_DYNM 89
+#define EIC7700_CLK_DIV_DSP_0_ACLK_DYNM 90
+#define EIC7700_CLK_DIV_DSP_1_ACLK_DYNM 91
+#define EIC7700_CLK_DIV_DSP_2_ACLK_DYNM 92
+#define EIC7700_CLK_DIV_DSP_3_ACLK_DYNM 93
+#define EIC7700_CLK_DIV_DDR_ACLK_DYNM 94
+#define EIC7700_CLK_DIV_AON_RTC_DYNM 95
+#define EIC7700_CLK_DIV_U84_RTC_TOGGLE_DYNM 96
+#define EIC7700_CLK_DIV_VO_CEC_DYNM 97
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_0 98
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_1 99
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_2 100
+#define EIC7700_CLK_GATE_CPU_EXT_SRC_CORE_CLK_3 101
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_0 102
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_1 103
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_2 104
+#define EIC7700_CLK_GATE_CPU_TRACE_CLK_3 105
+#define EIC7700_CLK_GATE_CPU_TRACE_COM_CLK 106
+#define EIC7700_CLK_GATE_SPLL0_FOUT2 107
+#define EIC7700_CLK_GATE_NOC_NSP_CLK 108
+#define EIC7700_CLK_GATE_BOOTSPI 109
+#define EIC7700_CLK_GATE_BOOTSPI_CFG 110
+#define EIC7700_CLK_GATE_SCPU_CORE 111
+#define EIC7700_CLK_GATE_SCPU_BUS 112
+#define EIC7700_CLK_GATE_LPCPU_CORE 113
+#define EIC7700_CLK_GATE_LPCPU_BUS 114
+#define EIC7700_CLK_GATE_GPU_ACLK 115
+#define EIC7700_CLK_GATE_GPU_GRAY_CLK 116
+#define EIC7700_CLK_GATE_GPU_CFG_CLK 117
+#define EIC7700_CLK_GATE_DSPT_ACLK 118
+#define EIC7700_CLK_GATE_DSPT_CFG_CLK 119
+#define EIC7700_CLK_GATE_D2D_ACLK 120
+#define EIC7700_CLK_GATE_D2D_CFG_CLK 121
+#define EIC7700_CLK_GATE_TCU_ACLK 122
+#define EIC7700_CLK_GATE_TCU_CFG_CLK 123
+#define EIC7700_CLK_GATE_DDRT_CFG_CLK 124
+#define EIC7700_CLK_GATE_DDRT0_P0_ACLK 125
+#define EIC7700_CLK_GATE_DDRT0_P1_ACLK 126
+#define EIC7700_CLK_GATE_DDRT0_P2_ACLK 127
+#define EIC7700_CLK_GATE_DDRT0_P3_ACLK 128
+#define EIC7700_CLK_GATE_DDRT0_P4_ACLK 129
+#define EIC7700_CLK_GATE_DDRT1_P0_ACLK 130
+#define EIC7700_CLK_GATE_DDRT1_P1_ACLK 131
+#define EIC7700_CLK_GATE_DDRT1_P2_ACLK 132
+#define EIC7700_CLK_GATE_DDRT1_P3_ACLK 133
+#define EIC7700_CLK_GATE_DDRT1_P4_ACLK 134
+#define EIC7700_CLK_GATE_TIMER_CLK_0 135
+#define EIC7700_CLK_GATE_TIMER_CLK_1 136
+#define EIC7700_CLK_GATE_TIMER_CLK_2 137
+#define EIC7700_CLK_GATE_TIMER_CLK_3 138
+#define EIC7700_CLK_GATE_TIMER_PCLK_0 139
+#define EIC7700_CLK_GATE_TIMER_PCLK_1 140
+#define EIC7700_CLK_GATE_TIMER_PCLK_2 141
+#define EIC7700_CLK_GATE_TIMER_PCLK_3 142
+#define EIC7700_CLK_GATE_TIMER3_CLK8 143
+#define EIC7700_CLK_GATE_PCIET_ACLK 144
+#define EIC7700_CLK_GATE_PCIET_CFG_CLK 145
+#define EIC7700_CLK_GATE_PCIET_CR_CLK 146
+#define EIC7700_CLK_GATE_PCIET_AUX_CLK 147
+#define EIC7700_CLK_GATE_NPU_ACLK 148
+#define EIC7700_CLK_GATE_NPU_CFG_CLK 149
+#define EIC7700_CLK_GATE_NPU_LLC_ACLK 150
+#define EIC7700_CLK_GATE_NPU_CLK 151
+#define EIC7700_CLK_GATE_NPU_E31_CLK 152
+#define EIC7700_CLK_GATE_VI_ACLK 153
+#define EIC7700_CLK_GATE_VI_DVP_CLK 154
+#define EIC7700_CLK_GATE_VI_CFG_CLK 155
+#define EIC7700_CLK_GATE_VI_DIG_DW_CLK 156
+#define EIC7700_CLK_GATE_VI_DIG_ISP_CLK 157
+#define EIC7700_CLK_GATE_VI_SHUTTER_0 158
+#define EIC7700_CLK_GATE_VI_SHUTTER_1 159
+#define EIC7700_CLK_GATE_VI_SHUTTER_2 160
+#define EIC7700_CLK_GATE_VI_SHUTTER_3 161
+#define EIC7700_CLK_GATE_VI_SHUTTER_4 162
+#define EIC7700_CLK_GATE_VI_SHUTTER_5 163
+#define EIC7700_CLK_GATE_VI_PHY_TXCLKESC 164
+#define EIC7700_CLK_GATE_VI_PHY_CFG 165
+#define EIC7700_CLK_GATE_VO_ACLK 166
+#define EIC7700_CLK_GATE_VO_CFG_CLK 167
+#define EIC7700_CLK_GATE_VO_HDMI_IESMCLK 168
+#define EIC7700_CLK_GATE_VO_PIXEL_CLK 169
+#define EIC7700_CLK_GATE_VO_I2S_MCLK 170
+#define EIC7700_CLK_GATE_HSP_CFG_CLK 171
+#define EIC7700_CLK_GATE_VC_ACLK 172
+#define EIC7700_CLK_GATE_VC_CFG_CLK 173
+#define EIC7700_CLK_GATE_VC_JE_CLK 174
+#define EIC7700_CLK_GATE_VC_JD_CLK 175
+#define EIC7700_CLK_GATE_VC_VE_CLK 176
+#define EIC7700_CLK_GATE_VC_VD_CLK 177
+#define EIC7700_CLK_GATE_G2D_CFG_CLK 178
+#define EIC7700_CLK_GATE_G2D_CLK 179
+#define EIC7700_CLK_GATE_G2D_ACLK 180
+#define EIC7700_CLK_GATE_AONDMA_CFG 181
+#define EIC7700_CLK_GATE_AONDMA_ACLK 182
+#define EIC7700_CLK_GATE_AON_ACLK 183
+#define EIC7700_CLK_GATE_HSP_SATA_RBC_CLK 184
+#define EIC7700_CLK_GATE_VO_CR_CLK 185
+#define EIC7700_CLK_GATE_HSP_ACLK 186
+#define EIC7700_CLK_GATE_HSP_SATA_OOB_CLK 187
+#define EIC7700_CLK_GATE_RTC_CFG 188
+#define EIC7700_CLK_GATE_RTC 189
+#define EIC7700_CLK_GATE_HSP_MSHC0_CORE_CLK 190
+#define EIC7700_CLK_GATE_HSP_MSHC1_CORE_CLK 191
+#define EIC7700_CLK_GATE_HSP_MSHC2_CORE_CLK 192
+#define EIC7700_CLK_GATE_HSP_ETH0_CORE_CLK 193
+#define EIC7700_CLK_GATE_HSP_ETH1_CORE_CLK 194
+#define EIC7700_CLK_GATE_HSP_RMII_REF_0 195
+#define EIC7700_CLK_GATE_HSP_RMII_REF_1 196
+#define EIC7700_CLK_GATE_PKA_CFG 197
+#define EIC7700_CLK_GATE_SPACC_CFG 198
+#define EIC7700_CLK_GATE_CRYPTO 199
+#define EIC7700_CLK_GATE_TRNG_CFG 200
+#define EIC7700_CLK_GATE_OTP_CFG 201
+#define EIC7700_CLK_GATE_MAILBOX_0 202
+#define EIC7700_CLK_GATE_MAILBOX_1 203
+#define EIC7700_CLK_GATE_MAILBOX_2 204
+#define EIC7700_CLK_GATE_MAILBOX_3 205
+#define EIC7700_CLK_GATE_MAILBOX_4 206
+#define EIC7700_CLK_GATE_MAILBOX_5 207
+#define EIC7700_CLK_GATE_MAILBOX_6 208
+#define EIC7700_CLK_GATE_MAILBOX_7 209
+#define EIC7700_CLK_GATE_MAILBOX_8 210
+#define EIC7700_CLK_GATE_MAILBOX_9 211
+#define EIC7700_CLK_GATE_MAILBOX_10 212
+#define EIC7700_CLK_GATE_MAILBOX_11 213
+#define EIC7700_CLK_GATE_MAILBOX_12 214
+#define EIC7700_CLK_GATE_MAILBOX_13 215
+#define EIC7700_CLK_GATE_MAILBOX_14 216
+#define EIC7700_CLK_GATE_MAILBOX_15 217
+#define EIC7700_CLK_GATE_LSP_I2C0_PCLK 218
+#define EIC7700_CLK_GATE_LSP_I2C1_PCLK 219
+#define EIC7700_CLK_GATE_LSP_I2C2_PCLK 220
+#define EIC7700_CLK_GATE_LSP_I2C3_PCLK 221
+#define EIC7700_CLK_GATE_LSP_I2C4_PCLK 222
+#define EIC7700_CLK_GATE_LSP_I2C5_PCLK 223
+#define EIC7700_CLK_GATE_LSP_I2C6_PCLK 224
+#define EIC7700_CLK_GATE_LSP_I2C7_PCLK 225
+#define EIC7700_CLK_GATE_LSP_I2C8_PCLK 226
+#define EIC7700_CLK_GATE_LSP_I2C9_PCLK 227
+#define EIC7700_CLK_GATE_LSP_WDT0_PCLK 228
+#define EIC7700_CLK_GATE_LSP_WDT1_PCLK 229
+#define EIC7700_CLK_GATE_LSP_WDT2_PCLK 230
+#define EIC7700_CLK_GATE_LSP_WDT3_PCLK 231
+#define EIC7700_CLK_GATE_LSP_SSI0_PCLK 232
+#define EIC7700_CLK_GATE_LSP_SSI1_PCLK 233
+#define EIC7700_CLK_GATE_LSP_PVT_PCLK 234
+#define EIC7700_CLK_GATE_AON_I2C0_PCLK 235
+#define EIC7700_CLK_GATE_AON_I2C1_PCLK 236
+#define EIC7700_CLK_GATE_LSP_UART0_PCLK 237
+#define EIC7700_CLK_GATE_LSP_UART1_PCLK 238
+#define EIC7700_CLK_GATE_LSP_UART2_PCLK 239
+#define EIC7700_CLK_GATE_LSP_UART3_PCLK 240
+#define EIC7700_CLK_GATE_LSP_UART4_PCLK 241
+#define EIC7700_CLK_GATE_LSP_TIMER_PCLK 242
+#define EIC7700_CLK_GATE_LSP_FAN_PCLK 243
+#define EIC7700_CLK_GATE_LSP_PVT0_CLK 244
+#define EIC7700_CLK_GATE_LSP_PVT1_CLK 245
+#define EIC7700_CLK_GATE_VC_JE_PCLK 246
+#define EIC7700_CLK_GATE_VC_JD_PCLK 247
+#define EIC7700_CLK_GATE_VC_VE_PCLK 248
+#define EIC7700_CLK_GATE_VC_VD_PCLK 249
+#define EIC7700_CLK_GATE_VC_MON_PCLK 250
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK 251
+#define EIC7700_CLK_GATE_HSP_DMA0_CLK_TEST 252
+#define EIC7700_CLK_FIXED_FACTOR_CPU_DIV2 253
+#define EIC7700_CLK_FIXED_FACTOR_CLK_1M_DIV24 254
+#define EIC7700_CLK_FIXED_FACTOR_MIPI_TXESC_DIV10 255
+#define EIC7700_CLK_FIXED_FACTOR_U84_CORE_LP_DIV2 256
+#define EIC7700_CLK_FIXED_FACTOR_SCPU_BUS_DIV2 257
+#define EIC7700_CLK_FIXED_FACTOR_LPCPU_BUS_DIV2 258
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_CR_DIV2 259
+#define EIC7700_CLK_FIXED_FACTOR_PCIE_AUX_DIV4 260
+#define EIC7700_CLK_FIXED_FACTOR_PVT_DIV20 261
+#define EIC7700_CLK_FIXED_FACTOR_HSP_RMII_REF_DIV6 262
+#define EIC7700_CLK_DIV_NOC_WDREF_DYNM 263
+#define EIC7700_CLK_GATE_DDR0_TRACE 264
+#define EIC7700_CLK_GATE_DDR1_TRACE 265
+#define EIC7700_CLK_GATE_RNOC_NSP 266
+#define EIC7700_CLK_GATE_NOC_WDREF 267
+
+#endif /* _DT_BINDINGS_ESWIN_EIC7700_CLOCK_H_ */
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 80dacda..9528558 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -126,6 +126,7 @@
#define CLK_GOUT_GPIO_ALIVE_PCLK 22
#define CLK_GOUT_PMU_ALIVE_PCLK 23
#define CLK_GOUT_SYSREG_APM_PCLK 24
+#define CLK_GOUT_MAILBOX_APM_AP_PCLK 25
/* CMU_AUD */
#define CLK_DOUT_AUD_AUDIF 1
diff --git a/include/dt-bindings/clock/qcom,dispcc-sc7180.h b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
index b9b51617..0705103 100644
--- a/include/dt-bindings/clock/qcom,dispcc-sc7180.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sc7180.h
@@ -6,6 +6,7 @@
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
+/* Clocks */
#define DISP_CC_PLL0 0
#define DISP_CC_PLL0_OUT_EVEN 1
#define DISP_CC_MDSS_AHB_CLK 2
@@ -40,7 +41,11 @@
#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
#define DISP_CC_XO_CLK 32
-/* DISP_CC GDSCR */
+/* Resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_RSCC_BCR 1
+
+/* GDSCs */
#define MDSS_GDSC 0
#endif
diff --git a/include/dt-bindings/clock/qcom,eliza-dispcc.h b/include/dt-bindings/clock/qcom,eliza-dispcc.h
new file mode 100644
index 0000000..30c6d85
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,eliza-dispcc.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+#define _DT_BINDINGS_CLK_QCOM_ELIZA_DISP_CC_H
+
+/* DISP_CC clocks */
+#define DISP_CC_PLL0 0
+#define DISP_CC_PLL1 1
+#define DISP_CC_PLL2 2
+#define DISP_CC_ESYNC0_CLK 3
+#define DISP_CC_ESYNC0_CLK_SRC 4
+#define DISP_CC_ESYNC1_CLK 5
+#define DISP_CC_ESYNC1_CLK_SRC 6
+#define DISP_CC_MDSS_ACCU_SHIFT_CLK 7
+#define DISP_CC_MDSS_AHB1_CLK 8
+#define DISP_CC_MDSS_AHB_CLK 9
+#define DISP_CC_MDSS_AHB_CLK_SRC 10
+#define DISP_CC_MDSS_BYTE0_CLK 11
+#define DISP_CC_MDSS_BYTE0_CLK_SRC 12
+#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 13
+#define DISP_CC_MDSS_BYTE0_INTF_CLK 14
+#define DISP_CC_MDSS_BYTE1_CLK 15
+#define DISP_CC_MDSS_BYTE1_CLK_SRC 16
+#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC 17
+#define DISP_CC_MDSS_BYTE1_INTF_CLK 18
+#define DISP_CC_MDSS_DPTX0_AUX_CLK 19
+#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 20
+#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 21
+#define DISP_CC_MDSS_DPTX0_LINK_CLK 22
+#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 23
+#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 24
+#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 25
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 26
+#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 27
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 28
+#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 29
+#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 30
+#define DISP_CC_MDSS_DPTX1_AUX_CLK 31
+#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC 32
+#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK 33
+#define DISP_CC_MDSS_DPTX1_LINK_CLK 34
+#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC 35
+#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC 36
+#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK 37
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK 38
+#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC 39
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK 40
+#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC 41
+#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK 42
+#define DISP_CC_MDSS_DPTX2_AUX_CLK 43
+#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC 44
+#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK 45
+#define DISP_CC_MDSS_DPTX2_LINK_CLK 46
+#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC 47
+#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC 48
+#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK 49
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK 50
+#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC 51
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK 52
+#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC 53
+#define DISP_CC_MDSS_DPTX3_AUX_CLK 54
+#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC 55
+#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK 56
+#define DISP_CC_MDSS_DPTX3_LINK_CLK 57
+#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC 58
+#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC 59
+#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK 60
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK 61
+#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC 62
+#define DISP_CC_MDSS_ESC0_CLK 63
+#define DISP_CC_MDSS_ESC0_CLK_SRC 64
+#define DISP_CC_MDSS_ESC1_CLK 65
+#define DISP_CC_MDSS_ESC1_CLK_SRC 66
+#define DISP_CC_MDSS_HDMI_AHBM_CLK 67
+#define DISP_CC_MDSS_HDMI_APP_CLK 68
+#define DISP_CC_MDSS_HDMI_APP_CLK_SRC 69
+#define DISP_CC_MDSS_HDMI_CRYPTO_CLK 70
+#define DISP_CC_MDSS_HDMI_INTF_CLK 71
+#define DISP_CC_MDSS_HDMI_PCLK_CLK 72
+#define DISP_CC_MDSS_HDMI_PCLK_CLK_SRC 73
+#define DISP_CC_MDSS_HDMI_PCLK_DIV_CLK_SRC 74
+#define DISP_CC_MDSS_MDP1_CLK 75
+#define DISP_CC_MDSS_MDP_CLK 76
+#define DISP_CC_MDSS_MDP_CLK_SRC 77
+#define DISP_CC_MDSS_MDP_LUT1_CLK 78
+#define DISP_CC_MDSS_MDP_LUT_CLK 79
+#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 80
+#define DISP_CC_MDSS_PCLK0_CLK 81
+#define DISP_CC_MDSS_PCLK0_CLK_SRC 82
+#define DISP_CC_MDSS_PCLK1_CLK 83
+#define DISP_CC_MDSS_PCLK1_CLK_SRC 84
+#define DISP_CC_MDSS_PCLK2_CLK 85
+#define DISP_CC_MDSS_PCLK2_CLK_SRC 86
+#define DISP_CC_MDSS_RSCC_AHB_CLK 87
+#define DISP_CC_MDSS_RSCC_VSYNC_CLK 88
+#define DISP_CC_MDSS_VSYNC1_CLK 89
+#define DISP_CC_MDSS_VSYNC_CLK 90
+#define DISP_CC_MDSS_VSYNC_CLK_SRC 91
+#define DISP_CC_OSC_CLK 92
+#define DISP_CC_OSC_CLK_SRC 93
+#define DISP_CC_SLEEP_CLK 94
+#define DISP_CC_SLEEP_CLK_SRC 95
+#define DISP_CC_XO_CLK 96
+#define DISP_CC_XO_CLK_SRC 97
+
+/* DISP_CC resets */
+#define DISP_CC_MDSS_CORE_BCR 0
+#define DISP_CC_MDSS_CORE_INT2_BCR 1
+#define DISP_CC_MDSS_RSCC_BCR 2
+
+/* DISP_CC GDSCR */
+#define MDSS_GDSC 0
+#define MDSS_INT2_GDSC 1
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sc8180x.h b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
index b9d8438..9ed7b79 100644
--- a/include/dt-bindings/clock/qcom,gcc-sc8180x.h
+++ b/include/dt-bindings/clock/qcom,gcc-sc8180x.h
@@ -322,5 +322,10 @@
#define USB30_MP_GDSC 8
#define USB30_PRIM_GDSC 9
#define USB30_SEC_GDSC 10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 12
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 13
+#define HLOS1_VOTE_TURING_MMU_TBU0_GDSC 14
+#define HLOS1_VOTE_TURING_MMU_TBU1_GDSC 15
#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-gcc.h b/include/dt-bindings/clock/qcom,glymur-gcc.h
index 10c12b8..6907653 100644
--- a/include/dt-bindings/clock/qcom,glymur-gcc.h
+++ b/include/dt-bindings/clock/qcom,glymur-gcc.h
@@ -574,5 +574,6 @@
#define GCC_VIDEO_AXI0_CLK_ARES 89
#define GCC_VIDEO_AXI1_CLK_ARES 90
#define GCC_VIDEO_BCR 91
+#define GCC_VIDEO_AXI0C_CLK_ARES 92
#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-gpucc.h b/include/dt-bindings/clock/qcom,glymur-gpucc.h
new file mode 100644
index 0000000..35f5abb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-gpucc.h
@@ -0,0 +1,51 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2025, Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_GLYMUR_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CX_ACCU_SHIFT_CLK 2
+#define GPU_CC_CX_FF_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_DEMET_CLK 7
+#define GPU_CC_DPM_CLK 8
+#define GPU_CC_FF_CLK_SRC 9
+#define GPU_CC_FREQ_MEASURE_CLK 10
+#define GPU_CC_GMU_CLK_SRC 11
+#define GPU_CC_GPU_SMMU_VOTE_CLK 12
+#define GPU_CC_GX_ACCU_SHIFT_CLK 13
+#define GPU_CC_GX_ACD_AHB_FF_CLK 14
+#define GPU_CC_GX_AHB_FF_CLK 15
+#define GPU_CC_GX_GMU_CLK 16
+#define GPU_CC_GX_RCG_AHB_FF_CLK 17
+#define GPU_CC_HUB_AON_CLK 18
+#define GPU_CC_HUB_CLK_SRC 19
+#define GPU_CC_HUB_CX_INT_CLK 20
+#define GPU_CC_HUB_DIV_CLK_SRC 21
+#define GPU_CC_MEMNOC_GFX_CLK 22
+#define GPU_CC_PLL0 23
+#define GPU_CC_PLL0_OUT_EVEN 24
+#define GPU_CC_RSCC_HUB_AON_CLK 25
+#define GPU_CC_RSCC_XO_AON_CLK 26
+#define GPU_CC_SLEEP_CLK 27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC 0
+
+/* GPU_CC resets */
+#define GPU_CC_CB_BCR 0
+#define GPU_CC_CX_BCR 1
+#define GPU_CC_FAST_HUB_BCR 2
+#define GPU_CC_FF_BCR 3
+#define GPU_CC_GMU_BCR 4
+#define GPU_CC_GX_BCR 5
+#define GPU_CC_XO_BCR 6
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,glymur-videocc.h b/include/dt-bindings/clock/qcom,glymur-videocc.h
new file mode 100644
index 0000000..98c0deb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,glymur-videocc.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_GLYMUR_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_AHB_CLK 0
+#define VIDEO_CC_AHB_CLK_SRC 1
+#define VIDEO_CC_MVS0_CLK 2
+#define VIDEO_CC_MVS0_CLK_SRC 3
+#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
+#define VIDEO_CC_MVS0_FREERUN_CLK 5
+#define VIDEO_CC_MVS0_SHIFT_CLK 6
+#define VIDEO_CC_MVS0C_CLK 7
+#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 8
+#define VIDEO_CC_MVS0C_FREERUN_CLK 9
+#define VIDEO_CC_MVS0C_SHIFT_CLK 10
+#define VIDEO_CC_MVS1_CLK 11
+#define VIDEO_CC_MVS1_DIV_CLK_SRC 12
+#define VIDEO_CC_MVS1_FREERUN_CLK 13
+#define VIDEO_CC_MVS1_SHIFT_CLK 14
+#define VIDEO_CC_PLL0 15
+#define VIDEO_CC_SLEEP_CLK 16
+#define VIDEO_CC_SLEEP_CLK_SRC 17
+#define VIDEO_CC_XO_CLK 18
+#define VIDEO_CC_XO_CLK_SRC 19
+
+/* VIDEO_CC power domains */
+#define VIDEO_CC_MVS0_GDSC 0
+#define VIDEO_CC_MVS0C_GDSC 1
+#define VIDEO_CC_MVS1_GDSC 2
+
+/* VIDEO_CC resets */
+#define VIDEO_CC_INTERFACE_BCR 0
+#define VIDEO_CC_MVS0_BCR 1
+#define VIDEO_CC_MVS0C_BCR 2
+#define VIDEO_CC_MVS0C_FREERUN_CLK_ARES 3
+#define VIDEO_CC_MVS0_FREERUN_CLK_ARES 4
+#define VIDEO_CC_MVS1_FREERUN_CLK_ARES 5
+#define VIDEO_CC_XO_CLK_ARES 6
+#define VIDEO_CC_MVS1_BCR 7
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
new file mode 100644
index 0000000..28d325b
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq6018-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ6018_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ6018_CMN_PLL_CLK 0
+
+/* The output clocks from CMN PLL of IPQ6018. */
+#define IPQ6018_BIAS_PLL_CC_CLK 1
+#define IPQ6018_BIAS_PLL_NSS_NOC_CLK 2
+#endif
diff --git a/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
new file mode 100644
index 0000000..354258a
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,ipq8074-cmn-pll.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+#define _DT_BINDINGS_CLK_QCOM_IPQ8074_CMN_PLL_H
+
+/* CMN PLL core clock. */
+#define IPQ8074_CMN_PLL_CLK 0
+
+/* The output clocks from CMN PLL of IPQ8074. */
+#define IPQ8074_BIAS_PLL_CC_CLK 1
+#define IPQ8074_BIAS_PLL_NSS_NOC_CLK 2
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-gcc.h b/include/dt-bindings/clock/qcom,nord-gcc.h
new file mode 100644
index 0000000..8fbde16
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-gcc.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_NORD_H
+
+/* GCC clocks */
+#define GCC_BOOT_ROM_AHB_CLK 0
+#define GCC_GP1_CLK 1
+#define GCC_GP1_CLK_SRC 2
+#define GCC_GP2_CLK 3
+#define GCC_GP2_CLK_SRC 4
+#define GCC_GPLL0 5
+#define GCC_GPLL0_OUT_EVEN 6
+#define GCC_MMU_0_TCU_VOTE_CLK 7
+#define GCC_PCIE_A_AUX_CLK 8
+#define GCC_PCIE_A_AUX_CLK_SRC 9
+#define GCC_PCIE_A_CFG_AHB_CLK 10
+#define GCC_PCIE_A_DTI_QTC_CLK 11
+#define GCC_PCIE_A_MSTR_AXI_CLK 12
+#define GCC_PCIE_A_PHY_AUX_CLK 13
+#define GCC_PCIE_A_PHY_AUX_CLK_SRC 14
+#define GCC_PCIE_A_PHY_RCHNG_CLK 15
+#define GCC_PCIE_A_PHY_RCHNG_CLK_SRC 16
+#define GCC_PCIE_A_PIPE_CLK 17
+#define GCC_PCIE_A_PIPE_CLK_SRC 18
+#define GCC_PCIE_A_SLV_AXI_CLK 19
+#define GCC_PCIE_A_SLV_Q2A_AXI_CLK 20
+#define GCC_PCIE_B_AUX_CLK 21
+#define GCC_PCIE_B_AUX_CLK_SRC 22
+#define GCC_PCIE_B_CFG_AHB_CLK 23
+#define GCC_PCIE_B_DTI_QTC_CLK 24
+#define GCC_PCIE_B_MSTR_AXI_CLK 25
+#define GCC_PCIE_B_PHY_AUX_CLK 26
+#define GCC_PCIE_B_PHY_AUX_CLK_SRC 27
+#define GCC_PCIE_B_PHY_RCHNG_CLK 28
+#define GCC_PCIE_B_PHY_RCHNG_CLK_SRC 29
+#define GCC_PCIE_B_PIPE_CLK 30
+#define GCC_PCIE_B_PIPE_CLK_SRC 31
+#define GCC_PCIE_B_SLV_AXI_CLK 32
+#define GCC_PCIE_B_SLV_Q2A_AXI_CLK 33
+#define GCC_PCIE_C_AUX_CLK 34
+#define GCC_PCIE_C_AUX_CLK_SRC 35
+#define GCC_PCIE_C_CFG_AHB_CLK 36
+#define GCC_PCIE_C_DTI_QTC_CLK 37
+#define GCC_PCIE_C_MSTR_AXI_CLK 38
+#define GCC_PCIE_C_PHY_AUX_CLK 39
+#define GCC_PCIE_C_PHY_AUX_CLK_SRC 40
+#define GCC_PCIE_C_PHY_RCHNG_CLK 41
+#define GCC_PCIE_C_PHY_RCHNG_CLK_SRC 42
+#define GCC_PCIE_C_PIPE_CLK 43
+#define GCC_PCIE_C_PIPE_CLK_SRC 44
+#define GCC_PCIE_C_SLV_AXI_CLK 45
+#define GCC_PCIE_C_SLV_Q2A_AXI_CLK 46
+#define GCC_PCIE_D_AUX_CLK 47
+#define GCC_PCIE_D_AUX_CLK_SRC 48
+#define GCC_PCIE_D_CFG_AHB_CLK 49
+#define GCC_PCIE_D_DTI_QTC_CLK 50
+#define GCC_PCIE_D_MSTR_AXI_CLK 51
+#define GCC_PCIE_D_PHY_AUX_CLK 52
+#define GCC_PCIE_D_PHY_AUX_CLK_SRC 53
+#define GCC_PCIE_D_PHY_RCHNG_CLK 54
+#define GCC_PCIE_D_PHY_RCHNG_CLK_SRC 55
+#define GCC_PCIE_D_PIPE_CLK 56
+#define GCC_PCIE_D_PIPE_CLK_SRC 57
+#define GCC_PCIE_D_SLV_AXI_CLK 58
+#define GCC_PCIE_D_SLV_Q2A_AXI_CLK 59
+#define GCC_PCIE_LINK_AHB_CLK 60
+#define GCC_PCIE_LINK_XO_CLK 61
+#define GCC_PCIE_NOC_ASYNC_BRIDGE_CLK 62
+#define GCC_PCIE_NOC_CNOC_SF_QX_CLK 63
+#define GCC_PCIE_NOC_M_CFG_CLK 64
+#define GCC_PCIE_NOC_M_PDB_CLK 65
+#define GCC_PCIE_NOC_MSTR_AXI_CLK 66
+#define GCC_PCIE_NOC_PWRCTL_CLK 67
+#define GCC_PCIE_NOC_QOSGEN_EXTREF_CLK 68
+#define GCC_PCIE_NOC_REFGEN_CLK 69
+#define GCC_PCIE_NOC_REFGEN_CLK_SRC 70
+#define GCC_PCIE_NOC_S_CFG_CLK 71
+#define GCC_PCIE_NOC_S_PDB_CLK 72
+#define GCC_PCIE_NOC_SAFETY_CLK 73
+#define GCC_PCIE_NOC_SAFETY_CLK_SRC 74
+#define GCC_PCIE_NOC_SLAVE_AXI_CLK 75
+#define GCC_PCIE_NOC_TSCTR_CLK 76
+#define GCC_PCIE_NOC_XO_CLK 77
+#define GCC_PDM2_CLK 78
+#define GCC_PDM2_CLK_SRC 79
+#define GCC_PDM_AHB_CLK 80
+#define GCC_PDM_XO4_CLK 81
+#define GCC_QUPV3_WRAP3_CORE_2X_CLK 82
+#define GCC_QUPV3_WRAP3_CORE_CLK 83
+#define GCC_QUPV3_WRAP3_M_CLK 84
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK 85
+#define GCC_QUPV3_WRAP3_QSPI_REF_CLK_SRC 86
+#define GCC_QUPV3_WRAP3_S0_CLK 87
+#define GCC_QUPV3_WRAP3_S0_CLK_SRC 88
+#define GCC_QUPV3_WRAP3_S_AHB_CLK 89
+#define GCC_SMMU_PCIE_QTC_VOTE_CLK 90
+
+/* GCC power domains */
+#define GCC_PCIE_A_GDSC 0
+#define GCC_PCIE_A_PHY_GDSC 1
+#define GCC_PCIE_B_GDSC 2
+#define GCC_PCIE_B_PHY_GDSC 3
+#define GCC_PCIE_C_GDSC 4
+#define GCC_PCIE_C_PHY_GDSC 5
+#define GCC_PCIE_D_GDSC 6
+#define GCC_PCIE_D_PHY_GDSC 7
+#define GCC_PCIE_NOC_GDSC 8
+
+/* GCC resets */
+#define GCC_PCIE_A_BCR 0
+#define GCC_PCIE_A_LINK_DOWN_BCR 1
+#define GCC_PCIE_A_NOCSR_COM_PHY_BCR 2
+#define GCC_PCIE_A_PHY_BCR 3
+#define GCC_PCIE_A_PHY_CFG_AHB_BCR 4
+#define GCC_PCIE_A_PHY_COM_BCR 5
+#define GCC_PCIE_A_PHY_NOCSR_COM_PHY_BCR 6
+#define GCC_PCIE_B_BCR 7
+#define GCC_PCIE_B_LINK_DOWN_BCR 8
+#define GCC_PCIE_B_NOCSR_COM_PHY_BCR 9
+#define GCC_PCIE_B_PHY_BCR 10
+#define GCC_PCIE_B_PHY_CFG_AHB_BCR 11
+#define GCC_PCIE_B_PHY_COM_BCR 12
+#define GCC_PCIE_B_PHY_NOCSR_COM_PHY_BCR 13
+#define GCC_PCIE_C_BCR 14
+#define GCC_PCIE_C_LINK_DOWN_BCR 15
+#define GCC_PCIE_C_NOCSR_COM_PHY_BCR 16
+#define GCC_PCIE_C_PHY_BCR 17
+#define GCC_PCIE_C_PHY_CFG_AHB_BCR 18
+#define GCC_PCIE_C_PHY_COM_BCR 19
+#define GCC_PCIE_C_PHY_NOCSR_COM_PHY_BCR 20
+#define GCC_PCIE_D_BCR 21
+#define GCC_PCIE_D_LINK_DOWN_BCR 22
+#define GCC_PCIE_D_NOCSR_COM_PHY_BCR 23
+#define GCC_PCIE_D_PHY_BCR 24
+#define GCC_PCIE_D_PHY_CFG_AHB_BCR 25
+#define GCC_PCIE_D_PHY_COM_BCR 26
+#define GCC_PCIE_D_PHY_NOCSR_COM_PHY_BCR 27
+#define GCC_PCIE_NOC_BCR 28
+#define GCC_PDM_BCR 29
+#define GCC_QUPV3_WRAPPER_3_BCR 30
+#define GCC_TCSR_PCIE_BCR 31
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-negcc.h b/include/dt-bindings/clock/qcom,nord-negcc.h
new file mode 100644
index 0000000..95f333d8
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-negcc.h
@@ -0,0 +1,124 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NE_GCC_NORD_H
+
+/* NE_GCC clocks */
+#define NE_GCC_AGGRE_NOC_UFS_PHY_AXI_CLK 0
+#define NE_GCC_AGGRE_NOC_USB2_AXI_CLK 1
+#define NE_GCC_AGGRE_NOC_USB3_PRIM_AXI_CLK 2
+#define NE_GCC_AGGRE_NOC_USB3_SEC_AXI_CLK 3
+#define NE_GCC_AHB2PHY_CLK 4
+#define NE_GCC_CNOC_USB2_AXI_CLK 5
+#define NE_GCC_CNOC_USB3_PRIM_AXI_CLK 6
+#define NE_GCC_CNOC_USB3_SEC_AXI_CLK 7
+#define NE_GCC_FRQ_MEASURE_REF_CLK 8
+#define NE_GCC_GP1_CLK 9
+#define NE_GCC_GP1_CLK_SRC 10
+#define NE_GCC_GP2_CLK 11
+#define NE_GCC_GP2_CLK_SRC 12
+#define NE_GCC_GPLL0 13
+#define NE_GCC_GPLL0_OUT_EVEN 14
+#define NE_GCC_GPLL2 15
+#define NE_GCC_GPU_2_CFG_CLK 16
+#define NE_GCC_GPU_2_GPLL0_CLK_SRC 17
+#define NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC 18
+#define NE_GCC_GPU_2_HSCNOC_GFX_CLK 19
+#define NE_GCC_GPU_2_SMMU_VOTE_CLK 20
+#define NE_GCC_QUPV3_WRAP2_CORE_2X_CLK 21
+#define NE_GCC_QUPV3_WRAP2_CORE_CLK 22
+#define NE_GCC_QUPV3_WRAP2_M_AHB_CLK 23
+#define NE_GCC_QUPV3_WRAP2_S0_CLK 24
+#define NE_GCC_QUPV3_WRAP2_S0_CLK_SRC 25
+#define NE_GCC_QUPV3_WRAP2_S1_CLK 26
+#define NE_GCC_QUPV3_WRAP2_S1_CLK_SRC 27
+#define NE_GCC_QUPV3_WRAP2_S2_CLK 28
+#define NE_GCC_QUPV3_WRAP2_S2_CLK_SRC 29
+#define NE_GCC_QUPV3_WRAP2_S3_CLK 30
+#define NE_GCC_QUPV3_WRAP2_S3_CLK_SRC 31
+#define NE_GCC_QUPV3_WRAP2_S4_CLK 32
+#define NE_GCC_QUPV3_WRAP2_S4_CLK_SRC 33
+#define NE_GCC_QUPV3_WRAP2_S5_CLK 34
+#define NE_GCC_QUPV3_WRAP2_S5_CLK_SRC 35
+#define NE_GCC_QUPV3_WRAP2_S6_CLK 36
+#define NE_GCC_QUPV3_WRAP2_S6_CLK_SRC 37
+#define NE_GCC_QUPV3_WRAP2_S_AHB_CLK 38
+#define NE_GCC_SDCC4_APPS_CLK 39
+#define NE_GCC_SDCC4_APPS_CLK_SRC 40
+#define NE_GCC_SDCC4_AXI_CLK 41
+#define NE_GCC_UFS_PHY_AHB_CLK 42
+#define NE_GCC_UFS_PHY_AXI_CLK 43
+#define NE_GCC_UFS_PHY_AXI_CLK_SRC 44
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK 45
+#define NE_GCC_UFS_PHY_ICE_CORE_CLK_SRC 46
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK 47
+#define NE_GCC_UFS_PHY_PHY_AUX_CLK_SRC 48
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK 49
+#define NE_GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 50
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK 51
+#define NE_GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 52
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK 53
+#define NE_GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 54
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK 55
+#define NE_GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 56
+#define NE_GCC_USB20_MASTER_CLK 57
+#define NE_GCC_USB20_MASTER_CLK_SRC 58
+#define NE_GCC_USB20_MOCK_UTMI_CLK 59
+#define NE_GCC_USB20_MOCK_UTMI_CLK_SRC 60
+#define NE_GCC_USB20_MOCK_UTMI_POSTDIV_CLK_SRC 61
+#define NE_GCC_USB20_SLEEP_CLK 62
+#define NE_GCC_USB31_PRIM_ATB_CLK 63
+#define NE_GCC_USB31_PRIM_EUD_AHB_CLK 64
+#define NE_GCC_USB31_PRIM_MASTER_CLK 65
+#define NE_GCC_USB31_PRIM_MASTER_CLK_SRC 66
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK 67
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_CLK_SRC 68
+#define NE_GCC_USB31_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 69
+#define NE_GCC_USB31_PRIM_SLEEP_CLK 70
+#define NE_GCC_USB31_SEC_ATB_CLK 71
+#define NE_GCC_USB31_SEC_EUD_AHB_CLK 72
+#define NE_GCC_USB31_SEC_MASTER_CLK 73
+#define NE_GCC_USB31_SEC_MASTER_CLK_SRC 74
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK 75
+#define NE_GCC_USB31_SEC_MOCK_UTMI_CLK_SRC 76
+#define NE_GCC_USB31_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 77
+#define NE_GCC_USB31_SEC_SLEEP_CLK 78
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK 79
+#define NE_GCC_USB3_PRIM_PHY_AUX_CLK_SRC 80
+#define NE_GCC_USB3_PRIM_PHY_COM_AUX_CLK 81
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK 82
+#define NE_GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 83
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK 84
+#define NE_GCC_USB3_SEC_PHY_AUX_CLK_SRC 85
+#define NE_GCC_USB3_SEC_PHY_COM_AUX_CLK 86
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK 87
+#define NE_GCC_USB3_SEC_PHY_PIPE_CLK_SRC 88
+
+/* NE_GCC power domains */
+#define NE_GCC_UFS_MEM_PHY_GDSC 0
+#define NE_GCC_UFS_PHY_GDSC 1
+#define NE_GCC_USB20_PRIM_GDSC 2
+#define NE_GCC_USB31_PRIM_GDSC 3
+#define NE_GCC_USB31_SEC_GDSC 4
+#define NE_GCC_USB3_PHY_GDSC 5
+#define NE_GCC_USB3_SEC_PHY_GDSC 6
+
+/* NE_GCC resets */
+#define NE_GCC_GPU_2_BCR 0
+#define NE_GCC_QUPV3_WRAPPER_2_BCR 1
+#define NE_GCC_SDCC4_BCR 2
+#define NE_GCC_UFS_PHY_BCR 3
+#define NE_GCC_USB20_PRIM_BCR 4
+#define NE_GCC_USB31_PRIM_BCR 5
+#define NE_GCC_USB31_SEC_BCR 6
+#define NE_GCC_USB3_DP_PHY_PRIM_BCR 7
+#define NE_GCC_USB3_DP_PHY_SEC_BCR 8
+#define NE_GCC_USB3_PHY_PRIM_BCR 9
+#define NE_GCC_USB3_PHY_SEC_BCR 10
+#define NE_GCC_USB3PHY_PHY_PRIM_BCR 11
+#define NE_GCC_USB3PHY_PHY_SEC_BCR 12
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-nwgcc.h b/include/dt-bindings/clock/qcom,nord-nwgcc.h
new file mode 100644
index 0000000..b6253dd
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-nwgcc.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_NW_GCC_NORD_H
+
+/* NW_GCC clocks */
+#define NW_GCC_ACMU_MUX_CLK 0
+#define NW_GCC_CAMERA_AHB_CLK 1
+#define NW_GCC_CAMERA_HF_AXI_CLK 2
+#define NW_GCC_CAMERA_SF_AXI_CLK 3
+#define NW_GCC_CAMERA_TRIG_CLK 4
+#define NW_GCC_CAMERA_XO_CLK 5
+#define NW_GCC_DISP_0_AHB_CLK 6
+#define NW_GCC_DISP_0_HF_AXI_CLK 7
+#define NW_GCC_DISP_0_TRIG_CLK 8
+#define NW_GCC_DISP_1_AHB_CLK 9
+#define NW_GCC_DISP_1_HF_AXI_CLK 10
+#define NW_GCC_DISP_1_TRIG_CLK 11
+#define NW_GCC_DPRX0_AXI_HF_CLK 12
+#define NW_GCC_DPRX0_CFG_AHB_CLK 13
+#define NW_GCC_DPRX1_AXI_HF_CLK 14
+#define NW_GCC_DPRX1_CFG_AHB_CLK 15
+#define NW_GCC_EVA_AHB_CLK 16
+#define NW_GCC_EVA_AXI0_CLK 17
+#define NW_GCC_EVA_AXI0C_CLK 18
+#define NW_GCC_EVA_TRIG_CLK 19
+#define NW_GCC_EVA_XO_CLK 20
+#define NW_GCC_FRQ_MEASURE_REF_CLK 21
+#define NW_GCC_GP1_CLK 22
+#define NW_GCC_GP1_CLK_SRC 23
+#define NW_GCC_GP2_CLK 24
+#define NW_GCC_GP2_CLK_SRC 25
+#define NW_GCC_GPLL0 26
+#define NW_GCC_GPLL0_OUT_EVEN 27
+#define NW_GCC_GPU_2_CFG_AHB_CLK 28
+#define NW_GCC_GPU_2_GPLL0_CLK_SRC 29
+#define NW_GCC_GPU_2_GPLL0_DIV_CLK_SRC 30
+#define NW_GCC_GPU_2_HSCNOC_GFX_CLK 31
+#define NW_GCC_GPU_CFG_AHB_CLK 32
+#define NW_GCC_GPU_GPLL0_CLK_SRC 33
+#define NW_GCC_GPU_GPLL0_DIV_CLK_SRC 34
+#define NW_GCC_GPU_HSCNOC_GFX_CLK 35
+#define NW_GCC_GPU_SMMU_VOTE_CLK 36
+#define NW_GCC_HSCNOC_GPU_2_AXI_CLK 37
+#define NW_GCC_HSCNOC_GPU_AXI_CLK 38
+#define NW_GCC_MMU_1_TCU_VOTE_CLK 39
+#define NW_GCC_VIDEO_AHB_CLK 40
+#define NW_GCC_VIDEO_AXI0_CLK 41
+#define NW_GCC_VIDEO_AXI0C_CLK 42
+#define NW_GCC_VIDEO_AXI1_CLK 43
+#define NW_GCC_VIDEO_XO_CLK 44
+
+/* NW_GCC power domains */
+
+/* NW_GCC resets */
+#define NW_GCC_CAMERA_BCR 0
+#define NW_GCC_DISPLAY_0_BCR 1
+#define NW_GCC_DISPLAY_1_BCR 2
+#define NW_GCC_DPRX0_BCR 3
+#define NW_GCC_DPRX1_BCR 4
+#define NW_GCC_EVA_BCR 5
+#define NW_GCC_GPU_2_BCR 6
+#define NW_GCC_GPU_BCR 7
+#define NW_GCC_VIDEO_BCR 8
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-segcc.h b/include/dt-bindings/clock/qcom,nord-segcc.h
new file mode 100644
index 0000000..f0f7422
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-segcc.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_SE_GCC_NORD_H
+
+/* SE_GCC clocks */
+#define SE_GCC_EEE_EMAC0_CLK 0
+#define SE_GCC_EEE_EMAC0_CLK_SRC 1
+#define SE_GCC_EEE_EMAC1_CLK 2
+#define SE_GCC_EEE_EMAC1_CLK_SRC 3
+#define SE_GCC_EMAC0_AXI_CLK 4
+#define SE_GCC_EMAC0_CC_SGMIIPHY_RX_CLK 5
+#define SE_GCC_EMAC0_CC_SGMIIPHY_TX_CLK 6
+#define SE_GCC_EMAC0_PHY_AUX_CLK 7
+#define SE_GCC_EMAC0_PHY_AUX_CLK_SRC 8
+#define SE_GCC_EMAC0_PTP_CLK 9
+#define SE_GCC_EMAC0_PTP_CLK_SRC 10
+#define SE_GCC_EMAC0_RGMII_CLK 11
+#define SE_GCC_EMAC0_RGMII_CLK_SRC 12
+#define SE_GCC_EMAC0_RPCS_RX_CLK 13
+#define SE_GCC_EMAC0_RPCS_TX_CLK 14
+#define SE_GCC_EMAC0_XGXS_RX_CLK 15
+#define SE_GCC_EMAC0_XGXS_TX_CLK 16
+#define SE_GCC_EMAC1_AXI_CLK 17
+#define SE_GCC_EMAC1_CC_SGMIIPHY_RX_CLK 18
+#define SE_GCC_EMAC1_CC_SGMIIPHY_TX_CLK 19
+#define SE_GCC_EMAC1_PHY_AUX_CLK 20
+#define SE_GCC_EMAC1_PHY_AUX_CLK_SRC 21
+#define SE_GCC_EMAC1_PTP_CLK 22
+#define SE_GCC_EMAC1_PTP_CLK_SRC 23
+#define SE_GCC_EMAC1_RGMII_CLK 24
+#define SE_GCC_EMAC1_RGMII_CLK_SRC 25
+#define SE_GCC_EMAC1_RPCS_RX_CLK 26
+#define SE_GCC_EMAC1_RPCS_TX_CLK 27
+#define SE_GCC_EMAC1_XGXS_RX_CLK 28
+#define SE_GCC_EMAC1_XGXS_TX_CLK 29
+#define SE_GCC_FRQ_MEASURE_REF_CLK 30
+#define SE_GCC_GP1_CLK 31
+#define SE_GCC_GP1_CLK_SRC 32
+#define SE_GCC_GP2_CLK 33
+#define SE_GCC_GP2_CLK_SRC 34
+#define SE_GCC_GPLL0 35
+#define SE_GCC_GPLL0_OUT_EVEN 36
+#define SE_GCC_GPLL2 37
+#define SE_GCC_GPLL4 38
+#define SE_GCC_GPLL5 39
+#define SE_GCC_MMU_2_TCU_VOTE_CLK 40
+#define SE_GCC_QUPV3_WRAP0_CORE_2X_CLK 41
+#define SE_GCC_QUPV3_WRAP0_CORE_CLK 42
+#define SE_GCC_QUPV3_WRAP0_M_AHB_CLK 43
+#define SE_GCC_QUPV3_WRAP0_S0_CLK 44
+#define SE_GCC_QUPV3_WRAP0_S0_CLK_SRC 45
+#define SE_GCC_QUPV3_WRAP0_S1_CLK 46
+#define SE_GCC_QUPV3_WRAP0_S1_CLK_SRC 47
+#define SE_GCC_QUPV3_WRAP0_S2_CLK 48
+#define SE_GCC_QUPV3_WRAP0_S2_CLK_SRC 49
+#define SE_GCC_QUPV3_WRAP0_S3_CLK 50
+#define SE_GCC_QUPV3_WRAP0_S3_CLK_SRC 51
+#define SE_GCC_QUPV3_WRAP0_S4_CLK 52
+#define SE_GCC_QUPV3_WRAP0_S4_CLK_SRC 53
+#define SE_GCC_QUPV3_WRAP0_S5_CLK 54
+#define SE_GCC_QUPV3_WRAP0_S5_CLK_SRC 55
+#define SE_GCC_QUPV3_WRAP0_S6_CLK 56
+#define SE_GCC_QUPV3_WRAP0_S6_CLK_SRC 57
+#define SE_GCC_QUPV3_WRAP0_S_AHB_CLK 58
+#define SE_GCC_QUPV3_WRAP1_CORE_2X_CLK 59
+#define SE_GCC_QUPV3_WRAP1_CORE_CLK 60
+#define SE_GCC_QUPV3_WRAP1_M_AHB_CLK 61
+#define SE_GCC_QUPV3_WRAP1_S0_CLK 62
+#define SE_GCC_QUPV3_WRAP1_S0_CLK_SRC 63
+#define SE_GCC_QUPV3_WRAP1_S1_CLK 64
+#define SE_GCC_QUPV3_WRAP1_S1_CLK_SRC 65
+#define SE_GCC_QUPV3_WRAP1_S2_CLK 66
+#define SE_GCC_QUPV3_WRAP1_S2_CLK_SRC 67
+#define SE_GCC_QUPV3_WRAP1_S3_CLK 68
+#define SE_GCC_QUPV3_WRAP1_S3_CLK_SRC 69
+#define SE_GCC_QUPV3_WRAP1_S4_CLK 70
+#define SE_GCC_QUPV3_WRAP1_S4_CLK_SRC 71
+#define SE_GCC_QUPV3_WRAP1_S5_CLK 72
+#define SE_GCC_QUPV3_WRAP1_S5_CLK_SRC 73
+#define SE_GCC_QUPV3_WRAP1_S6_CLK 74
+#define SE_GCC_QUPV3_WRAP1_S6_CLK_SRC 75
+#define SE_GCC_QUPV3_WRAP1_S_AHB_CLK 76
+
+/* SE_GCC power domains */
+#define SE_GCC_EMAC0_GDSC 0
+#define SE_GCC_EMAC1_GDSC 1
+
+/* SE_GCC resets */
+#define SE_GCC_EMAC0_BCR 0
+#define SE_GCC_EMAC1_BCR 1
+#define SE_GCC_QUPV3_WRAPPER_0_BCR 2
+#define SE_GCC_QUPV3_WRAPPER_1_BCR 3
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,nord-tcsrcc.h b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
new file mode 100644
index 0000000..3f0e2ff
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,nord-tcsrcc.h
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+#define _DT_BINDINGS_CLK_QCOM_TCSR_CC_NORD_H
+
+/* TCSR_CC clocks */
+#define TCSR_DP_RX_0_CLKREF_EN 0
+#define TCSR_DP_RX_1_CLKREF_EN 1
+#define TCSR_DP_TX_0_CLKREF_EN 2
+#define TCSR_DP_TX_1_CLKREF_EN 3
+#define TCSR_DP_TX_2_CLKREF_EN 4
+#define TCSR_DP_TX_3_CLKREF_EN 5
+#define TCSR_PCIE_CLKREF_EN 6
+#define TCSR_UFS_CLKREF_EN 7
+#define TCSR_USB2_0_CLKREF_EN 8
+#define TCSR_USB2_1_CLKREF_EN 9
+#define TCSR_USB2_2_CLKREF_EN 10
+#define TCSR_USB3_0_CLKREF_EN 11
+#define TCSR_USB3_1_CLKREF_EN 12
+#define TCSR_UX_SGMII_0_CLKREF_EN 13
+#define TCSR_UX_SGMII_1_CLKREF_EN 14
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,sm8750-gpucc.h b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
new file mode 100644
index 0000000..e2143d9
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8750-gpucc.h
@@ -0,0 +1,50 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ */
+#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+#define _DT_BINDINGS_CLK_QCOM_GPU_CC_SM8750_H
+
+/* GPU_CC clocks */
+#define GPU_CC_AHB_CLK 0
+#define GPU_CC_CB_CLK 1
+#define GPU_CC_CX_ACCU_SHIFT_CLK 2
+#define GPU_CC_CX_FF_CLK 3
+#define GPU_CC_CX_GMU_CLK 4
+#define GPU_CC_CXO_AON_CLK 5
+#define GPU_CC_CXO_CLK 6
+#define GPU_CC_DEMET_CLK 7
+#define GPU_CC_DPM_CLK 8
+#define GPU_CC_FF_CLK_SRC 9
+#define GPU_CC_FREQ_MEASURE_CLK 10
+#define GPU_CC_GMU_CLK_SRC 11
+#define GPU_CC_GX_ACCU_SHIFT_CLK 12
+#define GPU_CC_GX_ACD_AHB_FF_CLK 13
+#define GPU_CC_GX_AHB_FF_CLK 14
+#define GPU_CC_GX_GMU_CLK 15
+#define GPU_CC_GX_RCG_AHB_FF_CLK 16
+#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 17
+#define GPU_CC_HUB_AON_CLK 18
+#define GPU_CC_HUB_CLK_SRC 19
+#define GPU_CC_HUB_CX_INT_CLK 20
+#define GPU_CC_HUB_DIV_CLK_SRC 21
+#define GPU_CC_MEMNOC_GFX_CLK 22
+#define GPU_CC_PLL0 23
+#define GPU_CC_PLL0_OUT_EVEN 24
+#define GPU_CC_RSCC_HUB_AON_CLK 25
+#define GPU_CC_RSCC_XO_AON_CLK 26
+#define GPU_CC_SLEEP_CLK 27
+
+/* GPU_CC power domains */
+#define GPU_CC_CX_GDSC 0
+
+/* GPU_CC resets */
+#define GPU_CC_GPU_CC_CB_BCR 0
+#define GPU_CC_GPU_CC_CX_BCR 1
+#define GPU_CC_GPU_CC_FAST_HUB_BCR 2
+#define GPU_CC_GPU_CC_FF_BCR 3
+#define GPU_CC_GPU_CC_GMU_BCR 4
+#define GPU_CC_GPU_CC_GX_BCR 5
+#define GPU_CC_GPU_CC_XO_BCR 6
+
+#endif
diff --git a/include/dt-bindings/clock/samsung,exynosautov920.h b/include/dt-bindings/clock/samsung,exynosautov920.h
index 06dec27..f2628c2 100644
--- a/include/dt-bindings/clock/samsung,exynosautov920.h
+++ b/include/dt-bindings/clock/samsung,exynosautov920.h
@@ -309,4 +309,10 @@
#define CLK_MOUT_MFD_NOC_USER 1
#define CLK_DOUT_MFD_NOCP 2
+/* CMU_G3D */
+#define FOUT_PLL_G3D 1
+#define CLK_MOUT_G3D_NOC 2
+#define CLK_MOUT_G3D_SWITCH_USER 3
+#define CLK_MOUT_G3D_NOCP_USER 4
+
#endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV920_H */
diff --git a/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h b/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
new file mode 100644
index 0000000..c1c875e
--- /dev/null
+++ b/include/dt-bindings/clock/tenstorrent,atlantis-prcm-rcpu.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Tenstorrent Atlantis PRCM Clock and Reset Indices
+ *
+ * Copyright (c) 2026 Tenstorrent
+ */
+
+#ifndef _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
+#define _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H
+
+/*
+ * RCPU Domain Clock IDs
+ */
+#define CLK_RCPU_PLL 0
+#define CLK_RCPU_ROOT 1
+#define CLK_RCPU_DIV2 2
+#define CLK_RCPU_DIV4 3
+#define CLK_RCPU_RTC 4
+#define CLK_SMNDMA0_ACLK 5
+#define CLK_SMNDMA1_ACLK 6
+#define CLK_WDT0_PCLK 7
+#define CLK_WDT1_PCLK 8
+#define CLK_TIMER_PCLK 9
+#define CLK_PVTC_PCLK 10
+#define CLK_PMU_PCLK 11
+#define CLK_MAILBOX_HCLK 12
+#define CLK_SEC_SPACC_HCLK 13
+#define CLK_SEC_OTP_HCLK 14
+#define CLK_TRNG_PCLK 15
+#define CLK_SEC_CRC_HCLK 16
+#define CLK_SMN_HCLK 17
+#define CLK_AHB0_HCLK 18
+#define CLK_SMN_PCLK 19
+#define CLK_SMN_CLK 20
+#define CLK_SCRATCHPAD_CLK 21
+#define CLK_RCPU_CORE_CLK 22
+#define CLK_RCPU_ROM_CLK 23
+#define CLK_OTP_LOAD_CLK 24
+#define CLK_NOC_PLL 25
+#define CLK_NOCC_CLK 26
+#define CLK_NOCC_DIV2 27
+#define CLK_NOCC_DIV4 28
+#define CLK_NOCC_RTC 29
+#define CLK_NOCC_CAN 30
+#define CLK_QSPI_SCLK 31
+#define CLK_QSPI_HCLK 32
+#define CLK_I2C0_PCLK 33
+#define CLK_I2C1_PCLK 34
+#define CLK_I2C2_PCLK 35
+#define CLK_I2C3_PCLK 36
+#define CLK_I2C4_PCLK 37
+#define CLK_UART0_PCLK 38
+#define CLK_UART1_PCLK 39
+#define CLK_UART2_PCLK 40
+#define CLK_UART3_PCLK 41
+#define CLK_UART4_PCLK 42
+#define CLK_SPI0_PCLK 43
+#define CLK_SPI1_PCLK 44
+#define CLK_SPI2_PCLK 45
+#define CLK_SPI3_PCLK 46
+#define CLK_GPIO_PCLK 47
+#define CLK_CAN0_HCLK 48
+#define CLK_CAN0_CLK 49
+#define CLK_CAN1_HCLK 50
+#define CLK_CAN1_CLK 51
+#define CLK_CAN0_TIMER_CLK 52
+#define CLK_CAN1_TIMER_CLK 53
+
+/* RCPU domain reset */
+#define RST_SMNDMA0 0
+#define RST_SMNDMA1 1
+#define RST_WDT0 2
+#define RST_WDT1 3
+#define RST_TMR 4
+#define RST_PVTC 5
+#define RST_PMU 6
+#define RST_MAILBOX 7
+#define RST_SPACC 8
+#define RST_OTP 9
+#define RST_TRNG 10
+#define RST_CRC 11
+#define RST_QSPI 12
+#define RST_I2C0 13
+#define RST_I2C1 14
+#define RST_I2C2 15
+#define RST_I2C3 16
+#define RST_I2C4 17
+#define RST_UART0 18
+#define RST_UART1 19
+#define RST_UART2 20
+#define RST_UART3 21
+#define RST_UART4 22
+#define RST_SPI0 23
+#define RST_SPI1 24
+#define RST_SPI2 25
+#define RST_SPI3 26
+#define RST_GPIO 27
+#define RST_CAN0 28
+#define RST_CAN1 29
+#define RST_I2S0 30
+#define RST_I2S1 31
+
+#endif /* _DT_BINDINGS_ATLANTIS_PRCM_RCPU_H */
diff --git a/include/dt-bindings/clock/vf610-clock.h b/include/dt-bindings/clock/vf610-clock.h
index 373644e..5d94bd5 100644
--- a/include/dt-bindings/clock/vf610-clock.h
+++ b/include/dt-bindings/clock/vf610-clock.h
@@ -197,6 +197,10 @@
#define VF610_CLK_TCON1 188
#define VF610_CLK_CAAM 189
#define VF610_CLK_CRC 190
-#define VF610_CLK_END 191
+#define VF610_CLK_ESW 191
+#define VF610_CLK_ESW_MAC_TAB0 192
+#define VF610_CLK_ESW_MAC_TAB1 193
+#define VF610_CLK_ESW_MAC_TAB2 194
+#define VF610_CLK_ESW_MAC_TAB3 195
#endif /* __DT_BINDINGS_CLOCK_VF610_H */
diff --git a/include/dt-bindings/reset/econet,en751221-scu.h b/include/dt-bindings/reset/econet,en751221-scu.h
new file mode 100644
index 0000000..bad499d
--- /dev/null
+++ b/include/dt-bindings/reset/econet,en751221-scu.h
@@ -0,0 +1,49 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+
+#ifndef __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+#define __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_
+
+#define EN751221_XPON_PHY_RST 0
+#define EN751221_PCM1_ZSI_ISI_RST 1
+#define EN751221_FE_QDMA1_RST 2
+#define EN751221_FE_QDMA2_RST 3
+#define EN751221_FE_UNZIP_RST 4
+#define EN751221_PCM2_RST 5
+#define EN751221_PTM_MAC_RST 6
+#define EN751221_CRYPTO_RST 7
+#define EN751221_SAR_RST 8
+#define EN751221_TIMER_RST 9
+#define EN751221_INTC_RST 10
+#define EN751221_BONDING_RST 11
+#define EN751221_PCM1_RST 12
+#define EN751221_UART_RST 13
+#define EN751221_GPIO_RST 14
+#define EN751221_GDMA_RST 15
+#define EN751221_I2C_MASTER_RST 16
+#define EN751221_PCM2_ZSI_ISI_RST 17
+#define EN751221_SFC_RST 18
+#define EN751221_UART2_RST 19
+#define EN751221_GDMP_RST 20
+#define EN751221_FE_RST 21
+#define EN751221_USB_HOST_P0_RST 22
+#define EN751221_GSW_RST 23
+#define EN751221_SFC2_PCM_RST 24
+#define EN751221_PCIE0_RST 25
+#define EN751221_PCIE1_RST 26
+#define EN751221_CPU_TIMER_RST 27
+#define EN751221_PCIE_HB_RST 28
+#define EN751221_SIMIF_RST 29
+#define EN751221_XPON_MAC_RST 30
+#define EN751221_GFAST_RST 31
+#define EN751221_CPU_TIMER2_RST 32
+#define EN751221_UART3_RST 33
+#define EN751221_UART4_RST 34
+#define EN751221_UART5_RST 35
+#define EN751221_I2C2_RST 36
+#define EN751221_XSI_MAC_RST 37
+#define EN751221_XSI_PHY_RST 38
+#define EN751221_DMT_RST 39
+#define EN751221_USB_PHY_P0_RST 40
+#define EN751221_USB_PHY_P1_RST 41
+
+#endif /* __DT_BINDINGS_RESET_CONTROLLER_ECONET_EN751221_H_ */
