diff --git a/Bindings/net/pse-pd/microchip,pd692x0.yaml b/Bindings/net/pse-pd/microchip,pd692x0.yaml
index 8284393..fd4244f 100644
--- a/Bindings/net/pse-pd/microchip,pd692x0.yaml
+++ b/Bindings/net/pse-pd/microchip,pd692x0.yaml
@@ -24,6 +24,7 @@
 
   managers:
     type: object
+    additionalProperties: false
     description:
       List of the PD69208T4/PD69204T4/PD69208M PSE managers. Each manager
       have 4 or 8 physical ports according to the chip version. No need to
@@ -47,8 +48,9 @@
       - "#size-cells"
 
     patternProperties:
-      "^manager@0[0-9a-b]$":
+      "^manager@[0-9a-b]$":
         type: object
+        additionalProperties: false
         description:
           PD69208T4/PD69204T4/PD69208M PSE manager exposing 4 or 8 physical
           ports.
@@ -69,9 +71,14 @@
         patternProperties:
           '^port@[0-7]$':
             type: object
+            additionalProperties: false
+
+            properties:
+              reg:
+                maxItems: 1
+
             required:
               - reg
-            additionalProperties: false
 
         required:
           - reg
diff --git a/Bindings/net/pse-pd/ti,tps23881.yaml b/Bindings/net/pse-pd/ti,tps23881.yaml
index 4147adb..6992d56 100644
--- a/Bindings/net/pse-pd/ti,tps23881.yaml
+++ b/Bindings/net/pse-pd/ti,tps23881.yaml
@@ -29,13 +29,31 @@
       of the ports conversion matrix that establishes relationship between
       the logical ports and the physical channels.
     type: object
+    additionalProperties: false
+
+    properties:
+      "#address-cells":
+        const: 1
+
+      "#size-cells":
+        const: 0
 
     patternProperties:
       '^channel@[0-7]$':
         type: object
+        additionalProperties: false
+
+        properties:
+          reg:
+            maxItems: 1
+
         required:
           - reg
 
+    required:
+      - "#address-cells"
+      - "#size-cells"
+
 unevaluatedProperties: false
 
 required: