)]}'
{
  "commit": "81dd31d81b00e99a89b64eeecba32fa8e6cc0128",
  "tree": "0855e04db00aa597a2a5b23c3381b435f3e46643",
  "parents": [
    "63dd3374ca84f6b16f7e947b4bde7cf8ea8d5ec6",
    "67e446d2ad6b4d0134a79ec9a048b67b673ea8dd",
    "9cb7d912bd006723cf4010e7fa8b7c94a16298bf",
    "3dcfe1c66ed37aee14cc07bacde1fe1217d33419",
    "1eba11ab743ec71f932e88483b747c38cdf10c15"
  ],
  "author": {
    "name": "Stephen Boyd",
    "email": "sboyd@kernel.org",
    "time": "Thu Apr 16 10:12:43 2026 -0700"
  },
  "committer": {
    "name": "Stephen Boyd",
    "email": "sboyd@kernel.org",
    "time": "Thu Apr 16 10:12:43 2026 -0700"
  },
  "message": "Merge branches \u0027clk-samsung\u0027, \u0027clk-qcom\u0027, \u0027clk-round\u0027, \u0027clk-sai\u0027 and \u0027clk-cleanup\u0027 into clk-next\n\n* clk-samsung:\n  clk: samsung: exynos850: Add APM-to-AP mailbox clock\n  dt-bindings: clock: exynos850: Add APM_AP MAILBOX clock\n  clk: samsung: Use %pe format to simplify\n  clk: samsung: pll: Fix possible truncation in a9fraco recalc rate\n  clk: samsung: exynosautov920: add block G3D clock support\n  dt-bindings: clock: exynosautov920: add G3D clock definitions\n  clk: samsung: gs101: harmonise symbol names (clock arrays)\n  clk: samsung: artpec-9: Add initial clock support for ARTPEC-9 SoC\n  clk: samsung: Add clock PLL support for ARTPEC-9 SoC\n  dt-bindings: clock: Add ARTPEC-9 clock controller\n\n* clk-qcom: (67 commits)\n  clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC\n  clk: qcom: rpmh: Add support for Nord rpmh clocks\n  clk: qcom: Add TCSR clock driver for Nord SoC\n  dt-bindings: clock: qcom: Add Nord Global Clock Controller\n  dt-bindings: clock: qcom-rpmhcc: Add support for Nord SoCs\n  dt-bindings: clock: qcom: Document the Nord SoC TCSR Clock Controller\n  clk: qcom: gcc-x1e80100: Keep GCC USB QTB clock always ON\n  clk: qcom: Constify list of critical CBCR registers\n  clk: qcom: Constify qcom_cc_driver_data\n  clk: qcom: videocc-glymur: Constify qcom_cc_desc\n  clk: qcom: Add a driver for SM8750 GPU clocks\n  dt-bindings: clock: qcom: Add SM8750 GPU clocks\n  clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support\n  dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074\n  clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support\n  dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018\n  clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains\n  dt-bindings: clock: qcom: Add missing power-domains property\n  clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock\n  clk: qcom: dispcc-sc7180: Add missing MDSS resets\n  ...\n\n* clk-round:\n  clk: divider: remove divider_round_rate() and divider_round_rate_parent()\n  clk: divider: remove divider_ro_round_rate_parent()\n  clk: remove round_rate() clk ops\n  clk: composite: convert from round_rate() to determine_rate()\n  clk: test: remove references to clk_ops.round_rate\n\n* clk-sai:\n  clk: fsl-sai: Add MCLK generation support\n  clk: fsl-sai: Extract clock setup into fsl_sai_clk_register()\n  dt-bindings: clock: fsl-sai: Document clock-cells \u003d \u003c1\u003e support\n  clk: fsl-sai: Add i.MX8M support with 8 byte register offset\n  clk: fsl-sai: Sort the headers\n  dt-bindings: clock: fsl-sai: Document i.MX8M support\n\n* clk-cleanup:\n  clk: visconti: pll: initialize clk_init_data to zero\n  clk: xgene: Fix mapping leak in xgene_pllclk_init()\n  clk: Simplify clk_is_match()\n  clk: baikal-t1: Remove not-going-to-be-supported code for Baikal SoC\n  clk: mvebu: armada-37xx-periph: fix __iomem casts in structure init\n  clk: qoriq: avoid format string warning\n\n[ upstream commit: 6b701fde9b31f085f39fc2a371cb33212fab6f68 ]\n",
  "tree_diff": []
}