| // SPDX-License-Identifier: BSD-3-Clause |
| /* |
| * Copyright (c) 2021, The Linux Foundation. All rights reserved. |
| * Copyright (c) 2022, Linaro Limited |
| */ |
| |
| #include <dt-bindings/clock/qcom,dispcc-sc8280xp.h> |
| #include <dt-bindings/clock/qcom,gcc-sc8280xp.h> |
| #include <dt-bindings/clock/qcom,gpucc-sc8280xp.h> |
| #include <dt-bindings/clock/qcom,rpmh.h> |
| #include <dt-bindings/clock/qcom,sc8280xp-camcc.h> |
| #include <dt-bindings/clock/qcom,sc8280xp-lpasscc.h> |
| #include <dt-bindings/interconnect/qcom,osm-l3.h> |
| #include <dt-bindings/interconnect/qcom,sc8280xp.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/mailbox/qcom-ipcc.h> |
| #include <dt-bindings/phy/phy-qcom-qmp.h> |
| #include <dt-bindings/power/qcom-rpmpd.h> |
| #include <dt-bindings/soc/qcom,gpr.h> |
| #include <dt-bindings/soc/qcom,rpmh-rsc.h> |
| #include <dt-bindings/sound/qcom,q6afe.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| interrupt-parent = <&intc>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| clocks { |
| xo_board_clk: xo-board-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| }; |
| |
| sleep_clk: sleep-clk { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| clock-frequency = <32764>; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <2>; |
| #size-cells = <0>; |
| |
| CPU0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78c"; |
| reg = <0x0 0x0>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <981>; |
| dynamic-power-coefficient = <549>; |
| next-level-cache = <&L2_0>; |
| power-domains = <&CPU_PD0>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_0: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| L3_0: l3-cache { |
| compatible = "cache"; |
| cache-level = <3>; |
| cache-unified; |
| }; |
| }; |
| }; |
| |
| CPU1: cpu@100 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78c"; |
| reg = <0x0 0x100>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <981>; |
| dynamic-power-coefficient = <549>; |
| next-level-cache = <&L2_100>; |
| power-domains = <&CPU_PD1>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_100: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU2: cpu@200 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78c"; |
| reg = <0x0 0x200>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <981>; |
| dynamic-power-coefficient = <549>; |
| next-level-cache = <&L2_200>; |
| power-domains = <&CPU_PD2>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_200: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU3: cpu@300 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a78c"; |
| reg = <0x0 0x300>; |
| clocks = <&cpufreq_hw 0>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <981>; |
| dynamic-power-coefficient = <549>; |
| next-level-cache = <&L2_300>; |
| power-domains = <&CPU_PD3>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 0>; |
| operating-points-v2 = <&cpu0_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_300: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU4: cpu@400 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-x1c"; |
| reg = <0x0 0x400>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <590>; |
| next-level-cache = <&L2_400>; |
| power-domains = <&CPU_PD4>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_400: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU5: cpu@500 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-x1c"; |
| reg = <0x0 0x500>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <590>; |
| next-level-cache = <&L2_500>; |
| power-domains = <&CPU_PD5>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_500: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU6: cpu@600 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-x1c"; |
| reg = <0x0 0x600>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <590>; |
| next-level-cache = <&L2_600>; |
| power-domains = <&CPU_PD6>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_600: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| CPU7: cpu@700 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-x1c"; |
| reg = <0x0 0x700>; |
| clocks = <&cpufreq_hw 1>; |
| enable-method = "psci"; |
| capacity-dmips-mhz = <1024>; |
| dynamic-power-coefficient = <590>; |
| next-level-cache = <&L2_700>; |
| power-domains = <&CPU_PD7>; |
| power-domain-names = "psci"; |
| qcom,freq-domain = <&cpufreq_hw 1>; |
| operating-points-v2 = <&cpu4_opp_table>; |
| interconnects = <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; |
| #cooling-cells = <2>; |
| L2_700: l2-cache { |
| compatible = "cache"; |
| cache-level = <2>; |
| cache-unified; |
| next-level-cache = <&L3_0>; |
| }; |
| }; |
| |
| cpu-map { |
| cluster0 { |
| core0 { |
| cpu = <&CPU0>; |
| }; |
| |
| core1 { |
| cpu = <&CPU1>; |
| }; |
| |
| core2 { |
| cpu = <&CPU2>; |
| }; |
| |
| core3 { |
| cpu = <&CPU3>; |
| }; |
| |
| core4 { |
| cpu = <&CPU4>; |
| }; |
| |
| core5 { |
| cpu = <&CPU5>; |
| }; |
| |
| core6 { |
| cpu = <&CPU6>; |
| }; |
| |
| core7 { |
| cpu = <&CPU7>; |
| }; |
| }; |
| }; |
| |
| idle-states { |
| entry-method = "psci"; |
| |
| LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "little-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <355>; |
| exit-latency-us = <909>; |
| min-residency-us = <3934>; |
| local-timer-stop; |
| }; |
| |
| BIG_CPU_SLEEP_0: cpu-sleep-1-0 { |
| compatible = "arm,idle-state"; |
| idle-state-name = "big-rail-power-collapse"; |
| arm,psci-suspend-param = <0x40000004>; |
| entry-latency-us = <241>; |
| exit-latency-us = <1461>; |
| min-residency-us = <4488>; |
| local-timer-stop; |
| }; |
| }; |
| |
| domain-idle-states { |
| CLUSTER_SLEEP_0: cluster-sleep-0 { |
| compatible = "domain-idle-state"; |
| arm,psci-suspend-param = <0x4100c344>; |
| entry-latency-us = <3263>; |
| exit-latency-us = <6562>; |
| min-residency-us = <9987>; |
| }; |
| }; |
| }; |
| |
| firmware { |
| scm: scm { |
| compatible = "qcom,scm-sc8280xp", "qcom,scm"; |
| interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; |
| qcom,dload-mode = <&tcsr 0x13000>; |
| }; |
| }; |
| |
| aggre1_noc: interconnect-aggre1-noc { |
| compatible = "qcom,sc8280xp-aggre1-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| aggre2_noc: interconnect-aggre2-noc { |
| compatible = "qcom,sc8280xp-aggre2-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| clk_virt: interconnect-clk-virt { |
| compatible = "qcom,sc8280xp-clk-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| config_noc: interconnect-config-noc { |
| compatible = "qcom,sc8280xp-config-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| dc_noc: interconnect-dc-noc { |
| compatible = "qcom,sc8280xp-dc-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| gem_noc: interconnect-gem-noc { |
| compatible = "qcom,sc8280xp-gem-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| lpass_noc: interconnect-lpass-ag-noc { |
| compatible = "qcom,sc8280xp-lpass-ag-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mc_virt: interconnect-mc-virt { |
| compatible = "qcom,sc8280xp-mc-virt"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| mmss_noc: interconnect-mmss-noc { |
| compatible = "qcom,sc8280xp-mmss-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| nspa_noc: interconnect-nspa-noc { |
| compatible = "qcom,sc8280xp-nspa-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| nspb_noc: interconnect-nspb-noc { |
| compatible = "qcom,sc8280xp-nspb-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| system_noc: interconnect-system-noc { |
| compatible = "qcom,sc8280xp-system-noc"; |
| #interconnect-cells = <2>; |
| qcom,bcm-voters = <&apps_bcm_voter>; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* We expect the bootloader to fill in the size */ |
| reg = <0x0 0x80000000 0x0 0x0>; |
| }; |
| |
| cpu0_opp_table: opp-table-cpu0 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-300000000 { |
| opp-hz = /bits/ 64 <300000000>; |
| opp-peak-kBps = <(300000 * 32)>; |
| }; |
| opp-403200000 { |
| opp-hz = /bits/ 64 <403200000>; |
| opp-peak-kBps = <(384000 * 32)>; |
| }; |
| opp-499200000 { |
| opp-hz = /bits/ 64 <499200000>; |
| opp-peak-kBps = <(480000 * 32)>; |
| }; |
| opp-595200000 { |
| opp-hz = /bits/ 64 <595200000>; |
| opp-peak-kBps = <(576000 * 32)>; |
| }; |
| opp-691200000 { |
| opp-hz = /bits/ 64 <691200000>; |
| opp-peak-kBps = <(672000 * 32)>; |
| }; |
| opp-806400000 { |
| opp-hz = /bits/ 64 <806400000>; |
| opp-peak-kBps = <(768000 * 32)>; |
| }; |
| opp-902400000 { |
| opp-hz = /bits/ 64 <902400000>; |
| opp-peak-kBps = <(864000 * 32)>; |
| }; |
| opp-1017600000 { |
| opp-hz = /bits/ 64 <1017600000>; |
| opp-peak-kBps = <(960000 * 32)>; |
| }; |
| opp-1113600000 { |
| opp-hz = /bits/ 64 <1113600000>; |
| opp-peak-kBps = <(1075200 * 32)>; |
| }; |
| opp-1209600000 { |
| opp-hz = /bits/ 64 <1209600000>; |
| opp-peak-kBps = <(1171200 * 32)>; |
| }; |
| opp-1324800000 { |
| opp-hz = /bits/ 64 <1324800000>; |
| opp-peak-kBps = <(1267200 * 32)>; |
| }; |
| opp-1440000000 { |
| opp-hz = /bits/ 64 <1440000000>; |
| opp-peak-kBps = <(1363200 * 32)>; |
| }; |
| opp-1555200000 { |
| opp-hz = /bits/ 64 <1555200000>; |
| opp-peak-kBps = <(1536000 * 32)>; |
| }; |
| opp-1670400000 { |
| opp-hz = /bits/ 64 <1670400000>; |
| opp-peak-kBps = <(1612800 * 32)>; |
| }; |
| opp-1785600000 { |
| opp-hz = /bits/ 64 <1785600000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-1881600000 { |
| opp-hz = /bits/ 64 <1881600000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-1996800000 { |
| opp-hz = /bits/ 64 <1996800000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2112000000 { |
| opp-hz = /bits/ 64 <2112000000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2227200000 { |
| opp-hz = /bits/ 64 <2227200000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2342400000 { |
| opp-hz = /bits/ 64 <2342400000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2438400000 { |
| opp-hz = /bits/ 64 <2438400000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| }; |
| |
| cpu4_opp_table: opp-table-cpu4 { |
| compatible = "operating-points-v2"; |
| opp-shared; |
| |
| opp-825600000 { |
| opp-hz = /bits/ 64 <825600000>; |
| opp-peak-kBps = <(768000 * 32)>; |
| }; |
| opp-940800000 { |
| opp-hz = /bits/ 64 <940800000>; |
| opp-peak-kBps = <(864000 * 32)>; |
| }; |
| opp-1056000000 { |
| opp-hz = /bits/ 64 <1056000000>; |
| opp-peak-kBps = <(960000 * 32)>; |
| }; |
| opp-1171200000 { |
| opp-hz = /bits/ 64 <1171200000>; |
| opp-peak-kBps = <(1171200 * 32)>; |
| }; |
| opp-1286400000 { |
| opp-hz = /bits/ 64 <1286400000>; |
| opp-peak-kBps = <(1267200 * 32)>; |
| }; |
| opp-1401600000 { |
| opp-hz = /bits/ 64 <1401600000>; |
| opp-peak-kBps = <(1363200 * 32)>; |
| }; |
| opp-1516800000 { |
| opp-hz = /bits/ 64 <1516800000>; |
| opp-peak-kBps = <(1459200 * 32)>; |
| }; |
| opp-1632000000 { |
| opp-hz = /bits/ 64 <1632000000>; |
| opp-peak-kBps = <(1612800 * 32)>; |
| }; |
| opp-1747200000 { |
| opp-hz = /bits/ 64 <1747200000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-1862400000 { |
| opp-hz = /bits/ 64 <1862400000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-1977600000 { |
| opp-hz = /bits/ 64 <1977600000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2073600000 { |
| opp-hz = /bits/ 64 <2073600000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2169600000 { |
| opp-hz = /bits/ 64 <2169600000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2284800000 { |
| opp-hz = /bits/ 64 <2284800000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2400000000 { |
| opp-hz = /bits/ 64 <2400000000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2496000000 { |
| opp-hz = /bits/ 64 <2496000000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2592000000 { |
| opp-hz = /bits/ 64 <2592000000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2688000000 { |
| opp-hz = /bits/ 64 <2688000000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2803200000 { |
| opp-hz = /bits/ 64 <2803200000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2899200000 { |
| opp-hz = /bits/ 64 <2899200000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| opp-2995200000 { |
| opp-hz = /bits/ 64 <2995200000>; |
| opp-peak-kBps = <(1689600 * 32)>; |
| }; |
| }; |
| |
| qup_opp_table_100mhz: opp-table-qup100mhz { |
| compatible = "operating-points-v2"; |
| |
| opp-75000000 { |
| opp-hz = /bits/ 64 <75000000>; |
| required-opps = <&rpmhpd_opp_low_svs>; |
| }; |
| |
| opp-100000000 { |
| opp-hz = /bits/ 64 <100000000>; |
| required-opps = <&rpmhpd_opp_svs>; |
| }; |
| }; |
| |
| pmu { |
| compatible = "arm,armv8-pmuv3"; |
| interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "smc"; |
| |
| CPU_PD0: power-domain-cpu0 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD1: power-domain-cpu1 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD2: power-domain-cpu2 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD3: power-domain-cpu3 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&LITTLE_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD4: power-domain-cpu4 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD5: power-domain-cpu5 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD6: power-domain-cpu6 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CPU_PD7: power-domain-cpu7 { |
| #power-domain-cells = <0>; |
| power-domains = <&CLUSTER_PD>; |
| domain-idle-states = <&BIG_CPU_SLEEP_0>; |
| }; |
| |
| CLUSTER_PD: power-domain-cpu-cluster0 { |
| #power-domain-cells = <0>; |
| domain-idle-states = <&CLUSTER_SLEEP_0>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| reserved-region@80000000 { |
| reg = <0 0x80000000 0 0x860000>; |
| no-map; |
| }; |
| |
| cmd_db: cmd-db-region@80860000 { |
| compatible = "qcom,cmd-db"; |
| reg = <0 0x80860000 0 0x20000>; |
| no-map; |
| }; |
| |
| reserved-region@80880000 { |
| reg = <0 0x80880000 0 0x80000>; |
| no-map; |
| }; |
| |
| smem_mem: smem-region@80900000 { |
| compatible = "qcom,smem"; |
| reg = <0 0x80900000 0 0x200000>; |
| no-map; |
| hwlocks = <&tcsr_mutex 3>; |
| }; |
| |
| reserved-region@80b00000 { |
| reg = <0 0x80b00000 0 0x100000>; |
| no-map; |
| }; |
| |
| reserved-region@83b00000 { |
| reg = <0 0x83b00000 0 0x1700000>; |
| no-map; |
| }; |
| |
| reserved-region@85b00000 { |
| reg = <0 0x85b00000 0 0xc00000>; |
| no-map; |
| }; |
| |
| pil_adsp_mem: adsp-region@86c00000 { |
| reg = <0 0x86c00000 0 0x2000000>; |
| no-map; |
| }; |
| |
| pil_nsp0_mem: cdsp0-region@8a100000 { |
| reg = <0 0x8a100000 0 0x1e00000>; |
| no-map; |
| }; |
| |
| pil_nsp1_mem: cdsp1-region@8c600000 { |
| reg = <0 0x8c600000 0 0x1e00000>; |
| no-map; |
| }; |
| |
| reserved-region@aeb00000 { |
| reg = <0 0xaeb00000 0 0x16600000>; |
| no-map; |
| }; |
| }; |
| |
| smp2p-adsp { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <443>, <429>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <2>; |
| |
| smp2p_adsp_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_adsp_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-nsp0 { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <94>, <432>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_CDSP |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <5>; |
| |
| smp2p_nsp0_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_nsp0_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| smp2p-nsp1 { |
| compatible = "qcom,smp2p"; |
| qcom,smem = <617>, <616>; |
| interrupts-extended = <&ipcc IPCC_CLIENT_NSP1 |
| IPCC_MPROC_SIGNAL_SMP2P |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_NSP1 |
| IPCC_MPROC_SIGNAL_SMP2P>; |
| |
| qcom,local-pid = <0>; |
| qcom,remote-pid = <12>; |
| |
| smp2p_nsp1_out: master-kernel { |
| qcom,entry-name = "master-kernel"; |
| #qcom,smem-state-cells = <1>; |
| }; |
| |
| smp2p_nsp1_in: slave-kernel { |
| qcom,entry-name = "slave-kernel"; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| }; |
| |
| soc: soc@0 { |
| compatible = "simple-bus"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0 0 0 0x10 0>; |
| dma-ranges = <0 0 0 0 0x10 0>; |
| |
| ethernet0: ethernet@20000 { |
| compatible = "qcom,sc8280xp-ethqos"; |
| reg = <0x0 0x00020000 0x0 0x10000>, |
| <0x0 0x00036000 0x0 0x100>; |
| reg-names = "stmmaceth", "rgmii"; |
| |
| clocks = <&gcc GCC_EMAC0_AXI_CLK>, |
| <&gcc GCC_EMAC0_SLV_AHB_CLK>, |
| <&gcc GCC_EMAC0_PTP_CLK>, |
| <&gcc GCC_EMAC0_RGMII_CLK>; |
| clock-names = "stmmaceth", |
| "pclk", |
| "ptp_ref", |
| "rgmii"; |
| |
| interrupts = <GIC_SPI 946 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 936 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "macirq", "eth_lpi"; |
| |
| iommus = <&apps_smmu 0x4c0 0xf>; |
| power-domains = <&gcc EMAC_0_GDSC>; |
| |
| snps,tso; |
| snps,pbl = <32>; |
| rx-fifo-depth = <4096>; |
| tx-fifo-depth = <4096>; |
| |
| status = "disabled"; |
| }; |
| |
| gcc: clock-controller@100000 { |
| compatible = "qcom,gcc-sc8280xp"; |
| reg = <0x0 0x00100000 0x0 0x1f0000>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&sleep_clk>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <&usb_0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <0>, |
| <&pcie2a_phy>, |
| <&pcie2b_phy>, |
| <&pcie3a_phy>, |
| <&pcie3b_phy>, |
| <&pcie4_phy>, |
| <0>, |
| <0>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| }; |
| |
| ipcc: mailbox@408000 { |
| compatible = "qcom,sc8280xp-ipcc", "qcom,ipcc"; |
| reg = <0 0x00408000 0 0x1000>; |
| interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-controller; |
| #interrupt-cells = <3>; |
| #mbox-cells = <2>; |
| }; |
| |
| qfprom: efuse@784000 { |
| compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; |
| reg = <0 0x00784000 0 0x3000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| gpu_speed_bin: gpu-speed-bin@18b { |
| reg = <0x18b 0x1>; |
| bits = <5 3>; |
| }; |
| }; |
| |
| qup2: geniqup@8c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x008c0000 0 0x2000>; |
| clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| iommus = <&apps_smmu 0xa3 0>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c16: i2c@880000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00880000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi16: spi@880000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00880000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c17: i2c@884000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00884000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi17: spi@884000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00884000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| uart17: serial@884000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00884000 0 0x4000>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; |
| operating-points-v2 = <&qup_opp_table_100mhz>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>; |
| interconnect-names = "qup-core", "qup-config"; |
| status = "disabled"; |
| }; |
| |
| i2c18: i2c@888000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00888000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi18: spi@888000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00888000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c19: i2c@88c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0088c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi19: spi@88c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0088c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c20: i2c@890000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00890000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi20: spi@890000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00890000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c21: i2c@894000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00894000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi21: spi@894000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00894000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c22: i2c@898000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00898000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; |
| interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi22: spi@898000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00898000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c23: i2c@89c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0089c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; |
| interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi23: spi@89c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0089c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_2 0 &clk_virt SLAVE_QUP_CORE_2 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_2 0>, |
| <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| }; |
| |
| qup0: geniqup@9c0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x009c0000 0 0x6000>; |
| clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| iommus = <&apps_smmu 0x563 0>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c0: i2c@980000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00980000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi0: spi@980000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00980000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@984000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00984000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi1: spi@984000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00984000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@988000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00988000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi2: spi@988000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00988000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| uart2: serial@988000 { |
| compatible = "qcom,geni-uart"; |
| reg = <0 0x00988000 0 0x4000>; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; |
| operating-points-v2 = <&qup_opp_table_100mhz>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>; |
| interconnect-names = "qup-core", "qup-config"; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@98c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0098c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi3: spi@98c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0098c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@990000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00990000 0 0x4000>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi4: spi@990000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00990000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@994000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00994000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi5: spi@994000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00994000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c6: i2c@998000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00998000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi6: spi@998000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00998000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c7: i2c@99c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x0099c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-names = "se"; |
| clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi7: spi@99c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x0099c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP2_S7_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>, |
| <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| }; |
| |
| qup1: geniqup@ac0000 { |
| compatible = "qcom,geni-se-qup"; |
| reg = <0 0x00ac0000 0 0x6000>; |
| clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| clock-names = "m-ahb", "s-ahb"; |
| iommus = <&apps_smmu 0x83 0>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| status = "disabled"; |
| |
| i2c8: i2c@a80000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a80000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi8: spi@a80000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a80000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c9: i2c@a84000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a84000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi9: spi@a84000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a84000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c10: i2c@a88000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a88000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi10: spi@a88000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a88000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c11: i2c@a8c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi11: spi@a8c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a8c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c12: i2c@a90000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a90000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi12: spi@a90000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a90000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c13: i2c@a94000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a94000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi13: spi@a94000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a94000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c14: i2c@a98000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a98000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi14: spi@a98000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a98000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| i2c15: i2c@a9c000 { |
| compatible = "qcom,geni-i2c"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| |
| spi15: spi@a9c000 { |
| compatible = "qcom,geni-spi"; |
| reg = <0 0x00a9c000 0 0x4000>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; |
| clock-names = "se"; |
| interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; |
| power-domains = <&rpmhpd SC8280XP_CX>; |
| interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>, |
| <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "qup-core", "qup-config", "qup-memory"; |
| status = "disabled"; |
| }; |
| }; |
| |
| rng: rng@10d3000 { |
| compatible = "qcom,prng-ee"; |
| reg = <0 0x010d3000 0 0x1000>; |
| clocks = <&rpmhcc RPMH_HWKM_CLK>; |
| clock-names = "core"; |
| }; |
| |
| pcie4: pcie@1c00000 { |
| device_type = "pci"; |
| compatible = "qcom,pcie-sc8280xp"; |
| reg = <0x0 0x01c00000 0x0 0x3000>, |
| <0x0 0x30000000 0x0 0xf1d>, |
| <0x0 0x30000f20 0x0 0xa8>, |
| <0x0 0x30001000 0x0 0x1000>, |
| <0x0 0x30100000 0x0 0x100000>, |
| <0x0 0x01c03000 0x0 0x1000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x00000000 0x0 0x30200000 0x0 0x100000>, |
| <0x02000000 0x0 0x30300000 0x0 0x30300000 0x0 0x1d00000>; |
| bus-range = <0x00 0xff>; |
| |
| dma-coherent; |
| |
| linux,pci-domain = <6>; |
| num-lanes = <1>; |
| |
| msi-map = <0x0 &its 0xe0000 0x10000>; |
| |
| interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_PCIE_4_AUX_CLK>, |
| <&gcc GCC_PCIE_4_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_4_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_4_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>, |
| <&gcc GCC_CNOC_PCIE4_QX_CLK>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ddrss_sf_tbu", |
| "noc_aggr_4", |
| "noc_aggr_south_sf", |
| "cnoc_qx"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| interconnects = <&aggre2_noc MASTER_PCIE_4 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_4 0>; |
| interconnect-names = "pcie-mem", "cpu-pcie"; |
| |
| resets = <&gcc GCC_PCIE_4_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_4_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| phys = <&pcie4_phy>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| |
| pcie4_port0: pcie@0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| bus-range = <0x01 0xff>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| }; |
| }; |
| |
| pcie4_phy: phy@1c06000 { |
| compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy"; |
| reg = <0x0 0x01c06000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_4_AUX_CLK>, |
| <&gcc GCC_PCIE_4_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_4_CLKREF_CLK>, |
| <&gcc GCC_PCIE4_PHY_RCHNG_CLK>, |
| <&gcc GCC_PCIE_4_PIPE_CLK>, |
| <&gcc GCC_PCIE_4_PIPEDIV2_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "rchng", |
| "pipe", "pipediv2"; |
| |
| assigned-clocks = <&gcc GCC_PCIE4_PHY_RCHNG_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_4_GDSC>; |
| |
| resets = <&gcc GCC_PCIE_4_PHY_BCR>; |
| reset-names = "phy"; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_4_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie3b: pcie@1c08000 { |
| device_type = "pci"; |
| compatible = "qcom,pcie-sc8280xp"; |
| reg = <0x0 0x01c08000 0x0 0x3000>, |
| <0x0 0x32000000 0x0 0xf1d>, |
| <0x0 0x32000f20 0x0 0xa8>, |
| <0x0 0x32001000 0x0 0x1000>, |
| <0x0 0x32100000 0x0 0x100000>, |
| <0x0 0x01c0b000 0x0 0x1000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x00000000 0x0 0x32200000 0x0 0x100000>, |
| <0x02000000 0x0 0x32300000 0x0 0x32300000 0x0 0x1d00000>; |
| bus-range = <0x00 0xff>; |
| |
| dma-coherent; |
| |
| linux,pci-domain = <5>; |
| num-lanes = <2>; |
| |
| msi-map = <0x0 &its 0xd0000 0x10000>; |
| |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 2 &intc 0 0 GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 3 &intc 0 0 GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 4 &intc 0 0 GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, |
| <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_3B_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_3B_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_3B_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ddrss_sf_tbu", |
| "noc_aggr_4", |
| "noc_aggr_south_sf"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_3B_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| interconnects = <&aggre2_noc MASTER_PCIE_3B 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3B 0>; |
| interconnect-names = "pcie-mem", "cpu-pcie"; |
| |
| resets = <&gcc GCC_PCIE_3B_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_3B_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| phys = <&pcie3b_phy>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| |
| pcie3b_port0: pcie@0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| bus-range = <0x01 0xff>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| }; |
| }; |
| |
| pcie3b_phy: phy@1c0e000 { |
| compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; |
| reg = <0x0 0x01c0e000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_3B_AUX_CLK>, |
| <&gcc GCC_PCIE_3B_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, |
| <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>, |
| <&gcc GCC_PCIE_3B_PIPE_CLK>, |
| <&gcc GCC_PCIE_3B_PIPEDIV2_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "rchng", |
| "pipe", "pipediv2"; |
| |
| assigned-clocks = <&gcc GCC_PCIE3B_PHY_RCHNG_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_3B_GDSC>; |
| |
| resets = <&gcc GCC_PCIE_3B_PHY_BCR>; |
| reset-names = "phy"; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_3b_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie3a: pcie@1c10000 { |
| device_type = "pci"; |
| compatible = "qcom,pcie-sc8280xp"; |
| reg = <0x0 0x01c10000 0x0 0x3000>, |
| <0x0 0x34000000 0x0 0xf1d>, |
| <0x0 0x34000f20 0x0 0xa8>, |
| <0x0 0x34001000 0x0 0x1000>, |
| <0x0 0x34100000 0x0 0x100000>, |
| <0x0 0x01c13000 0x0 0x1000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x00000000 0x0 0x34200000 0x0 0x100000>, |
| <0x02000000 0x0 0x34300000 0x0 0x34300000 0x0 0x1d00000>; |
| bus-range = <0x00 0xff>; |
| |
| dma-coherent; |
| |
| linux,pci-domain = <4>; |
| num-lanes = <4>; |
| |
| msi-map = <0x0 &its 0xc0000 0x10000>; |
| |
| interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 2 &intc 0 0 GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 3 &intc 0 0 GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 4 &intc 0 0 GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, |
| <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_3A_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_3A_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_3A_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ddrss_sf_tbu", |
| "noc_aggr_4", |
| "noc_aggr_south_sf"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_3A_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| interconnects = <&aggre2_noc MASTER_PCIE_3A 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_3A 0>; |
| interconnect-names = "pcie-mem", "cpu-pcie"; |
| |
| resets = <&gcc GCC_PCIE_3A_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_3A_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| phys = <&pcie3a_phy>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| |
| pcie3a_port0: pcie@0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| bus-range = <0x01 0xff>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| }; |
| }; |
| |
| pcie3a_phy: phy@1c14000 { |
| compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; |
| reg = <0x0 0x01c14000 0x0 0x2000>, |
| <0x0 0x01c16000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_3A_AUX_CLK>, |
| <&gcc GCC_PCIE_3A_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_3A3B_CLKREF_CLK>, |
| <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>, |
| <&gcc GCC_PCIE_3A_PIPE_CLK>, |
| <&gcc GCC_PCIE_3A_PIPEDIV2_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "rchng", |
| "pipe", "pipediv2"; |
| |
| assigned-clocks = <&gcc GCC_PCIE3A_PHY_RCHNG_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_3A_GDSC>; |
| |
| resets = <&gcc GCC_PCIE_3A_PHY_BCR>; |
| reset-names = "phy"; |
| |
| qcom,4ln-config-sel = <&tcsr 0xa044 1>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_3a_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie2b: pcie@1c18000 { |
| device_type = "pci"; |
| compatible = "qcom,pcie-sc8280xp"; |
| reg = <0x0 0x01c18000 0x0 0x3000>, |
| <0x0 0x38000000 0x0 0xf1d>, |
| <0x0 0x38000f20 0x0 0xa8>, |
| <0x0 0x38001000 0x0 0x1000>, |
| <0x0 0x38100000 0x0 0x100000>, |
| <0x0 0x01c1b000 0x0 0x1000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x00000000 0x0 0x38200000 0x0 0x100000>, |
| <0x02000000 0x0 0x38300000 0x0 0x38300000 0x0 0x1d00000>; |
| bus-range = <0x00 0xff>; |
| |
| dma-coherent; |
| |
| linux,pci-domain = <3>; |
| num-lanes = <2>; |
| |
| msi-map = <0x0 &its 0xb0000 0x10000>; |
| |
| interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 2 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 3 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 4 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, |
| <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_2B_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_2B_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_2B_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ddrss_sf_tbu", |
| "noc_aggr_4", |
| "noc_aggr_south_sf"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_2B_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| interconnects = <&aggre2_noc MASTER_PCIE_2B 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2B 0>; |
| interconnect-names = "pcie-mem", "cpu-pcie"; |
| |
| resets = <&gcc GCC_PCIE_2B_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_2B_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| phys = <&pcie2b_phy>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| |
| pcie2b_port0: pcie@0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| bus-range = <0x01 0xff>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| }; |
| }; |
| |
| pcie2b_phy: phy@1c1e000 { |
| compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy"; |
| reg = <0x0 0x01c1e000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_2B_AUX_CLK>, |
| <&gcc GCC_PCIE_2B_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, |
| <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>, |
| <&gcc GCC_PCIE_2B_PIPE_CLK>, |
| <&gcc GCC_PCIE_2B_PIPEDIV2_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "rchng", |
| "pipe", "pipediv2"; |
| |
| assigned-clocks = <&gcc GCC_PCIE2B_PHY_RCHNG_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_2B_GDSC>; |
| |
| resets = <&gcc GCC_PCIE_2B_PHY_BCR>; |
| reset-names = "phy"; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_2b_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| pcie2a: pcie@1c20000 { |
| device_type = "pci"; |
| compatible = "qcom,pcie-sc8280xp"; |
| reg = <0x0 0x01c20000 0x0 0x3000>, |
| <0x0 0x3c000000 0x0 0xf1d>, |
| <0x0 0x3c000f20 0x0 0xa8>, |
| <0x0 0x3c001000 0x0 0x1000>, |
| <0x0 0x3c100000 0x0 0x100000>, |
| <0x0 0x01c23000 0x0 0x1000>; |
| reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges = <0x01000000 0x0 0x00000000 0x0 0x3c200000 0x0 0x100000>, |
| <0x02000000 0x0 0x3c300000 0x0 0x3c300000 0x0 0x1d00000>; |
| bus-range = <0x00 0xff>; |
| |
| dma-coherent; |
| |
| linux,pci-domain = <2>; |
| num-lanes = <4>; |
| |
| msi-map = <0x0 &its 0xa0000 0x10000>; |
| |
| interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "msi0", "msi1", "msi2", "msi3"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0x7>; |
| interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 2 &intc 0 0 GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 3 &intc 0 0 GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, |
| <0 0 0 4 &intc 0 0 GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, |
| <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_2A_MSTR_AXI_CLK>, |
| <&gcc GCC_PCIE_2A_SLV_AXI_CLK>, |
| <&gcc GCC_PCIE_2A_SLV_Q2A_AXI_CLK>, |
| <&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_4_AXI_CLK>, |
| <&gcc GCC_AGGRE_NOC_PCIE_SOUTH_SF_AXI_CLK>; |
| clock-names = "aux", |
| "cfg", |
| "bus_master", |
| "bus_slave", |
| "slave_q2a", |
| "ddrss_sf_tbu", |
| "noc_aggr_4", |
| "noc_aggr_south_sf"; |
| |
| assigned-clocks = <&gcc GCC_PCIE_2A_AUX_CLK>; |
| assigned-clock-rates = <19200000>; |
| |
| interconnects = <&aggre2_noc MASTER_PCIE_2A 0 &mc_virt SLAVE_EBI1 0>, |
| <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_2A 0>; |
| interconnect-names = "pcie-mem", "cpu-pcie"; |
| |
| resets = <&gcc GCC_PCIE_2A_BCR>; |
| reset-names = "pci"; |
| |
| power-domains = <&gcc PCIE_2A_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| phys = <&pcie2a_phy>; |
| phy-names = "pciephy"; |
| |
| status = "disabled"; |
| |
| pcie2a_port0: pcie@0 { |
| device_type = "pci"; |
| reg = <0x0 0x0 0x0 0x0 0x0>; |
| bus-range = <0x01 0xff>; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| }; |
| }; |
| |
| pcie2a_phy: phy@1c24000 { |
| compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy"; |
| reg = <0x0 0x01c24000 0x0 0x2000>, |
| <0x0 0x01c26000 0x0 0x2000>; |
| |
| clocks = <&gcc GCC_PCIE_2A_AUX_CLK>, |
| <&gcc GCC_PCIE_2A_CFG_AHB_CLK>, |
| <&gcc GCC_PCIE_2A2B_CLKREF_CLK>, |
| <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>, |
| <&gcc GCC_PCIE_2A_PIPE_CLK>, |
| <&gcc GCC_PCIE_2A_PIPEDIV2_CLK>; |
| clock-names = "aux", "cfg_ahb", "ref", "rchng", |
| "pipe", "pipediv2"; |
| |
| assigned-clocks = <&gcc GCC_PCIE2A_PHY_RCHNG_CLK>; |
| assigned-clock-rates = <100000000>; |
| |
| power-domains = <&gcc PCIE_2A_GDSC>; |
| |
| resets = <&gcc GCC_PCIE_2A_PHY_BCR>; |
| reset-names = "phy"; |
| |
| qcom,4ln-config-sel = <&tcsr 0xa044 0>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "pcie_2a_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| ufs_mem_hc: ufs@1d84000 { |
| compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", |
| "jedec,ufs-2.0"; |
| reg = <0 0x01d84000 0 0x3000>; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufs_mem_phy>; |
| phy-names = "ufsphy"; |
| lanes-per-direction = <2>; |
| #reset-cells = <1>; |
| resets = <&gcc GCC_UFS_PHY_BCR>; |
| reset-names = "rst"; |
| |
| power-domains = <&gcc UFS_PHY_GDSC>; |
| required-opps = <&rpmhpd_opp_nom>; |
| |
| iommus = <&apps_smmu 0xe0 0x0>; |
| dma-coherent; |
| |
| clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, |
| <&gcc GCC_UFS_PHY_AHB_CLK>, |
| <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, |
| <&gcc GCC_UFS_REF_CLKREF_CLK>, |
| <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; |
| clock-names = "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| freq-table-hz = <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| status = "disabled"; |
| }; |
| |
| ufs_mem_phy: phy@1d87000 { |
| compatible = "qcom,sc8280xp-qmp-ufs-phy"; |
| reg = <0 0x01d87000 0 0x1000>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, |
| <&gcc GCC_UFS_CARD_CLKREF_CLK>; |
| clock-names = "ref", |
| "ref_aux", |
| "qref"; |
| |
| power-domains = <&gcc UFS_PHY_GDSC>; |
| |
| resets = <&ufs_mem_hc 0>; |
| reset-names = "ufsphy"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| ufs_card_hc: ufs@1da4000 { |
| compatible = "qcom,sc8280xp-ufshc", "qcom,ufshc", |
| "jedec,ufs-2.0"; |
| reg = <0 0x01da4000 0 0x3000>; |
| interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; |
| phys = <&ufs_card_phy>; |
| phy-names = "ufsphy"; |
| lanes-per-direction = <2>; |
| #reset-cells = <1>; |
| resets = <&gcc GCC_UFS_CARD_BCR>; |
| reset-names = "rst"; |
| |
| power-domains = <&gcc UFS_CARD_GDSC>; |
| |
| iommus = <&apps_smmu 0x4a0 0x0>; |
| dma-coherent; |
| |
| clocks = <&gcc GCC_UFS_CARD_AXI_CLK>, |
| <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>, |
| <&gcc GCC_UFS_CARD_AHB_CLK>, |
| <&gcc GCC_UFS_CARD_UNIPRO_CORE_CLK>, |
| <&gcc GCC_UFS_REF_CLKREF_CLK>, |
| <&gcc GCC_UFS_CARD_TX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_CARD_RX_SYMBOL_0_CLK>, |
| <&gcc GCC_UFS_CARD_RX_SYMBOL_1_CLK>; |
| clock-names = "core_clk", |
| "bus_aggr_clk", |
| "iface_clk", |
| "core_clk_unipro", |
| "ref_clk", |
| "tx_lane0_sync_clk", |
| "rx_lane0_sync_clk", |
| "rx_lane1_sync_clk"; |
| freq-table-hz = <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <75000000 300000000>, |
| <0 0>, |
| <0 0>, |
| <0 0>, |
| <0 0>; |
| status = "disabled"; |
| }; |
| |
| ufs_card_phy: phy@1da7000 { |
| compatible = "qcom,sc8280xp-qmp-ufs-phy"; |
| reg = <0 0x01da7000 0 0x1000>; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_UFS_CARD_PHY_AUX_CLK>, |
| <&gcc GCC_UFS_1_CARD_CLKREF_CLK>; |
| clock-names = "ref", |
| "ref_aux", |
| "qref"; |
| |
| power-domains = <&gcc UFS_CARD_GDSC>; |
| |
| resets = <&ufs_card_hc 0>; |
| reset-names = "ufsphy"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| tcsr_mutex: hwlock@1f40000 { |
| compatible = "qcom,tcsr-mutex"; |
| reg = <0x0 0x01f40000 0x0 0x20000>; |
| #hwlock-cells = <1>; |
| }; |
| |
| tcsr: syscon@1fc0000 { |
| compatible = "qcom,sc8280xp-tcsr", "syscon"; |
| reg = <0x0 0x01fc0000 0x0 0x30000>; |
| }; |
| |
| gpu: gpu@3d00000 { |
| compatible = "qcom,adreno-690.0", "qcom,adreno"; |
| |
| reg = <0 0x03d00000 0 0x40000>, |
| <0 0x03d9e000 0 0x1000>, |
| <0 0x03d61000 0 0x800>; |
| reg-names = "kgsl_3d0_reg_memory", |
| "cx_mem", |
| "cx_dbgc"; |
| interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; |
| iommus = <&gpu_smmu 0 0xc00>, <&gpu_smmu 1 0xc00>; |
| operating-points-v2 = <&gpu_opp_table>; |
| |
| qcom,gmu = <&gmu>; |
| interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; |
| interconnect-names = "gfx-mem"; |
| #cooling-cells = <2>; |
| |
| status = "disabled"; |
| |
| gpu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-270000000 { |
| opp-hz = /bits/ 64 <270000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; |
| opp-peak-kBps = <451000>; |
| }; |
| |
| opp-410000000 { |
| opp-hz = /bits/ 64 <410000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| opp-peak-kBps = <1555000>; |
| }; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; |
| opp-peak-kBps = <1555000>; |
| }; |
| |
| opp-547000000 { |
| opp-hz = /bits/ 64 <547000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; |
| opp-peak-kBps = <1555000>; |
| }; |
| |
| opp-606000000 { |
| opp-hz = /bits/ 64 <606000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM>; |
| opp-peak-kBps = <2736000>; |
| }; |
| |
| opp-640000000 { |
| opp-hz = /bits/ 64 <640000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; |
| opp-peak-kBps = <2736000>; |
| }; |
| |
| opp-655000000 { |
| opp-hz = /bits/ 64 <655000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; |
| opp-peak-kBps = <2736000>; |
| }; |
| |
| opp-690000000 { |
| opp-hz = /bits/ 64 <690000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; |
| opp-peak-kBps = <2736000>; |
| }; |
| }; |
| }; |
| |
| gmu: gmu@3d6a000 { |
| compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu"; |
| reg = <0 0x03d6a000 0 0x34000>, |
| <0 0x03de0000 0 0x10000>, |
| <0 0x0b290000 0 0x10000>; |
| reg-names = "gmu", "rscc", "gmu_pdc"; |
| interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "hfi", "gmu"; |
| clocks = <&gpucc GPU_CC_CX_GMU_CLK>, |
| <&gpucc GPU_CC_CXO_CLK>, |
| <&gcc GCC_DDRSS_GPU_AXI_CLK>, |
| <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| <&gpucc GPU_CC_AHB_CLK>, |
| <&gpucc GPU_CC_HUB_CX_INT_CLK>, |
| <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; |
| clock-names = "gmu", |
| "cxo", |
| "axi", |
| "memnoc", |
| "ahb", |
| "hub", |
| "smmu_vote"; |
| power-domains = <&gpucc GPU_CC_CX_GDSC>, |
| <&gpucc GPU_CC_GX_GDSC>; |
| power-domain-names = "cx", |
| "gx"; |
| iommus = <&gpu_smmu 5 0xc00>; |
| operating-points-v2 = <&gmu_opp_table>; |
| |
| gmu_opp_table: opp-table { |
| compatible = "operating-points-v2"; |
| |
| opp-200000000 { |
| opp-hz = /bits/ 64 <200000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; |
| }; |
| |
| opp-500000000 { |
| opp-hz = /bits/ 64 <500000000>; |
| opp-level = <RPMH_REGULATOR_LEVEL_SVS>; |
| }; |
| }; |
| }; |
| |
| gpucc: clock-controller@3d90000 { |
| compatible = "qcom,sc8280xp-gpucc"; |
| reg = <0 0x03d90000 0 0x9000>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>, |
| <&gcc GCC_GPU_GPLL0_CLK_SRC>, |
| <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; |
| clock-names = "bi_tcxo", |
| "gcc_gpu_gpll0_clk_src", |
| "gcc_gpu_gpll0_div_clk_src"; |
| |
| power-domains = <&rpmhpd SC8280XP_GFX>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| }; |
| |
| gpu_smmu: iommu@3da0000 { |
| compatible = "qcom,sc8280xp-smmu-500", "qcom,adreno-smmu", |
| "qcom,smmu-500", "arm,mmu-500"; |
| reg = <0 0x03da0000 0 0x20000>; |
| #iommu-cells = <2>; |
| #global-interrupts = <2>; |
| interrupts = <GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 689 IRQ_TYPE_LEVEL_HIGH>; |
| |
| clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, |
| <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, |
| <&gpucc GPU_CC_AHB_CLK>, |
| <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, |
| <&gpucc GPU_CC_CX_GMU_CLK>, |
| <&gpucc GPU_CC_HUB_CX_INT_CLK>, |
| <&gpucc GPU_CC_HUB_AON_CLK>; |
| clock-names = "gcc_gpu_memnoc_gfx_clk", |
| "gcc_gpu_snoc_dvm_gfx_clk", |
| "gpu_cc_ahb_clk", |
| "gpu_cc_hlos1_vote_gpu_smmu_clk", |
| "gpu_cc_cx_gmu_clk", |
| "gpu_cc_hub_cx_int_clk", |
| "gpu_cc_hub_aon_clk"; |
| |
| power-domains = <&gpucc GPU_CC_CX_GDSC>; |
| dma-coherent; |
| }; |
| |
| usb_0_hsphy: phy@88e5000 { |
| compatible = "qcom,sc8280xp-usb-hs-phy", |
| "qcom,usb-snps-hs-5nm-phy"; |
| reg = <0 0x088e5000 0 0x400>; |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_hsphy0: phy@88e7000 { |
| compatible = "qcom,sc8280xp-usb-hs-phy", |
| "qcom,usb-snps-hs-5nm-phy"; |
| reg = <0 0x088e7000 0 0x400>; |
| clocks = <&gcc GCC_USB2_HS0_CLKREF_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_HS0_MP_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_hsphy1: phy@88e8000 { |
| compatible = "qcom,sc8280xp-usb-hs-phy", |
| "qcom,usb-snps-hs-5nm-phy"; |
| reg = <0 0x088e8000 0 0x400>; |
| clocks = <&gcc GCC_USB2_HS1_CLKREF_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_HS1_MP_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_hsphy2: phy@88e9000 { |
| compatible = "qcom,sc8280xp-usb-hs-phy", |
| "qcom,usb-snps-hs-5nm-phy"; |
| reg = <0 0x088e9000 0 0x400>; |
| clocks = <&gcc GCC_USB2_HS2_CLKREF_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_HS2_MP_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_hsphy3: phy@88ea000 { |
| compatible = "qcom,sc8280xp-usb-hs-phy", |
| "qcom,usb-snps-hs-5nm-phy"; |
| reg = <0 0x088ea000 0 0x400>; |
| clocks = <&gcc GCC_USB2_HS3_CLKREF_CLK>; |
| clock-names = "ref"; |
| resets = <&gcc GCC_QUSB2PHY_HS3_MP_BCR>; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_qmpphy0: phy@88ef000 { |
| compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; |
| reg = <0 0x088ef000 0 0x2000>; |
| |
| clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, |
| <&gcc GCC_USB3_MP0_CLKREF_CLK>, |
| <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, |
| <&gcc GCC_USB3_MP_PHY_PIPE_0_CLK>; |
| clock-names = "aux", "ref", "com_aux", "pipe"; |
| |
| resets = <&gcc GCC_USB3_UNIPHY_MP0_BCR>, |
| <&gcc GCC_USB3UNIPHY_PHY_MP0_BCR>; |
| reset-names = "phy", "phy_phy"; |
| |
| power-domains = <&gcc USB30_MP_GDSC>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "usb2_phy0_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| usb_2_qmpphy1: phy@88f1000 { |
| compatible = "qcom,sc8280xp-qmp-usb3-uni-phy"; |
| reg = <0 0x088f1000 0 0x2000>; |
| |
| clocks = <&gcc GCC_USB3_MP_PHY_AUX_CLK>, |
| <&gcc GCC_USB3_MP1_CLKREF_CLK>, |
| <&gcc GCC_USB3_MP_PHY_COM_AUX_CLK>, |
| <&gcc GCC_USB3_MP_PHY_PIPE_1_CLK>; |
| clock-names = "aux", "ref", "com_aux", "pipe"; |
| |
| resets = <&gcc GCC_USB3_UNIPHY_MP1_BCR>, |
| <&gcc GCC_USB3UNIPHY_PHY_MP1_BCR>; |
| reset-names = "phy", "phy_phy"; |
| |
| power-domains = <&gcc USB30_MP_GDSC>; |
| |
| #clock-cells = <0>; |
| clock-output-names = "usb2_phy1_pipe_clk"; |
| |
| #phy-cells = <0>; |
| |
| status = "disabled"; |
| }; |
| |
| remoteproc_adsp: remoteproc@3000000 { |
| compatible = "qcom,sc8280xp-adsp-pas"; |
| reg = <0 0x03000000 0 0x100>; |
| |
| interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, |
| <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "wdog", "fatal", "ready", |
| "handover", "stop-ack", "shutdown-ack"; |
| |
| clocks = <&rpmhcc RPMH_CXO_CLK>; |
| clock-names = "xo"; |
| |
| power-domains = <&rpmhpd SC8280XP_LCX>, |
| <&rpmhpd SC8280XP_LMX>; |
| power-domain-names = "lcx", "lmx"; |
| |
| memory-region = <&pil_adsp_mem>; |
| |
| qcom,qmp = <&aoss_qmp>; |
| |
| qcom,smem-states = <&smp2p_adsp_out 0>; |
| qcom,smem-state-names = "stop"; |
| |
| status = "disabled"; |
| |
| remoteproc_adsp_glink: glink-edge { |
| interrupts-extended = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP |
| IRQ_TYPE_EDGE_RISING>; |
| mboxes = <&ipcc IPCC_CLIENT_LPASS |
| IPCC_MPROC_SIGNAL_GLINK_QMP>; |
| |
| label = "lpass"; |
| qcom,remote-pid = <2>; |
| |
| gpr { |
| compatible = "qcom,gpr"; |
| qcom,glink-channels = "adsp_apps"; |
| qcom,domain = <GPR_DOMAIN_ID_ADSP>; |
| qcom,intents = <512 20>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| q6apm: service@1 { |
| compatible = "qcom,q6apm"; |
| reg = <GPR_APM_MODULE_IID>; |
| #sound-dai-cells = <0>; |
| qcom,protection-domain = "avs/audio", |
| "msm/adsp/audio_pd"; |
| q6apmdai: dais { |
| compatible = "qcom,q6apm-dais"; |
| iommus = <&apps_smmu 0x0c01 0x0>; |
| }; |
| |
| q6apmbedai: bedais { |
| compatible = "qcom,q6apm-lpass-dais"; |
| #sound-dai-cells = <1>; |
| }; |
| }; |
| |
| q6prm: service@2 { |
| compatible = "qcom,q6prm"; |
| reg = <GPR_PRM_MODULE_IID>; |
| qcom,protection-domain = "avs/audio", |
| "msm/adsp/audio_pd"; |
| q6prmcc: clock-controller { |
| compatible = "qcom,q6prm-lpass-clocks"; |
| #clock-cells = <2>; |
| }; |
| }; |
| }; |
| }; |
| }; |
| |
| rxmacro: rxmacro@3200000 { |
| compatible = "qcom,sc8280xp-lpass-rx-macro"; |
| reg = <0 0x03200000 0 0x1000>; |
| clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&vamacro>; |
| clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; |
| assigned-clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, |
| <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_2X_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>; |
| assigned-clock-rates = <19200000>, <19200000>; |
| |
| clock-output-names = "mclk"; |
| #clock-cells = <0>; |
| #sound-dai-cells = <1>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&rx_swr_default>; |
| |
| status = "disabled"; |
| }; |
| |
| swr1: soundwire@3210000 { |
| compatible = "qcom,soundwire-v1.6.0"; |
| reg = <0 0x03210000 0 0x2000>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&rxmacro>; |
| clock-names = "iface"; |
| resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; |
| reset-names = "swr_audio_cgcr"; |
| label = "RX"; |
| |
| qcom,din-ports = <0>; |
| qcom,dout-ports = <5>; |
| |
| qcom,ports-sinterval-low = /bits/ 8 <0x03 0x1f 0x1f 0x07 0x00>; |
| qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0B 0x01 0x00>; |
| qcom,ports-offset2 = /bits/ |