Merge tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull more SoC updates from Arnd Bergmann: "These are the contents that arrived during the easter vacation and didn't make it into the last 7.0 bugfixes or the first set of branches for the merge window. Aside from a reset controller bugfix and an update to the MAINTAINERS entry, this is all devicetree changes. The Marvell devicetree updates contain the usual minor updates and bugfixes, along with a two larger but trivial patches to drop unused dtsi files, the single broadcom fix addresses a build time warning introduced during the merge window. The freescale, amlogic, and apple changes missed the last fixes branch for 7.0" * tag 'soc-late-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (38 commits) arm64: dts: meson-gxl-p230: fix ethernet PHY interrupt number arm64: dts: amlogic: meson-axg: Add missing cache information to cpu0 arm64: dts: amlogic: t7: khadas-vim4: fix board model name arm64: dts: amlogic: Fix GIC register ranges for Amlogic T7 arm64: dts: amlogic: t7: khadas-vim4: fix memory layout for 8GB RAM arm64: dts: amlogic: s6: Drop CPU masks from GICv3 PPI interrupts Documentation/process: maintainer-soc: Document purpose of defconfigs Documentation/process: maintainer-soc: Trim from trivial ask-DT ARM: dts: bcm4709: fix bus range assignment arm64: dts: apple: Fix spelling error dt-bindings: Update Sasha Finkelstein's email address mailmap: Update Sasha Finkelstein's email address arm64: dts: marvell: armada-37xx: swap PHYs' order in USB3 controller node arm64: dts: marvell: armada-37xx: use 'usb2-phy' in USB3 controller's phy-names arm64: dts: imx8mm-tqma8mqml: Correct PAD settings for PMIC_nINT arm64: dts: imx8mn-tqma8mqnl: Correct PAD settings for PMIC_nINT arm64: dts: imx8mm-emtop-som: Correct PAD settings for PMIC_nINT reset: amlogic: t7: Fix null reset ops arm64: dts: imx8mp-data-modul-edm-sbc: Correct PAD settings for PMIC_nINT arm64: dts: imx8mp-dhcom-som: Correct PAD settings for PMIC_nINT ... [ upstream commit: 507bd4b66c85d5b65696150cc16d31ac0b2ab151 ]
diff --git a/Bindings/arm/marvell/armada-7k-8k.yaml b/Bindings/arm/marvell/armada-7k-8k.yaml index 4bc7454..7e77310 100644 --- a/Bindings/arm/marvell/armada-7k-8k.yaml +++ b/Bindings/arm/marvell/armada-7k-8k.yaml
@@ -21,6 +21,17 @@ - const: marvell,armada-ap806-dual - const: marvell,armada-ap806 + - description: + Falcon (DB-98CX85x0) Development board COM Express Carrier plus + Armada 7020 SoC COM Express CPU module + items: + - const: marvell,armada7020-falcon-carrier + - const: marvell,db-falcon-carrier + - const: marvell,armada7020-cpu-module + - const: marvell,armada7020 + - const: marvell,armada-ap806-dual + - const: marvell,armada-ap806 + - description: Armada 7040 SoC items: - enum:
diff --git a/Bindings/display/apple,h7-display-pipe-mipi.yaml b/Bindings/display/apple,h7-display-pipe-mipi.yaml index 5e6da66..d7c822d 100644 --- a/Bindings/display/apple,h7-display-pipe-mipi.yaml +++ b/Bindings/display/apple,h7-display-pipe-mipi.yaml
@@ -7,7 +7,7 @@ title: Apple pre-DCP display controller MIPI interface maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: The MIPI controller part of the pre-DCP Apple display controller
diff --git a/Bindings/display/apple,h7-display-pipe.yaml b/Bindings/display/apple,h7-display-pipe.yaml index 102fb18..571fa32 100644 --- a/Bindings/display/apple,h7-display-pipe.yaml +++ b/Bindings/display/apple,h7-display-pipe.yaml
@@ -7,7 +7,7 @@ title: Apple pre-DCP display controller maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A secondary display controller used to drive the "touchbar" on
diff --git a/Bindings/display/panel/apple,summit.yaml b/Bindings/display/panel/apple,summit.yaml index f081755..1c1ba59 100644 --- a/Bindings/display/panel/apple,summit.yaml +++ b/Bindings/display/panel/apple,summit.yaml
@@ -7,7 +7,7 @@ title: Apple "Summit" display panel maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: An OLED panel used as a touchbar on certain Apple laptops.
diff --git a/Bindings/gpu/apple,agx.yaml b/Bindings/gpu/apple,agx.yaml index 05af942..59989d8 100644 --- a/Bindings/gpu/apple,agx.yaml +++ b/Bindings/gpu/apple,agx.yaml
@@ -7,7 +7,7 @@ title: Apple SoC GPU maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> properties: compatible:
diff --git a/Bindings/input/touchscreen/apple,z2-multitouch.yaml b/Bindings/input/touchscreen/apple,z2-multitouch.yaml index 402ca6b..44158e8 100644 --- a/Bindings/input/touchscreen/apple,z2-multitouch.yaml +++ b/Bindings/input/touchscreen/apple,z2-multitouch.yaml
@@ -7,7 +7,7 @@ title: Apple touchscreens attached using the Z2 protocol maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A series of touschscreen controllers used in Apple products
diff --git a/Bindings/nvmem/apple,spmi-nvmem.yaml b/Bindings/nvmem/apple,spmi-nvmem.yaml index 80b5a6c..4ca75ed 100644 --- a/Bindings/nvmem/apple,spmi-nvmem.yaml +++ b/Bindings/nvmem/apple,spmi-nvmem.yaml
@@ -9,7 +9,7 @@ description: Exports a series of SPMI registers as NVMEM cells maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> allOf: - $ref: nvmem.yaml#
diff --git a/Bindings/pwm/apple,s5l-fpwm.yaml b/Bindings/pwm/apple,s5l-fpwm.yaml index 04519b0..d8f4f9f 100644 --- a/Bindings/pwm/apple,s5l-fpwm.yaml +++ b/Bindings/pwm/apple,s5l-fpwm.yaml
@@ -8,7 +8,7 @@ maintainers: - asahi@lists.linux.dev - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: PWM controller used for keyboard backlight on ARM Macs
diff --git a/Bindings/spmi/apple,spmi.yaml b/Bindings/spmi/apple,spmi.yaml index ba524f1..3e5b14b 100644 --- a/Bindings/spmi/apple,spmi.yaml +++ b/Bindings/spmi/apple,spmi.yaml
@@ -7,7 +7,7 @@ title: Apple SPMI controller maintainers: - - Sasha Finkelstein <fnkl.kernel@gmail.com> + - Sasha Finkelstein <k@chaosmail.tech> description: A SPMI controller present on most Apple SoCs
diff --git a/src/arm/broadcom/bcm4709-netgear-r8000.dts b/src/arm/broadcom/bcm4709-netgear-r8000.dts index d170c71..e85693f 100644 --- a/src/arm/broadcom/bcm4709-netgear-r8000.dts +++ b/src/arm/broadcom/bcm4709-netgear-r8000.dts
@@ -139,7 +139,6 @@ pcie@0,0 { device_type = "pci"; reg = <0x0000 0 0 0 0>; - bus-range = <0x01 0xff>; #address-cells = <3>; #size-cells = <2>;
diff --git a/src/arm/marvell/armada-380.dtsi b/src/arm/marvell/armada-380.dtsi deleted file mode 100644 index e94f22b..0000000 --- a/src/arm/marvell/armada-380.dtsi +++ /dev/null
@@ -1,148 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Device Tree Include file for Marvell Armada 380 SoC. - * - * Copyright (C) 2014 Marvell - * - * Lior Amsalem <alior@marvell.com> - * Gregory CLEMENT <gregory.clement@free-electrons.com> - * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> - */ - -#include "armada-38x.dtsi" - -/ { - model = "Marvell Armada 380 family SoC"; - compatible = "marvell,armada380"; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - enable-method = "marvell,armada-380-smp"; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,cortex-a9"; - reg = <0>; - }; - }; - - soc { - internal-regs { - pinctrl@18000 { - compatible = "marvell,mv88f6810-pinctrl"; - }; - }; - - pcie { - compatible = "marvell,armada-370-pcie"; - status = "disabled"; - device_type = "pci"; - - #address-cells = <3>; - #size-cells = <2>; - - msi-parent = <&mpic>; - bus-range = <0x00 0xff>; - - ranges = - <0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000 - 0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 - 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 - 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 - 0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */ - 0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */ - 0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */ - 0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */ - 0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */ - 0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */>; - - /* x1 port */ - pcie@1,0 { - device_type = "pci"; - assigned-addresses = <0x82000800 0 0x80000 0 0x2000>; - reg = <0x0800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 - 0x81000000 0 0 0x81000000 0x1 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie1_intc 0>, - <0 0 0 2 &pcie1_intc 1>, - <0 0 0 3 &pcie1_intc 2>, - <0 0 0 4 &pcie1_intc 3>; - marvell,pcie-port = <0>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 8>; - status = "disabled"; - - pcie1_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@2,0 { - device_type = "pci"; - assigned-addresses = <0x82001000 0 0x40000 0 0x2000>; - reg = <0x1000 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0 - 0x81000000 0 0 0x81000000 0x2 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie2_intc 0>, - <0 0 0 2 &pcie2_intc 1>, - <0 0 0 3 &pcie2_intc 2>, - <0 0 0 4 &pcie2_intc 3>; - marvell,pcie-port = <1>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 5>; - status = "disabled"; - - pcie2_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - - /* x1 port */ - pcie@3,0 { - device_type = "pci"; - assigned-addresses = <0x82001800 0 0x44000 0 0x2000>; - reg = <0x1800 0 0 0 0>; - #address-cells = <3>; - #size-cells = <2>; - interrupt-names = "intx"; - interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; - #interrupt-cells = <1>; - ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0 - 0x81000000 0 0 0x81000000 0x3 0 1 0>; - bus-range = <0x00 0xff>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &pcie3_intc 0>, - <0 0 0 2 &pcie3_intc 1>, - <0 0 0 3 &pcie3_intc 2>, - <0 0 0 4 &pcie3_intc 3>; - marvell,pcie-port = <2>; - marvell,pcie-lane = <0>; - clocks = <&gateclk 6>; - status = "disabled"; - - pcie3_intc: interrupt-controller { - interrupt-controller; - #interrupt-cells = <1>; - }; - }; - }; - }; -};
diff --git a/src/arm64/amlogic/amlogic-s6.dtsi b/src/arm64/amlogic/amlogic-s6.dtsi index 8ef63193..ab3acef 100644 --- a/src/arm64/amlogic/amlogic-s6.dtsi +++ b/src/arm64/amlogic/amlogic-s6.dtsi
@@ -53,10 +53,10 @@ timer { compatible = "arm,armv8-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, - <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; }; psci { @@ -84,7 +84,7 @@ interrupt-controller; reg = <0x0 0xff200000 0 0x10000>, <0x0 0xff240000 0 0x80000>; - interrupts = <GIC_PPI 9 0xf04>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; }; apb: bus@fe000000 {
diff --git a/src/arm64/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/src/arm64/amlogic/amlogic-t7-a311d2-khadas-vim4.dts index fffdab9..f4c9530 100644 --- a/src/arm64/amlogic/amlogic-t7-a311d2-khadas-vim4.dts +++ b/src/arm64/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
@@ -8,7 +8,7 @@ #include "amlogic-t7.dtsi" / { - model = "Khadas vim4"; + model = "Khadas VIM4"; compatible = "khadas,vim4", "amlogic,a311d2", "amlogic,t7"; aliases { @@ -17,7 +17,9 @@ memory@0 { device_type = "memory"; - reg = <0x0 0x0 0x2 0x0>; /* 8 GB */ + reg = <0x0 0x0 0x0 0xE0000000 + 0x1 0x0 0x0 0xE0000000 + 0x2 0x0 0x0 0x40000000>; /* 8 GB */ }; reserved-memory {
diff --git a/src/arm64/amlogic/amlogic-t7.dtsi b/src/arm64/amlogic/amlogic-t7.dtsi index 6510068..d523cbc 100644 --- a/src/arm64/amlogic/amlogic-t7.dtsi +++ b/src/arm64/amlogic/amlogic-t7.dtsi
@@ -213,7 +213,9 @@ #address-cells = <0>; interrupt-controller; reg = <0x0 0xfff01000 0 0x1000>, - <0x0 0xfff02000 0 0x0100>; + <0x0 0xfff02000 0 0x2000>, + <0x0 0xfff04000 0 0x2000>, + <0x0 0xfff06000 0 0x2000>; interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; };
diff --git a/src/arm64/amlogic/meson-axg.dtsi b/src/arm64/amlogic/meson-axg.dtsi index cc72491..f1f53fd 100644 --- a/src/arm64/amlogic/meson-axg.dtsi +++ b/src/arm64/amlogic/meson-axg.dtsi
@@ -72,6 +72,12 @@ compatible = "arm,cortex-a53"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; clocks = <&scpi_dvfs 0>; dynamic-power-coefficient = <140>;
diff --git a/src/arm64/amlogic/meson-gxl-s905d-p230.dts b/src/arm64/amlogic/meson-gxl-s905d-p230.dts index 7dffeb5..701de57 100644 --- a/src/arm64/amlogic/meson-gxl-s905d-p230.dts +++ b/src/arm64/amlogic/meson-gxl-s905d-p230.dts
@@ -84,7 +84,8 @@ reset-gpios = <&gpio GPIOZ_14 GPIO_ACTIVE_LOW>; interrupt-parent = <&gpio_intc>; - interrupts = <29 IRQ_TYPE_LEVEL_LOW>; + /* MAC_INTR on GPIOZ_15 */ + interrupts = <25 IRQ_TYPE_LEVEL_LOW>; eee-broken-1000t; }; };
diff --git a/src/arm64/apple/spi1-nvram.dtsi b/src/arm64/apple/spi1-nvram.dtsi index 9740fbf..d2720b3 100644 --- a/src/arm64/apple/spi1-nvram.dtsi +++ b/src/arm64/apple/spi1-nvram.dtsi
@@ -2,7 +2,7 @@ // // Devicetree include for common spi-nor nvram flash. // -// Apple uses a consistent configiguration for the nvram on all known M1* and +// Apple uses a consistent configuration for the nvram on all known M1* and // M2* devices. // // Copyright The Asahi Linux Contributors
diff --git a/src/arm64/freescale/imx8mm-emtop-som.dtsi b/src/arm64/freescale/imx8mm-emtop-som.dtsi index 67d22d3..507d182 100644 --- a/src/arm64/freescale/imx8mm-emtop-som.dtsi +++ b/src/arm64/freescale/imx8mm-emtop-som.dtsi
@@ -60,7 +60,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 IRQ_TYPE_EDGE_RISING>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; regulators { buck1: BUCK1 { @@ -194,7 +194,7 @@ pinctrl_pmic: emtop-pmic-grp { fsl,pins = < - MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41 + MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141 >; };
diff --git a/src/arm64/freescale/imx8mm-tqma8mqml.dtsi b/src/arm64/freescale/imx8mm-tqma8mqml.dtsi index 29b298a..1b5ba3c 100644 --- a/src/arm64/freescale/imx8mm-tqma8mqml.dtsi +++ b/src/arm64/freescale/imx8mm-tqma8mqml.dtsi
@@ -292,7 +292,7 @@ }; pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x94>; + fsl,pins = <MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1d4>; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
diff --git a/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi b/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi index 31a3ca1..48a6879 100644 --- a/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi +++ b/src/arm64/freescale/imx8mn-tqma8mqnl.dtsi
@@ -283,7 +283,7 @@ }; pinctrl_pmic: pmicgrp { - fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x84>; + fsl,pins = <MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x1c4>; }; pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
diff --git a/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi b/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi index f654d86..e7666e5 100644 --- a/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi +++ b/src/arm64/freescale/imx8mp-aristainetos3a-som-v1.dtsi
@@ -903,7 +903,7 @@ pinctrl_pmic: aristainetos3-pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts b/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts index 7e46537..cb28cf1 100644 --- a/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/src/arm64/freescale/imx8mp-data-modul-edm-sbc.dts
@@ -1001,7 +1001,7 @@ pinctrl_pmic: pmic-grp { fsl,pins = < /* PMIC_nINT */ - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-debix-model-a.dts b/src/arm64/freescale/imx8mp-debix-model-a.dts index 9422bee..201cf7f 100644 --- a/src/arm64/freescale/imx8mp-debix-model-a.dts +++ b/src/arm64/freescale/imx8mp-debix-model-a.dts
@@ -440,7 +440,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts b/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts index 04619a7..1471ff3 100644 --- a/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/src/arm64/freescale/imx8mp-debix-som-a-bmb-08.dts
@@ -499,7 +499,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-debix-som-a.dtsi b/src/arm64/freescale/imx8mp-debix-som-a.dtsi index 91094c2..b31e8fe 100644 --- a/src/arm64/freescale/imx8mp-debix-som-a.dtsi +++ b/src/arm64/freescale/imx8mp-debix-som-a.dtsi
@@ -241,7 +241,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-dhcom-som.dtsi b/src/arm64/freescale/imx8mp-dhcom-som.dtsi index f8303b7..0a6a606 100644 --- a/src/arm64/freescale/imx8mp-dhcom-som.dtsi +++ b/src/arm64/freescale/imx8mp-dhcom-som.dtsi
@@ -989,7 +989,7 @@ pinctrl_pmic: dhcom-pmic-grp { fsl,pins = < /* PMIC_nINT */ - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40000090 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-edm-g.dtsi b/src/arm64/freescale/imx8mp-edm-g.dtsi index 3f1e083..91b87a7 100644 --- a/src/arm64/freescale/imx8mp-edm-g.dtsi +++ b/src/arm64/freescale/imx8mp-edm-g.dtsi
@@ -563,7 +563,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-icore-mx8mp.dtsi b/src/arm64/freescale/imx8mp-icore-mx8mp.dtsi index a631982..69558ff 100644 --- a/src/arm64/freescale/imx8mp-icore-mx8mp.dtsi +++ b/src/arm64/freescale/imx8mp-icore-mx8mp.dtsi
@@ -132,7 +132,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x41 + MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-navqp.dts b/src/arm64/freescale/imx8mp-navqp.dts index 4a4f7c1..9dedb9f 100644 --- a/src/arm64/freescale/imx8mp-navqp.dts +++ b/src/arm64/freescale/imx8mp-navqp.dts
@@ -356,7 +356,7 @@ pinctrl_pmic: pmicgrp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-nitrogen-som.dtsi b/src/arm64/freescale/imx8mp-nitrogen-som.dtsi index f658309..8465b36 100644 --- a/src/arm64/freescale/imx8mp-nitrogen-som.dtsi +++ b/src/arm64/freescale/imx8mp-nitrogen-som.dtsi
@@ -296,7 +296,7 @@ pinctrl_pmic: pmicirqgrp { fsl,pins = < - MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x41 + MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-sr-som.dtsi b/src/arm64/freescale/imx8mp-sr-som.dtsi index 3cdb0bc..c3f7daa 100644 --- a/src/arm64/freescale/imx8mp-sr-som.dtsi +++ b/src/arm64/freescale/imx8mp-sr-som.dtsi
@@ -174,7 +174,7 @@ pinctrl-0 = <&pmic_pins>; pinctrl-names = "default"; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; nxp,i2c-lt-enable; regulators { @@ -417,7 +417,7 @@ pmic_pins: pinctrl-pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 >; };
diff --git a/src/arm64/freescale/imx8mp-ultra-mach-sbc.dts b/src/arm64/freescale/imx8mp-ultra-mach-sbc.dts index 9ecec1a4..3e6f9c8 100644 --- a/src/arm64/freescale/imx8mp-ultra-mach-sbc.dts +++ b/src/arm64/freescale/imx8mp-ultra-mach-sbc.dts
@@ -275,7 +275,7 @@ reg = <0x25>; pinctrl-0 = <&pinctrl_pmic>; interrupt-parent = <&gpio1>; - interrupts = <3 GPIO_ACTIVE_LOW>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; /* * i.MX 8M Plus Data Sheet for Consumer Products @@ -739,7 +739,7 @@ pinctrl_pmic: pmic-grp { fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x40 /* #PMIC_INT */ + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x1c0 /* #PMIC_INT */ >; };
diff --git a/src/arm64/marvell/armada-3720-atlas-v5.dts b/src/arm64/marvell/armada-3720-atlas-v5.dts index 070d10a..a313d56 100644 --- a/src/arm64/marvell/armada-3720-atlas-v5.dts +++ b/src/arm64/marvell/armada-3720-atlas-v5.dts
@@ -82,7 +82,6 @@ mmc-ddr-1_8v; mmc-hs400-1_8v; sd-uhs-sdr104; - marvell,xenon-emmc; marvell,xenon-tun-count = <9>; marvell,pad-type = "fixed-1-8v"; vqmmc-supply = <&vsdc_reg>;
diff --git a/src/arm64/marvell/armada-3720-espressobin.dtsi b/src/arm64/marvell/armada-3720-espressobin.dtsi index fed2dce..37e16fb 100644 --- a/src/arm64/marvell/armada-3720-espressobin.dtsi +++ b/src/arm64/marvell/armada-3720-espressobin.dtsi
@@ -78,7 +78,6 @@ bus-width = <8>; mmc-ddr-1_8v; mmc-hs400-1_8v; - marvell,xenon-emmc; marvell,xenon-tun-count = <9>; marvell,pad-type = "fixed-1-8v";
diff --git a/src/arm64/marvell/armada-3720-uDPU.dtsi b/src/arm64/marvell/armada-3720-uDPU.dtsi index 2428208..12deacb 100644 --- a/src/arm64/marvell/armada-3720-uDPU.dtsi +++ b/src/arm64/marvell/armada-3720-uDPU.dtsi
@@ -15,6 +15,11 @@ #include "armada-372x.dtsi" / { + aliases { + ethernet0 = ð0; + ethernet1 = ð1; + }; + chosen { stdout-path = "serial0:115200n8"; }; @@ -156,7 +161,7 @@ &usb3 { status = "okay"; phys = <&usb2_utmi_otg_phy>; - phy-names = "usb2-utmi-otg-phy"; + phy-names = "usb2-phy"; }; &uart0 {
diff --git a/src/arm64/marvell/armada-37xx.dtsi b/src/arm64/marvell/armada-37xx.dtsi index 87f9367..360fc24 100644 --- a/src/arm64/marvell/armada-37xx.dtsi +++ b/src/arm64/marvell/armada-37xx.dtsi
@@ -369,11 +369,10 @@ compatible = "marvell,armada3700-xhci", "generic-xhci"; reg = <0x58000 0x4000>; - marvell,usb-misc-reg = <&usb32_syscon>; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; clocks = <&sb_periph_clk 12>; - phys = <&comphy0 0>, <&usb2_utmi_otg_phy>; - phy-names = "usb3-phy", "usb2-utmi-otg-phy"; + phys = <&usb2_utmi_otg_phy>, <&comphy0 0>; + phy-names = "usb2-phy", "usb3-phy"; status = "disabled"; }; @@ -393,10 +392,9 @@ usb2: usb@5e000 { compatible = "marvell,armada-3700-ehci"; reg = <0x5e000 0x1000>; - marvell,usb-misc-reg = <&usb2_syscon>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; phys = <&usb2_utmi_host_phy>; - phy-names = "usb2-utmi-host-phy"; + phy-names = "usb"; status = "disabled"; }; @@ -534,7 +532,6 @@ armada-3700-rwtm { compatible = "marvell,armada-3700-rwtm-firmware"; mboxes = <&rwtm 0>; - status = "okay"; }; }; };
diff --git a/src/arm64/marvell/armada-7020-comexpress.dtsi b/src/arm64/marvell/armada-7020-comexpress.dtsi index 2b5ec4a..0cfcf5f 100644 --- a/src/arm64/marvell/armada-7020-comexpress.dtsi +++ b/src/arm64/marvell/armada-7020-comexpress.dtsi
@@ -70,7 +70,7 @@ &cp0_eth1 { status = "okay"; - phy = <&phy0>; + phy-handle = <&phy0>; phy-mode = "rgmii-id"; };
diff --git a/src/arm64/marvell/armada-8020.dtsi b/src/arm64/marvell/armada-8020.dtsi deleted file mode 100644 index b6fc188..0000000 --- a/src/arm64/marvell/armada-8020.dtsi +++ /dev/null
@@ -1,20 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2016 Marvell Technology Group Ltd. - * - * Device Tree file for the Armada 8020 SoC, made of an AP806 Dual and - * two CP110. - */ - -#include "armada-ap806-dual.dtsi" -#include "armada-80x0.dtsi" - -/* The RTC requires external oscillator. But on Aramda 80x0, the RTC clock - * in CP master is not connected (by package) to the oscillator. So - * disable it. However, the RTC clock in CP slave is connected to the - * oscillator so this one is let enabled. - */ - -&cp0_rtc { - status = "disabled"; -};
diff --git a/src/arm64/marvell/cn9130-db-comexpress.dtsi b/src/arm64/marvell/cn9130-db-comexpress.dtsi deleted file mode 100644 index 028496e..0000000 --- a/src/arm64/marvell/cn9130-db-comexpress.dtsi +++ /dev/null
@@ -1,96 +0,0 @@ -// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -/* - * Copyright (C) 2023 Marvell International Ltd. - * - * Device tree for the CN9130-DB Com Express CPU module board. - */ - -#include "cn9130-db.dtsi" - -/ { - model = "Marvell Armada CN9130-DB COM EXPRESS type 7 CPU module board"; - compatible = "marvell,cn9130-cpu-module", "marvell,cn9130", - "marvell,armada-ap807-quad", "marvell,armada-ap807"; - -}; - -&ap0_reg_sd_vccq { - regulator-max-microvolt = <1800000>; - states = <1800000 0x1 1800000 0x0>; - /delete-property/ gpios; -}; - -&cp0_reg_usb3_vbus0 { - /delete-property/ gpio; -}; - -&cp0_reg_usb3_vbus1 { - /delete-property/ gpio; -}; - -&cp0_reg_sd_vcc { - status = "disabled"; -}; - -&cp0_reg_sd_vccq { - status = "disabled"; -}; - -&cp0_sdhci0 { - status = "disabled"; -}; - -&cp0_eth0 { - status = "disabled"; -}; - -&cp0_eth1 { - status = "okay"; - phy = <&phy0>; - phy-mode = "rgmii-id"; -}; - -&cp0_eth2 { - status = "disabled"; -}; - -&cp0_mdio { - status = "okay"; - pinctrl-0 = <&cp0_ge_mdio_pins>; - phy0: ethernet-phy@0 { - status = "okay"; - }; -}; - -&cp0_syscon0 { - cp0_pinctrl: pinctrl { - compatible = "marvell,cp115-standalone-pinctrl"; - - cp0_ge_mdio_pins: ge-mdio-pins { - marvell,pins = "mpp40", "mpp41"; - marvell,function = "ge"; - }; - }; -}; - -&cp0_sdhci0 { - status = "disabled"; -}; - -&cp0_spi1 { - status = "okay"; -}; - -&cp0_usb3_0 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy0>; - phy-names = "usb"; - /delete-property/ phys; -}; - -&cp0_usb3_1 { - status = "okay"; - usb-phy = <&cp0_usb3_0_phy1>; - phy-names = "usb"; - /delete-property/ phys; -};