Merge tag 'drm-msm-fixes-2023-05-17' of https://gitlab.freedesktop.org/drm/msm into drm-fixes
msm-fixes for v6.4-rc3
Display Fixes:
+ Catalog fixes:
- fix the programmable fetch lines and qos settings of msm8998
to match what is present downstream
- fix the LM pairs for msm8998 to match what is present downstream.
The current settings are not right as LMs with incompatible
connected blocks are paired
- remove unused INTF0 interrupt mask from SM6115/QCM2290 as there
is no INTF0 present on those chipsets. There is only one DSI on
index 1
- remove TE2 block from relevant chipsets because this is mainly
used for ping-pong split feature which is not supported upstream
and also for the chipsets where we are removing them in this
change, that block is not present as the tear check has been moved
to the intf block
- relocate non-MDP_TOP INTF_INTR offsets from dpu_hwio.h to
dpu_hw_interrupts.c to match where they belong
- fix the indentation for REV_7xxx interrupt masks
- fix the offset and version for dither blocks of SM8[34]50/SC8280XP
chipsets as it was incorrect
- make the ping-pong blk length 0 for appropriate chipsets as those
chipsets only have a dither ping-pong dither block but no other
functionality in the base ping-pong
- remove some duplicate register defines from INTF
+ Fix the log mask for the writeback block so that it can be enabled
correctly via debugfs
+ unregister the hdmi codec for dp during unbind otherwise it leaks
audio codec devices
+ Yaml change to fix warnings related to 'qcom,master-dsi' and
'qcom,sync-dual-dsi'
GPU Fixes:
+ fix submit error path leak
+ arm-smmu-qcom fix for regression that broke per-process page tables
+ fix no-iommu crash
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGvHEcJfp=k6qatmb_SvAeyvy3CBpaPfwLqtNthuEzA_7w@mail.gmail.com
[ upstream commit: 83ab69c9f759e365cba243568cd76f8d49dcd5b5 ]
diff --git a/Bindings/.yamllint b/Bindings/.yamllint
index 214abd3..4abe9f0 100644
--- a/Bindings/.yamllint
+++ b/Bindings/.yamllint
@@ -19,7 +19,7 @@
colons: {max-spaces-before: 0, max-spaces-after: 1}
commas: {min-spaces-after: 1, max-spaces-after: 1}
comments:
- require-starting-space: false
+ require-starting-space: true
min-spaces-from-content: 1
comments-indentation: disable
document-start:
diff --git a/Bindings/arm/amlogic.yaml b/Bindings/arm/amlogic.yaml
index b634d5b..274ee08 100644
--- a/Bindings/arm/amlogic.yaml
+++ b/Bindings/arm/amlogic.yaml
@@ -153,17 +153,27 @@
- description: Boards with the Amlogic Meson G12B A311D SoC
items:
- enum:
+ - bananapi,bpi-m2s
- khadas,vim3
- radxa,zero2
- const: amlogic,a311d
- const: amlogic,g12b
+ - description: Boards using the BPI-CM4 module with Amlogic Meson G12B A311D SoC
+ items:
+ - enum:
+ - bananapi,bpi-cm4io
+ - const: bananapi,bpi-cm4
+ - const: amlogic,a311d
+ - const: amlogic,g12b
+
- description: Boards with the Amlogic Meson G12B S922X SoC
items:
- enum:
- azw,gsking-x
- azw,gtking
- azw,gtking-pro
+ - bananapi,bpi-m2s
- hardkernel,odroid-go-ultra
- hardkernel,odroid-n2
- hardkernel,odroid-n2l
diff --git a/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml b/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
index 1748f16..7dff32f 100644
--- a/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
+++ b/Bindings/arm/amlogic/amlogic,meson-gx-ao-secure.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-gx-ao-secure.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Firmware registers Interface
diff --git a/Bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml b/Bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
index eee7cda..09b27e9 100644
--- a/Bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
+++ b/Bindings/arm/amlogic/amlogic,meson-mx-secbus2.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/amlogic/amlogic,meson-mx-secbus2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson8/Meson8b/Meson8m2 SECBUS2 register interface
diff --git a/Bindings/arm/apple.yaml b/Bindings/arm/apple.yaml
index da78c69..883fd67 100644
--- a/Bindings/arm/apple.yaml
+++ b/Bindings/arm/apple.yaml
@@ -19,6 +19,12 @@
- MacBook Air (M1, 2020)
- iMac (24-inch, M1, 2021)
+ Devices based on the "M2" SoC:
+
+ - MacBook Air (M2, 2022)
+ - MacBook Pro (13-inch, M2, 2022)
+ - Mac mini (M2, 2023)
+
And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs:
- MacBook Pro (14-inch, M1 Pro, 2021)
@@ -70,6 +76,15 @@
- const: apple,t8103
- const: apple,arm-platform
+ - description: Apple M2 SoC based platforms
+ items:
+ - enum:
+ - apple,j413 # MacBook Air (M2, 2022)
+ - apple,j473 # Mac mini (M2, 2023)
+ - apple,j493 # MacBook Pro (13-inch, M2, 2022)
+ - const: apple,t8112
+ - const: apple,arm-platform
+
- description: Apple M1 Pro SoC based platforms
items:
- enum:
diff --git a/Bindings/arm/apple/apple,pmgr.yaml b/Bindings/arm/apple/apple,pmgr.yaml
index 0dc957a..673277a 100644
--- a/Bindings/arm/apple/apple,pmgr.yaml
+++ b/Bindings/arm/apple/apple,pmgr.yaml
@@ -23,6 +23,7 @@
items:
- enum:
- apple,t8103-pmgr
+ - apple,t8112-pmgr
- apple,t6000-pmgr
- const: apple,pmgr
- const: syscon
diff --git a/Bindings/arm/arm,vexpress-juno.yaml b/Bindings/arm/arm,vexpress-juno.yaml
index eec190a..09c319f 100644
--- a/Bindings/arm/arm,vexpress-juno.yaml
+++ b/Bindings/arm/arm,vexpress-juno.yaml
@@ -144,6 +144,7 @@
it is stricter and always has two compatibles.
type: object
$ref: '/schemas/simple-bus.yaml'
+ unevaluatedProperties: false
properties:
compatible:
diff --git a/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml b/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
index b369b37..39e3c24 100644
--- a/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
+++ b/Bindings/arm/bcm/raspberrypi,bcm2835-firmware.yaml
@@ -30,6 +30,7 @@
clocks:
type: object
+ additionalProperties: false
properties:
compatible:
@@ -47,6 +48,7 @@
reset:
type: object
+ additionalProperties: false
properties:
compatible:
@@ -63,6 +65,7 @@
pwm:
type: object
+ additionalProperties: false
properties:
compatible:
@@ -76,8 +79,6 @@
- compatible
- "#pwm-cells"
- additionalProperties: false
-
required:
- compatible
- mboxes
diff --git a/Bindings/arm/cpus.yaml b/Bindings/arm/cpus.yaml
index c145f6a..ff272e5 100644
--- a/Bindings/arm/cpus.yaml
+++ b/Bindings/arm/cpus.yaml
@@ -85,6 +85,8 @@
compatible:
enum:
+ - apple,avalanche
+ - apple,blizzard
- apple,icestorm
- apple,firestorm
- arm,arm710t
@@ -139,6 +141,7 @@
- arm,cortex-a77
- arm,cortex-a78
- arm,cortex-a78ae
+ - arm,cortex-a78c
- arm,cortex-a510
- arm,cortex-a710
- arm,cortex-a715
@@ -151,6 +154,7 @@
- arm,cortex-r5
- arm,cortex-r7
- arm,cortex-x1
+ - arm,cortex-x1c
- arm,cortex-x2
- arm,cortex-x3
- arm,neoverse-e1
diff --git a/Bindings/arm/firmware/linaro,optee-tz.yaml b/Bindings/arm/firmware/linaro,optee-tz.yaml
index d4dc074..5d03357 100644
--- a/Bindings/arm/firmware/linaro,optee-tz.yaml
+++ b/Bindings/arm/firmware/linaro,optee-tz.yaml
@@ -28,7 +28,8 @@
maxItems: 1
description: |
This interrupt which is used to signal an event by the secure world
- software is expected to be edge-triggered.
+ software is expected to be either a per-cpu interrupt or an
+ edge-triggered peripheral interrupt.
method:
enum: [smc, hvc]
diff --git a/Bindings/arm/fsl.yaml b/Bindings/arm/fsl.yaml
index 442ce8f..15d4110 100644
--- a/Bindings/arm/fsl.yaml
+++ b/Bindings/arm/fsl.yaml
@@ -300,6 +300,7 @@
- variscite,dt6customboard
- wand,imx6q-wandboard # Wandboard i.MX6 Quad Board
- ysoft,imx6q-yapp4-crux # i.MX6 Quad Y Soft IOTA Crux board
+ - ysoft,imx6q-yapp4-pegasus # i.MX6 Quad Y Soft IOTA Pegasus board
- zealz,imx6q-gk802 # Zealz GK802
- zii,imx6q-zii-rdu2 # ZII RDU2 Board
- const: fsl,imx6q
@@ -410,6 +411,7 @@
- prt,prtwd3 # Protonic WD3 board
- wand,imx6qp-wandboard # Wandboard i.MX6 QuadPlus Board
- ysoft,imx6qp-yapp4-crux-plus # i.MX6 Quad Plus Y Soft IOTA Crux+ board
+ - ysoft,imx6qp-yapp4-pegasus-plus # i.MX6 Quad Plus Y Soft IOTA Pegasus+ board
- zii,imx6qp-zii-rdu2 # ZII RDU2+ Board
- const: fsl,imx6qp
@@ -474,9 +476,11 @@
- udoo,imx6dl-udoo # Udoo i.MX6 Dual-lite Board
- vdl,lanmcu # Van der Laan LANMCU board
- wand,imx6dl-wandboard # Wandboard i.MX6 Dual Lite Board
- - ysoft,imx6dl-yapp4-draco # i.MX6 DualLite Y Soft IOTA Draco board
+ - ysoft,imx6dl-yapp4-draco # i.MX6 Solo Y Soft IOTA Draco board
- ysoft,imx6dl-yapp4-hydra # i.MX6 DualLite Y Soft IOTA Hydra board
+ - ysoft,imx6dl-yapp4-lynx # i.MX6 DualLite Y Soft IOTA Lynx board
- ysoft,imx6dl-yapp4-orion # i.MX6 DualLite Y Soft IOTA Orion board
+ - ysoft,imx6dl-yapp4-phoenix # i.MX6 DualLite Y Soft IOTA Phoenix board
- ysoft,imx6dl-yapp4-ursa # i.MX6 Solo Y Soft IOTA Ursa board
- const: fsl,imx6dl
@@ -581,6 +585,7 @@
- kobo,aura2
- kobo,tolino-shine2hd
- kobo,tolino-shine3
+ - kobo,tolino-vision
- kobo,tolino-vision5
- revotics,imx6sl-warp # Revotics WaRP Board
- const: fsl,imx6sl
@@ -702,6 +707,15 @@
- const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM
- const: fsl,imx6ull
+ - description: i.MX6ULL chargebyte Tarragon Boards
+ items:
+ - enum:
+ - chargebyte,imx6ull-tarragon-master
+ - chargebyte,imx6ull-tarragon-micro
+ - chargebyte,imx6ull-tarragon-slave
+ - chargebyte,imx6ull-tarragon-slavext
+ - const: fsl,imx6ull
+
- description: i.MX6ULL DHCOM SoM based Boards
items:
- enum:
@@ -1002,6 +1016,7 @@
items:
- enum:
- beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit
+ - dmo,imx8mp-data-modul-edm-sbc # i.MX8MP eDM SBC
- fsl,imx8mp-evk # i.MX8MP EVK Board
- gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board
- polyhex,imx8mp-debix # Polyhex Debix boards
@@ -1020,7 +1035,9 @@
- description: i.MX8MP DHCOM based Boards
items:
- - const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
+ - enum:
+ - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board
+ - dh,imx8mp-dhcom-pdk3 # i.MX8MP DHCOM SoM on PDK3 board
- const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM
- const: fsl,imx8mp
@@ -1119,6 +1136,25 @@
items:
- enum:
- fsl,imx8qm-mek # i.MX8QM MEK Board
+ - toradex,apalis-imx8 # Apalis iMX8 Modules
+ - toradex,apalis-imx8-v1.1 # Apalis iMX8 V1.1 Modules
+ - const: fsl,imx8qm
+
+ - description: i.MX8QM Boards with Toradex Apalis iMX8 Modules
+ items:
+ - enum:
+ - toradex,apalis-imx8-eval # Apalis iMX8 Module on Apalis Evaluation Board
+ - toradex,apalis-imx8-ixora-v1.1 # Apalis iMX8 Module on Ixora V1.1 Carrier Board
+ - const: toradex,apalis-imx8
+ - const: fsl,imx8qm
+
+ - description: i.MX8QM Boards with Toradex Apalis iMX8 V1.1 Modules
+ items:
+ - enum:
+ - toradex,apalis-imx8-v1.1-eval # Apalis iMX8 V1.1 Module on Apalis Eval. Board
+ - toradex,apalis-imx8-v1.1-ixora-v1.1 # Apalis iMX8 V1.1 Module on Ixora V1.1 C. Board
+ - toradex,apalis-imx8-v1.1-ixora-v1.2 # Apalis iMX8 V1.1 Module on Ixora V1.2 C. Board
+ - const: toradex,apalis-imx8-v1.1
- const: fsl,imx8qm
- description: i.MX8QXP based Boards
@@ -1135,10 +1171,13 @@
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
- - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
+ - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules
items:
- enum:
+ - toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
+ - toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board
+ - toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
diff --git a/Bindings/arm/mediatek/mediatek,infracfg.yaml b/Bindings/arm/mediatek/mediatek,infracfg.yaml
index e997635..ea98043 100644
--- a/Bindings/arm/mediatek/mediatek,infracfg.yaml
+++ b/Bindings/arm/mediatek/mediatek,infracfg.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,infracfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Infrastructure System Configuration Controller
diff --git a/Bindings/arm/mediatek/mediatek,mmsys.yaml b/Bindings/arm/mediatek/mediatek,mmsys.yaml
index d141034..536f5a5 100644
--- a/Bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mmsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek mmsys controller
diff --git a/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml b/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
index 9fbeb62..d89848a 100644
--- a/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-pcie-mirror.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE Mirror Controller for MT7622
diff --git a/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml b/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
index 5c223cb..28ded09 100644
--- a/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt7622-wed.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7622-wed.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Wireless Ethernet Dispatch Controller for MT7622
@@ -20,6 +20,7 @@
items:
- enum:
- mediatek,mt7622-wed
+ - mediatek,mt7981-wed
- mediatek,mt7986-wed
- const: syscon
diff --git a/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml b/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
index 96221f5..82f6446 100644
--- a/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt7986-wed-pcie.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt7986-wed-pcie.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek PCIE WED Controller for MT7986
diff --git a/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
index cf1002c..7cd14b1 100644
--- a/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8186-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8186
diff --git a/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
index 661047d..64c7694 100644
--- a/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8186-sys-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8186-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8186
diff --git a/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml
index b57cc2e..dff4c8e 100644
--- a/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8192-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8192
diff --git a/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
index 27f7917..8d608fd 100644
--- a/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8192-sys-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8192-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8192
diff --git a/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml
index d62d601..d17164b 100644
--- a/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8195-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Functional Clock Controller for MT8195
diff --git a/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml b/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
index 95b6bdf..066c9b3 100644
--- a/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
+++ b/Bindings/arm/mediatek/mediatek,mt8195-sys-clock.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,mt8195-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek System Clock Controller for MT8195
diff --git a/Bindings/arm/mediatek/mediatek,pericfg.yaml b/Bindings/arm/mediatek/mediatek,pericfg.yaml
index ef62cbb..26158d0 100644
--- a/Bindings/arm/mediatek/mediatek,pericfg.yaml
+++ b/Bindings/arm/mediatek/mediatek,pericfg.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/mediatek/mediatek,pericfg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Peripheral Configuration Controller
diff --git a/Bindings/arm/mediatek/mediatek,sgmiisys.txt b/Bindings/arm/mediatek/mediatek,sgmiisys.txt
deleted file mode 100644
index d2c24c2..0000000
--- a/Bindings/arm/mediatek/mediatek,sgmiisys.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-MediaTek SGMIISYS controller
-============================
-
-The MediaTek SGMIISYS controller provides various clocks to the system.
-
-Required Properties:
-
-- compatible: Should be:
- - "mediatek,mt7622-sgmiisys", "syscon"
- - "mediatek,mt7629-sgmiisys", "syscon"
- - "mediatek,mt7981-sgmiisys_0", "syscon"
- - "mediatek,mt7981-sgmiisys_1", "syscon"
- - "mediatek,mt7986-sgmiisys_0", "syscon"
- - "mediatek,mt7986-sgmiisys_1", "syscon"
-- #clock-cells: Must be 1
-
-The SGMIISYS controller uses the common clk binding from
-Documentation/devicetree/bindings/clock/clock-bindings.txt
-The available clocks are defined in dt-bindings/clock/mt*-clk.h.
-
-Example:
-
-sgmiisys: sgmiisys@1b128000 {
- compatible = "mediatek,mt7622-sgmiisys", "syscon";
- reg = <0 0x1b128000 0 0x1000>;
- #clock-cells = <1>;
-};
diff --git a/Bindings/arm/msm/qcom,kpss-acc.txt b/Bindings/arm/msm/qcom,kpss-acc.txt
deleted file mode 100644
index 7f69636..0000000
--- a/Bindings/arm/msm/qcom,kpss-acc.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-Krait Processor Sub-system (KPSS) Application Clock Controller (ACC)
-
-The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
-There is one ACC register region per CPU within the KPSS remapped region as
-well as an alias register region that remaps accesses to the ACC associated
-with the CPU accessing the region.
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: should be one of:
- "qcom,kpss-acc-v1"
- "qcom,kpss-acc-v2"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: the first element specifies the base address and size of
- the register region. An optional second element specifies
- the base address and size of the alias register region.
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the pll parents.
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "pll8_vote", "pxo".
-
-- clock-output-names:
- Usage: optional
- Value type: <string>
- Definition: Name of the output clock. Typically acpuX_aux where X is a
- CPU number starting at 0.
-
-Example:
-
- clock-controller@2088000 {
- compatible = "qcom,kpss-acc-v2";
- reg = <0x02088000 0x1000>,
- <0x02008000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu0_aux";
- };
diff --git a/Bindings/arm/msm/qcom,kpss-gcc.txt b/Bindings/arm/msm/qcom,kpss-gcc.txt
deleted file mode 100644
index e628758..0000000
--- a/Bindings/arm/msm/qcom,kpss-gcc.txt
+++ /dev/null
@@ -1,44 +0,0 @@
-Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
-
-PROPERTIES
-
-- compatible:
- Usage: required
- Value type: <string>
- Definition: should be one of the following. The generic compatible
- "qcom,kpss-gcc" should also be included.
- "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc"
- "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc"
- "qcom,kpss-gcc-msm8974", "qcom,kpss-gcc"
- "qcom,kpss-gcc-msm8960", "qcom,kpss-gcc"
-
-- reg:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: base address and size of the register region
-
-- clocks:
- Usage: required
- Value type: <prop-encoded-array>
- Definition: reference to the pll parents.
-
-- clock-names:
- Usage: required
- Value type: <stringlist>
- Definition: must be "pll8_vote", "pxo".
-
-- clock-output-names:
- Usage: required
- Value type: <string>
- Definition: Name of the output clock. Typically acpu_l2_aux indicating
- an L2 cache auxiliary clock.
-
-Example:
-
- l2cc: clock-controller@2011000 {
- compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc";
- reg = <0x2011000 0x1000>;
- clocks = <&gcc PLL8_VOTE>, <&gcc PXO_SRC>;
- clock-names = "pll8_vote", "pxo";
- clock-output-names = "acpu_l2_aux";
- };
diff --git a/Bindings/arm/msm/qcom,llcc.yaml b/Bindings/arm/msm/qcom,llcc.yaml
deleted file mode 100644
index 38efcad..0000000
--- a/Bindings/arm/msm/qcom,llcc.yaml
+++ /dev/null
@@ -1,65 +0,0 @@
-# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Last Level Cache Controller
-
-maintainers:
- - Rishabh Bhatnagar <rishabhb@codeaurora.org>
- - Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
-
-description: |
- LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
- that can be shared by multiple clients. Clients here are different cores in the
- SoC, the idea is to minimize the local caches at the clients and migrate to
- common pool of memory. Cache memory is divided into partitions called slices
- which are assigned to clients. Clients can query the slice details, activate
- and deactivate them.
-
-properties:
- compatible:
- enum:
- - qcom,sc7180-llcc
- - qcom,sc7280-llcc
- - qcom,sc8180x-llcc
- - qcom,sc8280xp-llcc
- - qcom,sdm845-llcc
- - qcom,sm6350-llcc
- - qcom,sm8150-llcc
- - qcom,sm8250-llcc
- - qcom,sm8350-llcc
- - qcom,sm8450-llcc
- - qcom,sm8550-llcc
-
- reg:
- items:
- - description: LLCC base register region
- - description: LLCC broadcast base register region
-
- reg-names:
- items:
- - const: llcc_base
- - const: llcc_broadcast_base
-
- interrupts:
- maxItems: 1
-
-required:
- - compatible
- - reg
- - reg-names
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-
- system-cache-controller@1100000 {
- compatible = "qcom,sdm845-llcc";
- reg = <0x1100000 0x200000>, <0x1300000 0x50000> ;
- reg-names = "llcc_base", "llcc_broadcast_base";
- interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
- };
diff --git a/Bindings/arm/nvidia,tegra194-ccplex.yaml b/Bindings/arm/nvidia,tegra194-ccplex.yaml
index b6f57d7..84dc6b7 100644
--- a/Bindings/arm/nvidia,tegra194-ccplex.yaml
+++ b/Bindings/arm/nvidia,tegra194-ccplex.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/nvidia,tegra194-ccplex.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra194 CPU Complex
@@ -25,7 +25,7 @@
- nvidia,tegra194-ccplex
nvidia,bpmp:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the bpmp node that needs to be queried to get
operating point data for all CPUs.
diff --git a/Bindings/arm/oxnas.txt b/Bindings/arm/oxnas.txt
deleted file mode 100644
index ac64e60..0000000
--- a/Bindings/arm/oxnas.txt
+++ /dev/null
@@ -1,14 +0,0 @@
-Oxford Semiconductor OXNAS SoCs Family device tree bindings
--------------------------------------------
-
-Boards with the OX810SE SoC shall have the following properties:
- Required root node property:
- compatible: "oxsemi,ox810se"
-
-Boards with the OX820 SoC shall have the following properties:
- Required root node property:
- compatible: "oxsemi,ox820"
-
-Board compatible values:
- - "wd,mbwe" (OX810SE)
- - "cloudengines,pogoplugv3" (OX820)
diff --git a/Bindings/arm/pmu.yaml b/Bindings/arm/pmu.yaml
index dbb6f3d..e14358b 100644
--- a/Bindings/arm/pmu.yaml
+++ b/Bindings/arm/pmu.yaml
@@ -20,6 +20,8 @@
items:
- enum:
- apm,potenza-pmu
+ - apple,avalanche-pmu
+ - apple,blizzard-pmu
- apple,firestorm-pmu
- apple,icestorm-pmu
- arm,armv8-pmuv3 # Only for s/w models
diff --git a/Bindings/arm/qcom.yaml b/Bindings/arm/qcom.yaml
index 1bb24d4..d9dd256 100644
--- a/Bindings/arm/qcom.yaml
+++ b/Bindings/arm/qcom.yaml
@@ -30,8 +30,10 @@
apq8084
apq8096
ipq4018
+ ipq5332
ipq6018
ipq8074
+ ipq9574
mdm9615
msm8226
msm8916
@@ -45,7 +47,10 @@
msm8996
msm8998
qcs404
+ qcm2290
qdu1000
+ qrb2210
+ qrb4210
qru1000
sa8155p
sa8540p
@@ -80,6 +85,9 @@
The 'board' element must be one of the following strings:
adp
+ ap-al02-c7
+ ap-mi01.2
+ ap-mi01.6
cdp
cp01-c1
dragonboard
@@ -90,6 +98,7 @@
liquid
mtp
qrd
+ rb2
ride
sbc
x100
@@ -226,6 +235,7 @@
- thwc,uf896
- thwc,ufi001c
- wingtech,wt88047
+ - yiming,uz801-v3
- const: qcom,msm8916
- items:
@@ -322,6 +332,12 @@
- items:
- enum:
+ - qcom,ipq5332-ap-mi01.2
+ - qcom,ipq5332-ap-mi01.6
+ - const: qcom,ipq5332
+
+ - items:
+ - enum:
- mikrotik,rb3011
- qcom,ipq8064-ap148
- const: qcom,ipq8064
@@ -333,12 +349,24 @@
- qcom,ipq8074-hk10-c2
- const: qcom,ipq8074
+ - items:
+ - enum:
+ - qcom,ipq9574-ap-al02-c7
+ - const: qcom,ipq9574
+
- description: Sierra Wireless MangOH Green with WP8548 Module
items:
- const: swir,mangoh-green-wp8548
- const: swir,wp8548
- const: qcom,mdm9615
+ - description: Qualcomm Technologies, Inc. Robotics RB1
+ items:
+ - enum:
+ - qcom,qrb2210-rb1
+ - const: qcom,qrb2210
+ - const: qcom,qcm2290
+
- description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform
items:
- enum:
@@ -850,6 +878,12 @@
- items:
- enum:
+ - qcom,qrb4210-rb2
+ - const: qcom,qrb4210
+ - const: qcom,sm4250
+
+ - items:
+ - enum:
- lenovo,j606f
- const: qcom,sm6115p
- const: qcom,sm6115
@@ -857,6 +891,7 @@
- items:
- enum:
- sony,pdx201
+ - xiaomi,laurel-sprout
- const: qcom,sm6125
- items:
@@ -913,6 +948,7 @@
- items:
- enum:
- qcom,sm8550-mtp
+ - qcom,sm8550-qrd
- const: qcom,sm8550
# Board compatibles go above
diff --git a/Bindings/arm/rockchip.yaml b/Bindings/arm/rockchip.yaml
index 35f74ed..ec141c9 100644
--- a/Bindings/arm/rockchip.yaml
+++ b/Bindings/arm/rockchip.yaml
@@ -185,9 +185,11 @@
- const: firefly,rk3566-roc-pc
- const: rockchip,rk3566
- - description: FriendlyElec NanoPi R2S
+ - description: FriendlyElec NanoPi R2 series boards
items:
- - const: friendlyarm,nanopi-r2s
+ - enum:
+ - friendlyarm,nanopi-r2c
+ - friendlyarm,nanopi-r2s
- const: rockchip,rk3328
- description: FriendlyElec NanoPi4 series boards
@@ -201,6 +203,13 @@
- friendlyarm,nanopi-r4s-enterprise
- const: rockchip,rk3399
+ - description: FriendlyElec NanoPi R5 series boards
+ items:
+ - enum:
+ - friendlyarm,nanopi-r5c
+ - friendlyarm,nanopi-r5s
+ - const: rockchip,rk3568
+
- description: GeekBuying GeekBox
items:
- const: geekbuying,geekbox
@@ -533,6 +542,11 @@
- khadas,edge-v
- const: rockchip,rk3399
+ - description: Khadas Edge2 series boards
+ items:
+ - const: khadas,edge2
+ - const: rockchip,rk3588s
+
- description: Kobol Helios64
items:
- const: kobol,helios64
@@ -817,9 +831,11 @@
- const: tronsmart,orion-r68-meta
- const: rockchip,rk3368
- - description: Xunlong Orange Pi R1 Plus
+ - description: Xunlong Orange Pi R1 Plus / LTS
items:
- - const: xunlong,orangepi-r1-plus
+ - enum:
+ - xunlong,orangepi-r1-plus
+ - xunlong,orangepi-r1-plus-lts
- const: rockchip,rk3328
- description: Zkmagic A95X Z2
diff --git a/Bindings/arm/stm32/st,stm32-syscon.yaml b/Bindings/arm/stm32/st,stm32-syscon.yaml
index b2b156c..ad8e51a 100644
--- a/Bindings/arm/stm32/st,stm32-syscon.yaml
+++ b/Bindings/arm/stm32/st,stm32-syscon.yaml
@@ -20,6 +20,7 @@
- st,stm32-syscfg
- st,stm32-power-config
- st,stm32-tamp
+ - st,stm32f4-gcan
- const: syscon
- items:
- const: st,stm32-tamp
@@ -42,6 +43,7 @@
contains:
enum:
- st,stm32mp157-syscfg
+ - st,stm32f4-gcan
then:
required:
- clocks
diff --git a/Bindings/arm/sunxi.yaml b/Bindings/arm/sunxi.yaml
index 3ad1cd5..013821f 100644
--- a/Bindings/arm/sunxi.yaml
+++ b/Bindings/arm/sunxi.yaml
@@ -366,6 +366,12 @@
- const: lamobo,lamobo-r1
- const: allwinner,sun7i-a20
+ - description: Lctech Pi F1C200s
+ items:
+ - const: lctech,pi-f1c200s
+ - const: allwinner,suniv-f1c200s
+ - const: allwinner,suniv-f1c100s
+
- description: Libre Computer Board ALL-H3-CC H2+
items:
- const: libretech,all-h3-cc-h2-plus
@@ -807,6 +813,13 @@
- const: sinlinx,sina33
- const: allwinner,sun8i-a33
+ - description: SourceParts PopStick v1.1
+ items:
+ - const: sourceparts,popstick-v1.1
+ - const: sourceparts,popstick
+ - const: allwinner,suniv-f1c200s
+ - const: allwinner,suniv-f1c100s
+
- description: SL631 Action Camera with IMX179
items:
- const: allwinner,sl631-imx179
@@ -843,6 +856,11 @@
- const: wexler,tab7200
- const: allwinner,sun7i-a20
+ - description: MangoPi MQ-R board
+ items:
+ - const: widora,mangopi-mq-r-t113
+ - const: allwinner,sun8i-t113s
+
- description: WITS A31 Colombus Evaluation Board
items:
- const: wits,colombus
diff --git a/Bindings/arm/tegra.yaml b/Bindings/arm/tegra.yaml
index 1f62253..0df41f5 100644
--- a/Bindings/arm/tegra.yaml
+++ b/Bindings/arm/tegra.yaml
@@ -167,5 +167,14 @@
- const: nvidia,p3737-0000+p3701-0000
- const: nvidia,p3701-0000
- const: nvidia,tegra234
+ - description: Jetson Orin NX
+ items:
+ - const: nvidia,p3767-0000
+ - const: nvidia,tegra234
+ - description: Jetson Orin NX Engineering Reference Developer Kit
+ items:
+ - const: nvidia,p3768-0000+p3767-0000
+ - const: nvidia,p3767-0000
+ - const: nvidia,tegra234
additionalProperties: true
diff --git a/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml b/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
index 6089a96..36dbd08 100644
--- a/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra-ccplex-cluster.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra-ccplex-cluster.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra CPU COMPLEX CLUSTER area
@@ -29,7 +29,7 @@
maxItems: 1
nvidia,bpmp:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description: |
Specifies the BPMP node that needs to be queried to get
operating point data for all CPUs.
diff --git a/Bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml b/Bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
index 788a13f..5e0f1dc 100644
--- a/Bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra194-axi2apb.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-axi2apb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra194 AXI2APB bridge
diff --git a/Bindings/arm/tegra/nvidia,tegra194-cbb.yaml b/Bindings/arm/tegra/nvidia,tegra194-cbb.yaml
index dd3a477..d9c54c3 100644
--- a/Bindings/arm/tegra/nvidia,tegra194-cbb.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra194-cbb.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra194-cbb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra194 CBB 1.0
@@ -64,13 +64,13 @@
- description: secure interrupt
nvidia,axi2apb:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies the node having all axi2apb bridges which need to be checked
for any error logged in their status register.
nvidia,apbmisc:
- $ref: '/schemas/types.yaml#/definitions/phandle'
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
Specifies the apbmisc node which need to be used for reading the ERD
register.
diff --git a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
index 4a00593..89191cf 100644
--- a/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra20-pmc.yaml
@@ -234,6 +234,7 @@
patternProperties:
"^[a-z0-9]+$":
type: object
+ additionalProperties: false
properties:
clocks:
@@ -252,6 +253,9 @@
for controlling a power-gate.
See ../reset/reset.txt for more details.
+ power-domains:
+ maxItems: 1
+
'#power-domain-cells':
const: 0
description: Must be 0.
diff --git a/Bindings/arm/tegra/nvidia,tegra234-cbb.yaml b/Bindings/arm/tegra/nvidia,tegra234-cbb.yaml
index 44184ee..fcdf031 100644
--- a/Bindings/arm/tegra/nvidia,tegra234-cbb.yaml
+++ b/Bindings/arm/tegra/nvidia,tegra234-cbb.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/arm/tegra/nvidia,tegra234-cbb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra CBB 2.0
diff --git a/Bindings/arm/ti/k3.yaml b/Bindings/arm/ti/k3.yaml
index a60a406..e1183f9 100644
--- a/Bindings/arm/ti/k3.yaml
+++ b/Bindings/arm/ti/k3.yaml
@@ -28,7 +28,9 @@
- description: K3 AM625 SoC
items:
- enum:
+ - beagle,am625-beagleplay
- ti,am625-sk
+ - ti,am62-lp-sk
- const: ti,am625
- description: K3 AM642 SoC
diff --git a/Bindings/ata/ahci-common.yaml b/Bindings/ata/ahci-common.yaml
index 94d72ae..7fdf409 100644
--- a/Bindings/ata/ahci-common.yaml
+++ b/Bindings/ata/ahci-common.yaml
@@ -59,7 +59,7 @@
const: sata-phy
hba-cap:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA generic platform capabilities like Staggered
Spin-up or Mechanical Presence Switch support. It can be used to
@@ -67,7 +67,7 @@
in case if the system firmware hasn't done it.
ports-implemented:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Mask that indicates which ports the HBA supports. Useful if PI is not
programmed by the BIOS, which is true for some embedded SoC's.
@@ -110,7 +110,7 @@
description: Power regulator for SATA port target device
hba-port-cap:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Bitfield of the HBA port-specific platform capabilities like Hot
plugging, eSATA, FIS-based Switching, etc (see AHCI specification
diff --git a/Bindings/ata/ahci-platform.yaml b/Bindings/ata/ahci-platform.yaml
index 7dc2a2e..3586171 100644
--- a/Bindings/ata/ahci-platform.yaml
+++ b/Bindings/ata/ahci-platform.yaml
@@ -30,12 +30,12 @@
- marvell,armada-3700-ahci
- marvell,armada-8k-ahci
- marvell,berlin2q-ahci
+ - socionext,uniphier-pro4-ahci
+ - socionext,uniphier-pxs2-ahci
+ - socionext,uniphier-pxs3-ahci
required:
- compatible
-allOf:
- - $ref: "ahci-common.yaml#"
-
properties:
compatible:
oneOf:
@@ -45,6 +45,9 @@
- marvell,armada-8k-ahci
- marvell,berlin2-ahci
- marvell,berlin2q-ahci
+ - socionext,uniphier-pro4-ahci
+ - socionext,uniphier-pxs2-ahci
+ - socionext,uniphier-pxs3-ahci
- const: generic-ahci
- enum:
- cavium,octeon-7130-ahci
@@ -74,7 +77,8 @@
maxItems: 1
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 3
patternProperties:
"^sata-port@[0-9a-f]+$":
@@ -91,6 +95,43 @@
- reg
- interrupts
+allOf:
+ - $ref: ahci-common.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: socionext,uniphier-pro4-ahci
+ then:
+ properties:
+ resets:
+ items:
+ - description: reset line for the parent
+ - description: reset line for the glue logic
+ - description: reset line for the controller
+ required:
+ - resets
+ else:
+ if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - socionext,uniphier-pxs2-ahci
+ - socionext,uniphier-pxs3-ahci
+ then:
+ properties:
+ resets:
+ items:
+ - description: reset for the glue logic
+ - description: reset for the controller
+ required:
+ - resets
+ else:
+ properties:
+ resets:
+ maxItems: 1
+
unevaluatedProperties: false
examples:
diff --git a/Bindings/ata/renesas,rcar-sata.yaml b/Bindings/ata/renesas,rcar-sata.yaml
index c4e4a9e..fe09095 100644
--- a/Bindings/ata/renesas,rcar-sata.yaml
+++ b/Bindings/ata/renesas,rcar-sata.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/ata/renesas,rcar-sata.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car Serial-ATA Interface
diff --git a/Bindings/auxdisplay/holtek,ht16k33.yaml b/Bindings/auxdisplay/holtek,ht16k33.yaml
index fc4873d..49304a1 100644
--- a/Bindings/auxdisplay/holtek,ht16k33.yaml
+++ b/Bindings/auxdisplay/holtek,ht16k33.yaml
@@ -10,7 +10,7 @@
- Robin van der Gracht <robin@protonic.nl>
allOf:
- - $ref: "/schemas/input/matrix-keymap.yaml#"
+ - $ref: /schemas/input/matrix-keymap.yaml#
properties:
compatible:
@@ -72,7 +72,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/leds/common.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/bus/allwinner,sun50i-a64-de2.yaml b/Bindings/bus/allwinner,sun50i-a64-de2.yaml
index 85c4a97..9845a18 100644
--- a/Bindings/bus/allwinner,sun50i-a64-de2.yaml
+++ b/Bindings/bus/allwinner,sun50i-a64-de2.yaml
@@ -46,6 +46,7 @@
# All other properties should be child nodes with unit-address and 'reg'
"^[a-zA-Z][a-zA-Z0-9,+\\-._]{0,63}@[0-9a-fA-F]+$":
type: object
+ additionalProperties: true
properties:
reg:
maxItems: 1
diff --git a/Bindings/bus/allwinner,sun8i-a23-rsb.yaml b/Bindings/bus/allwinner,sun8i-a23-rsb.yaml
index bee5f53..24c939f 100644
--- a/Bindings/bus/allwinner,sun8i-a23-rsb.yaml
+++ b/Bindings/bus/allwinner,sun8i-a23-rsb.yaml
@@ -45,6 +45,7 @@
patternProperties:
"^.*@[0-9a-fA-F]+$":
type: object
+ additionalProperties: true
properties:
reg:
maxItems: 1
diff --git a/Bindings/bus/microsoft,vmbus.yaml b/Bindings/bus/microsoft,vmbus.yaml
new file mode 100644
index 0000000..a8d40c7
--- /dev/null
+++ b/Bindings/bus/microsoft,vmbus.yaml
@@ -0,0 +1,54 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/microsoft,vmbus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microsoft Hyper-V VMBus
+
+maintainers:
+ - Saurabh Sengar <ssengar@linux.microsoft.com>
+
+description:
+ VMBus is a software bus that implement the protocols for communication
+ between the root or host OS and guest OSs (virtual machines).
+
+properties:
+ compatible:
+ const: microsoft,vmbus
+
+ ranges: true
+
+ '#address-cells':
+ const: 2
+
+ '#size-cells':
+ const: 1
+
+required:
+ - compatible
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ soc {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges;
+
+ vmbus@ff0000000 {
+ compatible = "microsoft,vmbus";
+ #address-cells = <2>;
+ #size-cells = <1>;
+ ranges = <0x0f 0xf0000000 0x0f 0xf0000000 0x10000000>;
+ };
+ };
+ };
diff --git a/Bindings/bus/palmbus.yaml b/Bindings/bus/palmbus.yaml
index 30fa652..c36c1e9 100644
--- a/Bindings/bus/palmbus.yaml
+++ b/Bindings/bus/palmbus.yaml
@@ -36,6 +36,7 @@
# All other properties should be child nodes with unit-address and 'reg'
"@[0-9a-f]+$":
type: object
+ additionalProperties: true
properties:
reg:
maxItems: 1
diff --git a/Bindings/bus/xlnx,versal-net-cdx.yaml b/Bindings/bus/xlnx,versal-net-cdx.yaml
new file mode 100644
index 0000000..7f62ffb
--- /dev/null
+++ b/Bindings/bus/xlnx,versal-net-cdx.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/bus/xlnx,versal-net-cdx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: AMD CDX bus controller
+
+description: |
+ CDX bus controller for AMD devices is implemented to dynamically
+ detect CDX bus and devices using the firmware.
+ The CDX bus manages multiple FPGA based hardware devices, which
+ can support network, crypto or any other specialized type of
+ devices. These FPGA based devices can be added/modified dynamically
+ on run-time.
+
+ All devices on the CDX bus will have a unique streamid (for IOMMU)
+ and a unique device ID (for MSI) corresponding to a requestor ID
+ (one to one associated with the device). The streamid and deviceid
+ are used to configure SMMU and GIC-ITS respectively.
+
+ iommu-map property is used to define the set of stream ids
+ corresponding to each device and the associated IOMMU.
+
+ The MSI writes are accompanied by sideband data (Device ID).
+ The msi-map property is used to associate the devices with the
+ device ID as well as the associated ITS controller.
+
+ rproc property (xlnx,rproc) is used to identify the remote processor
+ with which APU (Application Processor Unit) interacts to find out
+ the bus and device configuration.
+
+maintainers:
+ - Nipun Gupta <nipun.gupta@amd.com>
+ - Nikhil Agarwal <nikhil.agarwal@amd.com>
+
+properties:
+ compatible:
+ const: xlnx,versal-net-cdx
+
+ iommu-map: true
+
+ msi-map: true
+
+ xlnx,rproc:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ phandle to the remoteproc_r5 rproc node using which APU interacts
+ with remote processor.
+
+ ranges: true
+
+ "#address-cells":
+ enum: [1, 2]
+
+ "#size-cells":
+ enum: [1, 2]
+
+required:
+ - compatible
+ - iommu-map
+ - msi-map
+ - xlnx,rproc
+ - ranges
+ - "#address-cells"
+ - "#size-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ cdx {
+ compatible = "xlnx,versal-net-cdx";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ /* define map for RIDs 250-259 */
+ iommu-map = <250 &smmu 250 10>;
+ /* define msi map for RIDs 250-259 */
+ msi-map = <250 &its 250 10>;
+ xlnx,rproc = <&remoteproc_r5>;
+ ranges;
+ };
diff --git a/Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Bindings/cache/baikal,bt1-l2-ctl.yaml
similarity index 94%
rename from Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml
rename to Bindings/cache/baikal,bt1-l2-ctl.yaml
index 1fca282..ec4f367 100644
--- a/Bindings/memory-controllers/baikal,bt1-l2-ctl.yaml
+++ b/Bindings/cache/baikal,bt1-l2-ctl.yaml
@@ -2,7 +2,7 @@
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
-$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
+$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 L2-cache Control Block
diff --git a/Bindings/powerpc/fsl/l2cache.txt b/Bindings/cache/freescale-l2cache.txt
similarity index 100%
rename from Bindings/powerpc/fsl/l2cache.txt
rename to Bindings/cache/freescale-l2cache.txt
diff --git a/Bindings/arm/l2c2x0.yaml b/Bindings/cache/l2c2x0.yaml
similarity index 98%
rename from Bindings/arm/l2c2x0.yaml
rename to Bindings/cache/l2c2x0.yaml
index 6b8f4d4..d7840a5 100644
--- a/Bindings/arm/l2c2x0.yaml
+++ b/Bindings/cache/l2c2x0.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
+$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM L2 Cache Controller
diff --git a/Bindings/arm/mrvl/feroceon.txt b/Bindings/cache/marvell,feroceon-cache.txt
similarity index 100%
rename from Bindings/arm/mrvl/feroceon.txt
rename to Bindings/cache/marvell,feroceon-cache.txt
diff --git a/Bindings/arm/mrvl/tauros2.txt b/Bindings/cache/marvell,tauros2-cache.txt
similarity index 100%
rename from Bindings/arm/mrvl/tauros2.txt
rename to Bindings/cache/marvell,tauros2-cache.txt
diff --git a/Bindings/cache/qcom,llcc.yaml b/Bindings/cache/qcom,llcc.yaml
new file mode 100644
index 0000000..d8b9194
--- /dev/null
+++ b/Bindings/cache/qcom,llcc.yaml
@@ -0,0 +1,168 @@
+# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Last Level Cache Controller
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ LLCC (Last Level Cache Controller) provides last level of cache memory in SoC,
+ that can be shared by multiple clients. Clients here are different cores in the
+ SoC, the idea is to minimize the local caches at the clients and migrate to
+ common pool of memory. Cache memory is divided into partitions called slices
+ which are assigned to clients. Clients can query the slice details, activate
+ and deactivate them.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sc7180-llcc
+ - qcom,sc7280-llcc
+ - qcom,sc8180x-llcc
+ - qcom,sc8280xp-llcc
+ - qcom,sdm845-llcc
+ - qcom,sm6350-llcc
+ - qcom,sm7150-llcc
+ - qcom,sm8150-llcc
+ - qcom,sm8250-llcc
+ - qcom,sm8350-llcc
+ - qcom,sm8450-llcc
+ - qcom,sm8550-llcc
+
+ reg:
+ minItems: 2
+ maxItems: 9
+
+ reg-names:
+ minItems: 2
+ maxItems: 9
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - reg-names
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7180-llcc
+ - qcom,sm6350-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc8180x-llcc
+ - qcom,sc8280xp-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC4 base register region
+ - description: LLCC5 base register region
+ - description: LLCC6 base register region
+ - description: LLCC7 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc4_base
+ - const: llcc5_base
+ - const: llcc6_base
+ - const: llcc7_base
+ - const: llcc_broadcast_base
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-llcc
+ - qcom,sm8150-llcc
+ - qcom,sm8250-llcc
+ - qcom,sm8350-llcc
+ - qcom,sm8450-llcc
+ then:
+ properties:
+ reg:
+ items:
+ - description: LLCC0 base register region
+ - description: LLCC1 base register region
+ - description: LLCC2 base register region
+ - description: LLCC3 base register region
+ - description: LLCC broadcast base register region
+ reg-names:
+ items:
+ - const: llcc0_base
+ - const: llcc1_base
+ - const: llcc2_base
+ - const: llcc3_base
+ - const: llcc_broadcast_base
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ system-cache-controller@1100000 {
+ compatible = "qcom,sdm845-llcc";
+ reg = <0 0x01100000 0 0x50000>, <0 0x01180000 0 0x50000>,
+ <0 0x01200000 0 0x50000>, <0 0x01280000 0 0x50000>,
+ <0 0x01300000 0 0x50000>;
+ reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+ "llcc3_base", "llcc_broadcast_base";
+ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/Bindings/riscv/sifive,ccache0.yaml b/Bindings/cache/sifive,ccache0.yaml
similarity index 98%
rename from Bindings/riscv/sifive,ccache0.yaml
rename to Bindings/cache/sifive,ccache0.yaml
index eb6ab73..8a6a78e 100644
--- a/Bindings/riscv/sifive,ccache0.yaml
+++ b/Bindings/cache/sifive,ccache0.yaml
@@ -2,7 +2,7 @@
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
+$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
diff --git a/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Bindings/cache/socionext,uniphier-system-cache.yaml
similarity index 96%
rename from Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
rename to Bindings/cache/socionext,uniphier-system-cache.yaml
index 6096c08..3196263 100644
--- a/Bindings/arm/socionext/socionext,uniphier-system-cache.yaml
+++ b/Bindings/cache/socionext,uniphier-system-cache.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
+$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller
diff --git a/Bindings/chrome/google,cros-ec-typec.yaml b/Bindings/chrome/google,cros-ec-typec.yaml
index defcf1e..3b0548c 100644
--- a/Bindings/chrome/google,cros-ec-typec.yaml
+++ b/Bindings/chrome/google,cros-ec-typec.yaml
@@ -41,7 +41,7 @@
examples:
- |+
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/chrome/google,cros-kbd-led-backlight.yaml b/Bindings/chrome/google,cros-kbd-led-backlight.yaml
index 40244d0..c94ab8f 100644
--- a/Bindings/chrome/google,cros-kbd-led-backlight.yaml
+++ b/Bindings/chrome/google,cros-kbd-led-backlight.yaml
@@ -20,7 +20,7 @@
examples:
- |
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/clock/apple,nco.yaml b/Bindings/clock/apple,nco.yaml
index 74eab5c..8b8411d 100644
--- a/Bindings/clock/apple,nco.yaml
+++ b/Bindings/clock/apple,nco.yaml
@@ -23,6 +23,7 @@
- enum:
- apple,t6000-nco
- apple,t8103-nco
+ - apple,t8112-nco
- const: apple,nco
clocks:
diff --git a/Bindings/clock/arm,syscon-icst.yaml b/Bindings/clock/arm,syscon-icst.yaml
index 90eadf6..b5533f8 100644
--- a/Bindings/clock/arm,syscon-icst.yaml
+++ b/Bindings/clock/arm,syscon-icst.yaml
@@ -81,11 +81,11 @@
maxItems: 1
lock-offset:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the unlocking register for the oscillator
vco-offset:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Offset to the VCO register for the oscillator
deprecated: true
diff --git a/Bindings/clock/brcm,bcm63268-timer-clocks.yaml b/Bindings/clock/brcm,bcm63268-timer-clocks.yaml
new file mode 100644
index 0000000..199818b
--- /dev/null
+++ b/Bindings/clock/brcm,bcm63268-timer-clocks.yaml
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/brcm,bcm63268-timer-clocks.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom BCM63268 Timer Clock and Reset Device Tree Bindings
+
+maintainers:
+ - Álvaro Fernández Rojas <noltari@gmail.com>
+
+properties:
+ compatible:
+ const: brcm,bcm63268-timer-clocks
+
+ reg:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+ "#reset-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#reset-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ timer_clk: clock-controller@100000ac {
+ compatible = "brcm,bcm63268-timer-clocks";
+ reg = <0x100000ac 0x4>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/clock/imx8mp-audiomix.yaml b/Bindings/clock/imx8mp-audiomix.yaml
new file mode 100644
index 0000000..ff96004
--- /dev/null
+++ b/Bindings/clock/imx8mp-audiomix.yaml
@@ -0,0 +1,79 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/imx8mp-audiomix.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP i.MX8MP AudioMIX Block Control Binding
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+description: |
+ NXP i.MX8M Plus AudioMIX is dedicated clock muxing and gating IP
+ used to control Audio related clock on the SoC.
+
+properties:
+ compatible:
+ const: fsl,imx8mp-audio-blk-ctrl
+
+ reg:
+ maxItems: 1
+
+ power-domains:
+ maxItems: 1
+
+ clocks:
+ minItems: 7
+ maxItems: 7
+
+ clock-names:
+ items:
+ - const: ahb
+ - const: sai1
+ - const: sai2
+ - const: sai3
+ - const: sai5
+ - const: sai6
+ - const: sai7
+
+ '#clock-cells':
+ const: 1
+ description:
+ The clock consumer should specify the desired clock by having the clock
+ ID in its "clocks" phandle cell. See include/dt-bindings/clock/imx8mp-clock.h
+ for the full list of i.MX8MP IMX8MP_CLK_AUDIOMIX_ clock IDs.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - power-domains
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ # Clock Control Module node:
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+
+ clock-controller@30e20000 {
+ compatible = "fsl,imx8mp-audio-blk-ctrl";
+ reg = <0x30e20000 0x10000>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>,
+ <&clk IMX8MP_CLK_SAI1>,
+ <&clk IMX8MP_CLK_SAI2>,
+ <&clk IMX8MP_CLK_SAI3>,
+ <&clk IMX8MP_CLK_SAI5>,
+ <&clk IMX8MP_CLK_SAI6>,
+ <&clk IMX8MP_CLK_SAI7>;
+ clock-names = "ahb",
+ "sai1", "sai2", "sai3",
+ "sai5", "sai6", "sai7";
+ power-domains = <&pgc_audio>;
+ };
+
+...
diff --git a/Bindings/clock/loongson,ls1x-clk.yaml b/Bindings/clock/loongson,ls1x-clk.yaml
new file mode 100644
index 0000000..01561a0
--- /dev/null
+++ b/Bindings/clock/loongson,ls1x-clk.yaml
@@ -0,0 +1,45 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/loongson,ls1x-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 Clock Controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@gmail.com>
+
+properties:
+ compatible:
+ enum:
+ - loongson,ls1b-clk
+ - loongson,ls1c-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ "#clock-cells":
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - "#clock-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ clkc: clock-controller@1fe78030 {
+ compatible = "loongson,ls1b-clk";
+ reg = <0x1fe78030 0x8>;
+
+ clocks = <&xtal>;
+ #clock-cells = <1>;
+ };
+
+...
diff --git a/Bindings/clock/mediatek,apmixedsys.yaml b/Bindings/clock/mediatek,apmixedsys.yaml
index dae25db..372c1d7 100644
--- a/Bindings/clock/mediatek,apmixedsys.yaml
+++ b/Bindings/clock/mediatek,apmixedsys.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/mediatek,apmixedsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek AP Mixedsys Controller
diff --git a/Bindings/clock/mediatek,mt8186-fhctl.yaml b/Bindings/clock/mediatek,mt8186-fhctl.yaml
index cfd042a..d00327d 100644
--- a/Bindings/clock/mediatek,mt8186-fhctl.yaml
+++ b/Bindings/clock/mediatek,mt8186-fhctl.yaml
@@ -16,7 +16,12 @@
properties:
compatible:
- const: mediatek,mt8186-fhctl
+ enum:
+ - mediatek,mt6795-fhctl
+ - mediatek,mt8173-fhctl
+ - mediatek,mt8186-fhctl
+ - mediatek,mt8192-fhctl
+ - mediatek,mt8195-fhctl
reg:
maxItems: 1
diff --git a/Bindings/clock/mediatek,mt8188-clock.yaml b/Bindings/clock/mediatek,mt8188-clock.yaml
new file mode 100644
index 0000000..d7214d9
--- /dev/null
+++ b/Bindings/clock/mediatek,mt8188-clock.yaml
@@ -0,0 +1,71 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8188-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Functional Clock Controller for MT8188
+
+maintainers:
+ - Garmin Chang <garmin.chang@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The devices provide clock gate control in different IP blocks.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8188-adsp-audio26m
+ - mediatek,mt8188-camsys
+ - mediatek,mt8188-camsys-rawa
+ - mediatek,mt8188-camsys-rawb
+ - mediatek,mt8188-camsys-yuva
+ - mediatek,mt8188-camsys-yuvb
+ - mediatek,mt8188-ccusys
+ - mediatek,mt8188-imgsys
+ - mediatek,mt8188-imgsys-wpe1
+ - mediatek,mt8188-imgsys-wpe2
+ - mediatek,mt8188-imgsys-wpe3
+ - mediatek,mt8188-imgsys1-dip-nr
+ - mediatek,mt8188-imgsys1-dip-top
+ - mediatek,mt8188-imp-iic-wrap-c
+ - mediatek,mt8188-imp-iic-wrap-en
+ - mediatek,mt8188-imp-iic-wrap-w
+ - mediatek,mt8188-ipesys
+ - mediatek,mt8188-mfgcfg
+ - mediatek,mt8188-vdecsys
+ - mediatek,mt8188-vdecsys-soc
+ - mediatek,mt8188-vencsys
+ - mediatek,mt8188-vppsys0
+ - mediatek,mt8188-vppsys1
+ - mediatek,mt8188-wpesys
+ - mediatek,mt8188-wpesys-vpp0
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@11283000 {
+ compatible = "mediatek,mt8188-imp-iic-wrap-c";
+ reg = <0x11283000 0x1000>;
+ #clock-cells = <1>;
+ };
+
diff --git a/Bindings/clock/mediatek,mt8188-sys-clock.yaml b/Bindings/clock/mediatek,mt8188-sys-clock.yaml
new file mode 100644
index 0000000..4cf8d3a
--- /dev/null
+++ b/Bindings/clock/mediatek,mt8188-sys-clock.yaml
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mediatek,mt8188-sys-clock.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Clock Controller for MT8188
+
+maintainers:
+ - Garmin Chang <garmin.chang@mediatek.com>
+
+description: |
+ The clock architecture in MediaTek like below
+ PLLs -->
+ dividers -->
+ muxes
+ -->
+ clock gate
+
+ The apmixedsys provides most of PLLs which generated from SoC 26m.
+ The topckgen provides dividers and muxes which provide the clock source to other IP blocks.
+ The infracfg_ao provides clock gate in peripheral and infrastructure IP blocks.
+ The mcusys provides mux control to select the clock source in AP MCU.
+ The device nodes also provide the system control capacity for configuration.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8188-apmixedsys
+ - mediatek,mt8188-infracfg-ao
+ - mediatek,mt8188-pericfg-ao
+ - mediatek,mt8188-topckgen
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 1
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@10000000 {
+ compatible = "mediatek,mt8188-topckgen", "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ };
diff --git a/Bindings/clock/mediatek,topckgen.yaml b/Bindings/clock/mediatek,topckgen.yaml
index 0fdf564..6d087de 100644
--- a/Bindings/clock/mediatek,topckgen.yaml
+++ b/Bindings/clock/mediatek,topckgen.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/mediatek,topckgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek Top Clock Generator Controller
diff --git a/Bindings/clock/qcom,a53pll.yaml b/Bindings/clock/qcom,a53pll.yaml
index 525ebaa..659669b 100644
--- a/Bindings/clock/qcom,a53pll.yaml
+++ b/Bindings/clock/qcom,a53pll.yaml
@@ -16,6 +16,7 @@
properties:
compatible:
enum:
+ - qcom,ipq5332-a53pll
- qcom,ipq6018-a53pll
- qcom,ipq8074-a53pll
- qcom,msm8916-a53pll
@@ -45,14 +46,14 @@
additionalProperties: false
examples:
- #Example 1 - A53 PLL found on MSM8916 devices
+ # Example 1 - A53 PLL found on MSM8916 devices
- |
a53pll: clock@b016000 {
compatible = "qcom,msm8916-a53pll";
reg = <0xb016000 0x40>;
#clock-cells = <0>;
};
- #Example 2 - A53 PLL found on IPQ6018 devices
+ # Example 2 - A53 PLL found on IPQ6018 devices
- |
a53pll_ipq: clock-controller@b116000 {
compatible = "qcom,ipq6018-a53pll";
diff --git a/Bindings/clock/qcom,gcc-ipq4019.yaml b/Bindings/clock/qcom,gcc-ipq4019.yaml
new file mode 100644
index 0000000..6ebaef2
--- /dev/null
+++ b/Bindings/clock/qcom,gcc-ipq4019.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-ipq4019.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ4019
+
+maintainers:
+ - Stephen Boyd <sboyd@kernel.org>
+ - Taniya Das <tdas@codeaurora.org>
+ - Robert Marko <robert.markoo@sartura.hr>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ4019.
+
+ See also:: include/dt-bindings/clock/qcom,gcc-ipq4019.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,gcc-ipq4019
+
+ clocks:
+ items:
+ - description: board XO clock
+ - description: sleep clock
+
+ clock-names:
+ items:
+ - const: xo
+ - const: sleep_clk
+
+required:
+ - compatible
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,gcc-ipq4019";
+ reg = <0x1800000 0x60000>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ clocks = <&xo>, <&sleep_clk>;
+ clock-names = "xo", "sleep_clk";
+ };
+...
diff --git a/Bindings/clock/qcom,gcc-msm8909.yaml b/Bindings/clock/qcom,gcc-msm8909.yaml
index 6279a59..b914625 100644
--- a/Bindings/clock/qcom,gcc-msm8909.yaml
+++ b/Bindings/clock/qcom,gcc-msm8909.yaml
@@ -4,20 +4,25 @@
$id: http://devicetree.org/schemas/clock/qcom,gcc-msm8909.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Global Clock & Reset Controller on MSM8909
+title: Qualcomm Global Clock & Reset Controller on MSM8909, MSM8917 and QM215
maintainers:
- Stephan Gerhold <stephan@gerhold.net>
description: |
Qualcomm global clock control module provides the clocks, resets and power
- domains on MSM8909.
+ domains on MSM8909, MSM8917 or QM215.
- See also:: include/dt-bindings/clock/qcom,gcc-msm8909.h
+ See also::
+ include/dt-bindings/clock/qcom,gcc-msm8909.h
+ include/dt-bindings/clock/qcom,gcc-msm8917.h
properties:
compatible:
- const: qcom,gcc-msm8909
+ enum:
+ - qcom,gcc-msm8909
+ - qcom,gcc-msm8917
+ - qcom,gcc-qm215
clocks:
items:
diff --git a/Bindings/clock/qcom,gcc-other.yaml b/Bindings/clock/qcom,gcc-other.yaml
index 2e8acca..ae01e77 100644
--- a/Bindings/clock/qcom,gcc-other.yaml
+++ b/Bindings/clock/qcom,gcc-other.yaml
@@ -15,7 +15,6 @@
domains.
See also::
- include/dt-bindings/clock/qcom,gcc-ipq4019.h
include/dt-bindings/clock/qcom,gcc-ipq6018.h
include/dt-bindings/reset/qcom,gcc-ipq6018.h
include/dt-bindings/clock/qcom,gcc-msm8953.h
@@ -29,7 +28,6 @@
properties:
compatible:
enum:
- - qcom,gcc-ipq4019
- qcom,gcc-ipq6018
- qcom,gcc-mdm9607
- qcom,gcc-msm8953
diff --git a/Bindings/clock/qcom,gpucc.yaml b/Bindings/clock/qcom,gpucc.yaml
index db53eb2..1e3dc9d 100644
--- a/Bindings/clock/qcom,gpucc.yaml
+++ b/Bindings/clock/qcom,gpucc.yaml
@@ -15,6 +15,7 @@
See also::
include/dt-bindings/clock/qcom,gpucc-sdm845.h
+ include/dt-bindings/clock/qcom,gpucc-sa8775p.h
include/dt-bindings/clock/qcom,gpucc-sc7180.h
include/dt-bindings/clock/qcom,gpucc-sc7280.h
include/dt-bindings/clock/qcom,gpucc-sc8280xp.h
@@ -27,6 +28,7 @@
compatible:
enum:
- qcom,sdm845-gpucc
+ - qcom,sa8775p-gpucc
- qcom,sc7180-gpucc
- qcom,sc7280-gpucc
- qcom,sc8180x-gpucc
diff --git a/Bindings/clock/qcom,ipq5332-gcc.yaml b/Bindings/clock/qcom,ipq5332-gcc.yaml
new file mode 100644
index 0000000..718fe06
--- /dev/null
+++ b/Bindings/clock/qcom,ipq5332-gcc.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq5332-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ5332
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ5332.
+
+ See also:: include/dt-bindings/clock/qcom,gcc-ipq5332.h
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+properties:
+ compatible:
+ const: qcom,ipq5332-gcc
+
+ clocks:
+ items:
+ - description: Board XO clock source
+ - description: Sleep clock source
+ - description: PCIE 2lane PHY pipe clock source
+ - description: PCIE 2lane x1 PHY pipe clock source (For second lane)
+ - description: USB PCIE wrapper pipe clock source
+
+required:
+ - compatible
+ - clocks
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,ipq5332-gcc";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board>,
+ <&sleep_clk>,
+ <&pcie_2lane_phy_pipe_clk>,
+ <&pcie_2lane_phy_pipe_clk_x1>,
+ <&usb_pcie_wrapper_pipe_clk>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ #reset-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/qcom,ipq9574-gcc.yaml b/Bindings/clock/qcom,ipq9574-gcc.yaml
new file mode 100644
index 0000000..afc68eb
--- /dev/null
+++ b/Bindings/clock/qcom,ipq9574-gcc.yaml
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,ipq9574-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on IPQ9574
+
+maintainers:
+ - Anusha Rao <quic_anusha@quicinc.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on IPQ9574
+
+ See also::
+ include/dt-bindings/clock/qcom,ipq9574-gcc.h
+ include/dt-bindings/reset/qcom,ipq9574-gcc.h
+
+properties:
+ compatible:
+ const: qcom,ipq9574-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Sleep clock source
+ - description: Bias PLL ubi clock source
+ - description: PCIE30 PHY0 pipe clock source
+ - description: PCIE30 PHY1 pipe clock source
+ - description: PCIE30 PHY2 pipe clock source
+ - description: PCIE30 PHY3 pipe clock source
+ - description: USB3 PHY pipe clock source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ clock-controller@1800000 {
+ compatible = "qcom,ipq9574-gcc";
+ reg = <0x01800000 0x80000>;
+ clocks = <&xo_board_clk>,
+ <&sleep_clk>,
+ <&bias_pll_ubi_nc_clk>,
+ <&pcie30_phy0_pipe_clk>,
+ <&pcie30_phy1_pipe_clk>,
+ <&pcie30_phy2_pipe_clk>,
+ <&pcie30_phy3_pipe_clk>,
+ <&usb3phy_0_cc_pipe_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/qcom,kpss-acc-v1.yaml b/Bindings/clock/qcom,kpss-acc-v1.yaml
new file mode 100644
index 0000000..a466e4e
--- /dev/null
+++ b/Bindings/clock/qcom,kpss-acc-v1.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kpss-acc-v1.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Application Clock Controller (ACC) v1
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ The KPSS ACC provides clock, power domain, and reset control to a Krait CPU.
+ There is one ACC register region per CPU within the KPSS remapped region as
+ well as an alias register region that remaps accesses to the ACC associated
+ with the CPU accessing the region. ACC v1 is currently used as a
+ clock-controller for enabling the cpu and hanling the aux clocks.
+
+properties:
+ compatible:
+ const: qcom,kpss-acc-v1
+
+ reg:
+ items:
+ - description: Base address and size of the register region
+ - description: Optional base address and size of the alias register region
+ minItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pll8_vote
+ - const: pxo
+
+ clock-output-names:
+ description: Name of the aux clock. Krait can have at most 4 cpu.
+ enum:
+ - acpu0_aux
+ - acpu1_aux
+ - acpu2_aux
+ - acpu3_aux
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - clock-output-names
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+ clock-controller@2088000 {
+ compatible = "qcom,kpss-acc-v1";
+ reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ clock-output-names = "acpu0_aux";
+ #clock-cells = <0>;
+ };
+
+...
diff --git a/Bindings/clock/qcom,kpss-gcc.yaml b/Bindings/clock/qcom,kpss-gcc.yaml
new file mode 100644
index 0000000..88b7672
--- /dev/null
+++ b/Bindings/clock/qcom,kpss-gcc.yaml
@@ -0,0 +1,88 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,kpss-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Krait Processor Sub-system (KPSS) Global Clock Controller (GCC)
+
+maintainers:
+ - Christian Marangi <ansuelsmth@gmail.com>
+
+description:
+ Krait Processor Sub-system (KPSS) Global Clock Controller (GCC). Used
+ to control L2 mux (in the current implementation) and provide access
+ to the kpss-gcc registers.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,kpss-gcc-ipq8064
+ - qcom,kpss-gcc-apq8064
+ - qcom,kpss-gcc-msm8974
+ - qcom,kpss-gcc-msm8960
+ - qcom,kpss-gcc-msm8660
+ - qcom,kpss-gcc-mdm9615
+ - const: qcom,kpss-gcc
+ - const: syscon
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: pll8_vote
+ - const: pxo
+
+ '#clock-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,kpss-gcc-ipq8064
+ - qcom,kpss-gcc-apq8064
+ - qcom,kpss-gcc-msm8974
+ - qcom,kpss-gcc-msm8960
+then:
+ required:
+ - clocks
+ - clock-names
+ - '#clock-cells'
+else:
+ properties:
+ clock: false
+ clock-names: false
+ '#clock-cells': false
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+
+ clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-ipq8064", "qcom,kpss-gcc", "syscon";
+ reg = <0x2011000 0x1000>;
+ clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
+ clock-names = "pll8_vote", "pxo";
+ #clock-cells = <0>;
+ };
+
+ - |
+ clock-controller@2011000 {
+ compatible = "qcom,kpss-gcc-mdm9615", "qcom,kpss-gcc", "syscon";
+ reg = <0x02011000 0x1000>;
+ };
+...
diff --git a/Bindings/clock/qcom,rpmcc.yaml b/Bindings/clock/qcom,rpmcc.yaml
index 2a95bf8..3665dd3 100644
--- a/Bindings/clock/qcom,rpmcc.yaml
+++ b/Bindings/clock/qcom,rpmcc.yaml
@@ -31,6 +31,7 @@
- qcom,rpmcc-msm8660
- qcom,rpmcc-msm8909
- qcom,rpmcc-msm8916
+ - qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
@@ -107,6 +108,7 @@
- qcom,rpmcc-mdm9607
- qcom,rpmcc-msm8226
- qcom,rpmcc-msm8916
+ - qcom,rpmcc-msm8917
- qcom,rpmcc-msm8936
- qcom,rpmcc-msm8953
- qcom,rpmcc-msm8974
diff --git a/Bindings/clock/qcom,sc7280-lpasscc.yaml b/Bindings/clock/qcom,sc7280-lpasscc.yaml
index 6151fde..97c6bd9 100644
--- a/Bindings/clock/qcom,sc7280-lpasscc.yaml
+++ b/Bindings/clock/qcom,sc7280-lpasscc.yaml
@@ -41,6 +41,12 @@
- const: qdsp6ss
- const: top_cc
+ qcom,adsp-pil-mode:
+ description:
+ Indicates if the LPASS would be brought out of reset using
+ remoteproc peripheral loader.
+ type: boolean
+
required:
- compatible
- reg
@@ -60,6 +66,7 @@
reg-names = "qdsp6ss", "top_cc";
clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>;
clock-names = "iface";
+ qcom,adsp-pil-mode;
#clock-cells = <1>;
};
...
diff --git a/Bindings/clock/qcom,sm6115-gpucc.yaml b/Bindings/clock/qcom,sm6115-gpucc.yaml
new file mode 100644
index 0000000..cf19f44
--- /dev/null
+++ b/Bindings/clock/qcom,sm6115-gpucc.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6115-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on SM6115
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+ Qualcomm graphics clock control module provides clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also:: include/dt-bindings/clock/qcom,sm6115-gpucc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6115-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+ - description: GPLL0 main div source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6115.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clock-controller@5990000 {
+ compatible = "qcom,sm6115-gpucc";
+ reg = <0x05990000 0x9000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/clock/qcom,sm6125-gpucc.yaml b/Bindings/clock/qcom,sm6125-gpucc.yaml
new file mode 100644
index 0000000..374a184
--- /dev/null
+++ b/Bindings/clock/qcom,sm6125-gpucc.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6125-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on SM6125
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+ Qualcomm graphics clock control module provides clocks and power domains on
+ Qualcomm SoCs.
+
+ See also:: include/dt-bindings/clock/qcom,sm6125-gpucc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6125-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+
+ '#clock-cells':
+ const: 1
+
+ '#power-domain-cells':
+ const: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+ - '#power-domain-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sm6125.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ clock-controller@5990000 {
+ compatible = "qcom,sm6125-gpucc";
+ reg = <0x05990000 0x9000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>;
+ #clock-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/clock/qcom,sm6375-gpucc.yaml b/Bindings/clock/qcom,sm6375-gpucc.yaml
new file mode 100644
index 0000000..b480ead
--- /dev/null
+++ b/Bindings/clock/qcom,sm6375-gpucc.yaml
@@ -0,0 +1,60 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm6375-gpucc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Graphics Clock & Reset Controller on SM6375
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+ Qualcomm graphics clock control module provides clocks, resets and power
+ domains on Qualcomm SoCs.
+
+ See also:: include/dt-bindings/clock/qcom,sm6375-gpucc.h
+
+properties:
+ compatible:
+ enum:
+ - qcom,sm6375-gpucc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: GPLL0 main branch source
+ - description: GPLL0 div branch source
+ - description: SNoC DVM GFX source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm6375-gcc.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clock-controller@5990000 {
+ compatible = "qcom,sm6375-gpucc";
+ reg = <0 0x05990000 0 0x9000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_CLK_SRC>,
+ <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>,
+ <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+ };
+...
diff --git a/Bindings/clock/qcom,sm7150-gcc.yaml b/Bindings/clock/qcom,sm7150-gcc.yaml
new file mode 100644
index 0000000..0eb76d9
--- /dev/null
+++ b/Bindings/clock/qcom,sm7150-gcc.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,sm7150-gcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller on SM7150
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+ - Danila Tikhonov <danila@jiaxyga.com>
+ - David Wronek <davidwronek@gmail.com>
+
+description: |
+ Qualcomm global clock control module provides the clocks, resets and power
+ domains on SM7150
+
+ See also:: include/dt-bindings/clock/qcom,sm7150-gcc.h
+
+properties:
+ compatible:
+ const: qcom,sm7150-gcc
+
+ clocks:
+ items:
+ - description: Board XO source
+ - description: Board XO Active-Only source
+ - description: Sleep clock source
+
+required:
+ - compatible
+ - clocks
+
+allOf:
+ - $ref: qcom,gcc.yaml#
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ clock-controller@100000 {
+ compatible = "qcom,sm7150-gcc";
+ reg = <0x00100000 0x001f0000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>,
+ <&rpmhcc RPMH_CXO_CLK_A>,
+ <&sleep_clk>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+...
diff --git a/Bindings/clock/renesas,9series.yaml b/Bindings/clock/renesas,9series.yaml
index 6b6cec3..3afdebd 100644
--- a/Bindings/clock/renesas,9series.yaml
+++ b/Bindings/clock/renesas,9series.yaml
@@ -16,6 +16,11 @@
- 9FGV0241:
0 -- DIF0
1 -- DIF1
+ - 9FGV0441:
+ 0 -- DIF0
+ 1 -- DIF1
+ 2 -- DIF2
+ 3 -- DIF3
maintainers:
- Marek Vasut <marex@denx.de>
@@ -24,6 +29,7 @@
compatible:
enum:
- renesas,9fgv0241
+ - renesas,9fgv0441
reg:
description: I2C device address
diff --git a/Bindings/clock/renesas,cpg-mssr.yaml b/Bindings/clock/renesas,cpg-mssr.yaml
index e57bc40..9c3dc6c 100644
--- a/Bindings/clock/renesas,cpg-mssr.yaml
+++ b/Bindings/clock/renesas,cpg-mssr.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/renesas,cpg-mssr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas Clock Pulse Generator / Module Standby and Software Reset
diff --git a/Bindings/clock/renesas,r9a06g032-sysctrl.yaml b/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
index 95bf485..9968608 100644
--- a/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
+++ b/Bindings/clock/renesas,r9a06g032-sysctrl.yaml
@@ -7,7 +7,7 @@
title: Renesas RZ/N1D (R9A06G032) System Controller
maintainers:
- - Gareth Williams <gareth.williams.jx@renesas.com>
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
- Geert Uytterhoeven <geert+renesas@glider.be>
properties:
diff --git a/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml b/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml
index 81f09df..c84f29f 100644
--- a/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml
+++ b/Bindings/clock/renesas,rcar-usb2-clock-sel.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/renesas,rcar-usb2-clock-sel.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas R-Car USB 2.0 clock selector
diff --git a/Bindings/clock/renesas,rzg2l-cpg.yaml b/Bindings/clock/renesas,rzg2l-cpg.yaml
index 487f74c..fe2fba1 100644
--- a/Bindings/clock/renesas,rzg2l-cpg.yaml
+++ b/Bindings/clock/renesas,rzg2l-cpg.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/renesas,rzg2l-cpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/{G2L,V2L,V2M} Clock Pulse Generator / Module Standby Mode
diff --git a/Bindings/clock/samsung,exynos850-clock.yaml b/Bindings/clock/samsung,exynos850-clock.yaml
index 141cf17..c752c89 100644
--- a/Bindings/clock/samsung,exynos850-clock.yaml
+++ b/Bindings/clock/samsung,exynos850-clock.yaml
@@ -37,6 +37,7 @@
- samsung,exynos850-cmu-cmgp
- samsung,exynos850-cmu-core
- samsung,exynos850-cmu-dpu
+ - samsung,exynos850-cmu-g3d
- samsung,exynos850-cmu-hsi
- samsung,exynos850-cmu-is
- samsung,exynos850-cmu-mfcmscl
@@ -173,6 +174,24 @@
properties:
compatible:
contains:
+ const: samsung,exynos850-cmu-g3d
+
+ then:
+ properties:
+ clocks:
+ items:
+ - description: External reference clock (26 MHz)
+ - description: G3D clock (from CMU_TOP)
+
+ clock-names:
+ items:
+ - const: oscclk
+ - const: dout_g3d_switch
+
+ - if:
+ properties:
+ compatible:
+ contains:
const: samsung,exynos850-cmu-hsi
then:
@@ -183,7 +202,7 @@
- description: External RTC clock (32768 Hz)
- description: CMU_HSI bus clock (from CMU_TOP)
- description: SD card clock (from CMU_TOP)
- - description: "USB 2.0 DRD clock (from CMU_TOP)"
+ - description: USB 2.0 DRD clock (from CMU_TOP)
clock-names:
items:
diff --git a/Bindings/clock/skyworks,si521xx.yaml b/Bindings/clock/skyworks,si521xx.yaml
new file mode 100644
index 0000000..9e35e0e
--- /dev/null
+++ b/Bindings/clock/skyworks,si521xx.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/skyworks,si521xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Skyworks Si521xx I2C PCIe clock generators
+
+description: |
+ The Skyworks Si521xx are I2C PCIe clock generators providing
+ from 4 to 9 output clocks.
+
+maintainers:
+ - Marek Vasut <marex@denx.de>
+
+properties:
+ compatible:
+ enum:
+ - skyworks,si52144
+ - skyworks,si52146
+ - skyworks,si52147
+
+ reg:
+ const: 0x6b
+
+ '#clock-cells':
+ const: 1
+
+ clocks:
+ items:
+ - description: XTal input clock
+
+ skyworks,out-amplitude-microvolt:
+ enum: [ 300000, 400000, 500000, 600000, 700000, 800000, 900000, 1000000 ]
+ description: Output clock signal amplitude
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ clock-generator@6b {
+ compatible = "skyworks,si52144";
+ reg = <0x6b>;
+ #clock-cells = <1>;
+ clocks = <&ref25m>;
+ };
+ };
+
+...
diff --git a/Bindings/clock/sprd,sc9863a-clk.yaml b/Bindings/clock/sprd,sc9863a-clk.yaml
index 785a127..1703e30 100644
--- a/Bindings/clock/sprd,sc9863a-clk.yaml
+++ b/Bindings/clock/sprd,sc9863a-clk.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Unisoc Inc.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/sprd,sc9863a-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SC9863A Clock Control Unit
diff --git a/Bindings/clock/sprd,ums512-clk.yaml b/Bindings/clock/sprd,ums512-clk.yaml
index 5f747b0..43d2b6c 100644
--- a/Bindings/clock/sprd,ums512-clk.yaml
+++ b/Bindings/clock/sprd,ums512-clk.yaml
@@ -2,8 +2,8 @@
# Copyright 2022 Unisoc Inc.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/sprd,ums512-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UMS512 Soc clock controller
diff --git a/Bindings/clock/starfive,jh7110-aoncrg.yaml b/Bindings/clock/starfive,jh7110-aoncrg.yaml
new file mode 100644
index 0000000..923680a
--- /dev/null
+++ b/Bindings/clock/starfive,jh7110-aoncrg.yaml
@@ -0,0 +1,107 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-aoncrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Always-On Clock and Reset Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7110-aoncrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ oneOf:
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
+ - description: STG AXI/AHB
+ - description: APB Bus
+ - description: GMAC0 GTX
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference or GMAC0 RGMII RX
+ - description: STG AXI/AHB or GMAC0 RGMII RX
+ - description: APB Bus or STG AXI/AHB
+ - description: GMAC0 GTX or APB Bus
+ - description: RTC Oscillator (32.768 kHz) or GMAC0 GTX
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC0 RMII reference
+ - description: GMAC0 RGMII RX
+ - description: STG AXI/AHB
+ - description: APB Bus
+ - description: GMAC0 GTX
+ - description: RTC Oscillator (32.768 kHz)
+
+ clock-names:
+ oneOf:
+ - minItems: 5
+ items:
+ - const: osc
+ - enum:
+ - gmac0_rmii_refin
+ - gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus
+ - const: gmac0_gtxclk
+ - const: rtc_osc
+
+ - minItems: 6
+ items:
+ - const: osc
+ - const: gmac0_rmii_refin
+ - const: gmac0_rgmii_rxin
+ - const: stg_axiahb
+ - const: apb_bus
+ - const: gmac0_gtxclk
+ - const: rtc_osc
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive,jh7110-crg.h>
+
+ clock-controller@17000000 {
+ compatible = "starfive,jh7110-aoncrg";
+ reg = <0x17000000 0x10000>;
+ clocks = <&osc>, <&gmac0_rmii_refin>,
+ <&gmac0_rgmii_rxin>,
+ <&syscrg JH7110_SYSCLK_STG_AXIAHB>,
+ <&syscrg JH7110_SYSCLK_APB_BUS>,
+ <&syscrg JH7110_SYSCLK_GMAC0_GTXCLK>,
+ <&rtc_osc>;
+ clock-names = "osc", "gmac0_rmii_refin",
+ "gmac0_rgmii_rxin", "stg_axiahb",
+ "apb_bus", "gmac0_gtxclk",
+ "rtc_osc";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/clock/starfive,jh7110-syscrg.yaml b/Bindings/clock/starfive,jh7110-syscrg.yaml
new file mode 100644
index 0000000..84373ae3
--- /dev/null
+++ b/Bindings/clock/starfive,jh7110-syscrg.yaml
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-syscrg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 System Clock and Reset Generator
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+properties:
+ compatible:
+ const: starfive,jh7110-syscrg
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ oneOf:
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC1 RMII reference or GMAC1 RGMII RX
+ - description: External I2S TX bit clock
+ - description: External I2S TX left/right channel clock
+ - description: External I2S RX bit clock
+ - description: External I2S RX left/right channel clock
+ - description: External TDM clock
+ - description: External audio master clock
+
+ - items:
+ - description: Main Oscillator (24 MHz)
+ - description: GMAC1 RMII reference
+ - description: GMAC1 RGMII RX
+ - description: External I2S TX bit clock
+ - description: External I2S TX left/right channel clock
+ - description: External I2S RX bit clock
+ - description: External I2S RX left/right channel clock
+ - description: External TDM clock
+ - description: External audio master clock
+
+ clock-names:
+ oneOf:
+ - items:
+ - const: osc
+ - enum:
+ - gmac1_rmii_refin
+ - gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+
+ - items:
+ - const: osc
+ - const: gmac1_rmii_refin
+ - const: gmac1_rgmii_rxin
+ - const: i2stx_bclk_ext
+ - const: i2stx_lrck_ext
+ - const: i2srx_bclk_ext
+ - const: i2srx_lrck_ext
+ - const: tdm_ext
+ - const: mclk_ext
+
+ '#clock-cells':
+ const: 1
+ description:
+ See <dt-bindings/clock/starfive,jh7110-crg.h> for valid indices.
+
+ '#reset-cells':
+ const: 1
+ description:
+ See <dt-bindings/reset/starfive,jh7110-crg.h> for valid indices.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - '#clock-cells'
+ - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ clock-controller@13020000 {
+ compatible = "starfive,jh7110-syscrg";
+ reg = <0x13020000 0x10000>;
+ clocks = <&osc>, <&gmac1_rmii_refin>,
+ <&gmac1_rgmii_rxin>,
+ <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+ <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+ <&tdm_ext>, <&mclk_ext>;
+ clock-names = "osc", "gmac1_rmii_refin",
+ "gmac1_rgmii_rxin",
+ "i2stx_bclk_ext", "i2stx_lrck_ext",
+ "i2srx_bclk_ext", "i2srx_lrck_ext",
+ "tdm_ext", "mclk_ext";
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
diff --git a/Bindings/clock/ti,lmk04832.yaml b/Bindings/clock/ti,lmk04832.yaml
index 73d1783..13d7b3d 100644
--- a/Bindings/clock/ti,lmk04832.yaml
+++ b/Bindings/clock/ti,lmk04832.yaml
@@ -160,7 +160,7 @@
};
};
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/clock/xlnx,clocking-wizard.yaml b/Bindings/clock/xlnx,clocking-wizard.yaml
index 634b7b9..c1f0483 100644
--- a/Bindings/clock/xlnx,clocking-wizard.yaml
+++ b/Bindings/clock/xlnx,clocking-wizard.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/clock/xlnx,clocking-wizard.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx clocking wizard
diff --git a/Bindings/cpufreq/cpufreq-qcom-hw.yaml b/Bindings/cpufreq/cpufreq-qcom-hw.yaml
index e4aa8c6..a6b3bb8 100644
--- a/Bindings/cpufreq/cpufreq-qcom-hw.yaml
+++ b/Bindings/cpufreq/cpufreq-qcom-hw.yaml
@@ -20,12 +20,20 @@
oneOf:
- description: v1 of CPUFREQ HW
items:
+ - enum:
+ - qcom,qcm2290-cpufreq-hw
+ - qcom,sc7180-cpufreq-hw
+ - qcom,sdm845-cpufreq-hw
+ - qcom,sm6115-cpufreq-hw
+ - qcom,sm6350-cpufreq-hw
+ - qcom,sm8150-cpufreq-hw
- const: qcom,cpufreq-hw
- description: v2 of CPUFREQ HW (EPSS)
items:
- enum:
- qcom,qdu1000-cpufreq-epss
+ - qcom,sa8775p-cpufreq-epss
- qcom,sc7280-cpufreq-epss
- qcom,sc8280xp-cpufreq-epss
- qcom,sm6375-cpufreq-epss
@@ -36,14 +44,14 @@
- const: qcom,cpufreq-epss
reg:
- minItems: 2
+ minItems: 1
items:
- description: Frequency domain 0 register region
- description: Frequency domain 1 register region
- description: Frequency domain 2 register region
reg-names:
- minItems: 2
+ minItems: 1
items:
- const: freq-domain0
- const: freq-domain1
@@ -85,6 +93,111 @@
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qcm2290-cpufreq-hw
+ then:
+ properties:
+ reg:
+ minItems: 1
+ maxItems: 1
+
+ reg-names:
+ minItems: 1
+ maxItems: 1
+
+ interrupts:
+ minItems: 1
+ maxItems: 1
+
+ interrupt-names:
+ minItems: 1
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,qdu1000-cpufreq-epss
+ - qcom,sc7180-cpufreq-hw
+ - qcom,sc8280xp-cpufreq-epss
+ - qcom,sdm845-cpufreq-hw
+ - qcom,sm6115-cpufreq-hw
+ - qcom,sm6350-cpufreq-hw
+ - qcom,sm6375-cpufreq-epss
+ then:
+ properties:
+ reg:
+ minItems: 2
+ maxItems: 2
+
+ reg-names:
+ minItems: 2
+ maxItems: 2
+
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 2
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sc7280-cpufreq-epss
+ - qcom,sm8250-cpufreq-epss
+ - qcom,sm8350-cpufreq-epss
+ - qcom,sm8450-cpufreq-epss
+ - qcom,sm8550-cpufreq-epss
+ then:
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ minItems: 3
+ maxItems: 3
+
+ interrupts:
+ minItems: 3
+ maxItems: 3
+
+ interrupt-names:
+ minItems: 3
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sm8150-cpufreq-hw
+ then:
+ properties:
+ reg:
+ minItems: 3
+ maxItems: 3
+
+ reg-names:
+ minItems: 3
+ maxItems: 3
+
+ # On some SoCs the Prime core shares the LMH irq with Big cores
+ interrupts:
+ minItems: 2
+ maxItems: 2
+
+ interrupt-names:
+ minItems: 2
+
+
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
@@ -235,7 +348,7 @@
#size-cells = <1>;
cpufreq@17d43000 {
- compatible = "qcom,cpufreq-hw";
+ compatible = "qcom,sdm845-cpufreq-hw", "qcom,cpufreq-hw";
reg = <0x17d43000 0x1400>, <0x17d45800 0x1400>;
reg-names = "freq-domain0", "freq-domain1";
diff --git a/Bindings/crypto/fsl,sec-v4.0-mon.yaml b/Bindings/crypto/fsl,sec-v4.0-mon.yaml
new file mode 100644
index 0000000..286dffa
--- /dev/null
+++ b/Bindings/crypto/fsl,sec-v4.0-mon.yaml
@@ -0,0 +1,156 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0-mon.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale Secure Non-Volatile Storage (SNVS)
+
+maintainers:
+ - '"Horia Geantă" <horia.geanta@nxp.com>'
+ - Pankaj Gupta <pankaj.gupta@nxp.com>
+ - Gaurav Jain <gaurav.jain@nxp.com>
+
+description:
+ Node defines address range and the associated interrupt for the SNVS function.
+ This function monitors security state information & reports security
+ violations. This also included rtc, system power off and ON/OFF key.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,sec-v4.0-mon
+ - const: syscon
+ - const: simple-mfd
+ - items:
+ - const: fsl,sec-v5.0-mon
+ - const: fsl,sec-v4.0-mon
+ - items:
+ - enum:
+ - fsl,sec-v5.3-mon
+ - fsl,sec-v5.4-mon
+ - const: fsl,sec-v5.0-mon
+ - const: fsl,sec-v4.0-mon
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 2
+
+ snvs-rtc-lp:
+ type: object
+ additionalProperties: false
+ description:
+ Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
+
+ properties:
+ compatible:
+ const: fsl,sec-v4.0-mon-rtc-lp
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: snvs-rtc
+
+ interrupts:
+ # VFxxx has only one. What is the 2nd one?
+ minItems: 1
+ maxItems: 2
+
+ regmap:
+ description: Parent node containing registers
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ offset:
+ description: LP register offset
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0x34
+
+ required:
+ - compatible
+ - interrupts
+ - regmap
+
+ snvs-powerkey:
+ type: object
+ additionalProperties: false
+ description:
+ The snvs-pwrkey is designed to enable POWER key function which controlled
+ by SNVS ONOFF, the driver can report the status of POWER key and wakeup
+ system if pressed after system suspend.
+
+ properties:
+ compatible:
+ const: fsl,sec-v4.0-pwrkey
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: snvs-pwrkey
+
+ interrupts:
+ maxItems: 1
+
+ regmap:
+ description: Parent node containing registers
+ $ref: /schemas/types.yaml#/definitions/phandle
+
+ wakeup-source: true
+
+ linux,keycode:
+ default: 116
+
+ required:
+ - compatible
+ - interrupts
+ - regmap
+
+ snvs-lpgpr:
+ $ref: /schemas/nvmem/snvs-lpgpr.yaml#
+
+ snvs-poweroff:
+ description:
+ The SNVS could drive signal to PMIC to turn off system power by setting
+ SNVS_LP LPCR register.
+ $ref: /schemas/power/reset/syscon-poweroff.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/imx7d-clock.h>
+
+ sec_mon: sec-mon@314000 {
+ compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
+ reg = <0x314000 0x1000>;
+
+ snvs-rtc-lp {
+ compatible = "fsl,sec-v4.0-mon-rtc-lp";
+ regmap = <&sec_mon>;
+ offset = <0x34>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-rtc";
+ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
+ };
+
+ snvs-powerkey {
+ compatible = "fsl,sec-v4.0-pwrkey";
+ regmap = <&sec_mon>;
+ clocks = <&clks IMX7D_SNVS_CLK>;
+ clock-names = "snvs-pwrkey";
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ linux,keycode = <116>; /* KEY_POWER */
+ wakeup-source;
+ };
+ };
diff --git a/Bindings/crypto/fsl,sec-v4.0.yaml b/Bindings/crypto/fsl,sec-v4.0.yaml
new file mode 100644
index 0000000..0a9ed28
--- /dev/null
+++ b/Bindings/crypto/fsl,sec-v4.0.yaml
@@ -0,0 +1,266 @@
+# SPDX-License-Identifier: GPL-2.0
+# Copyright (C) 2008-2011 Freescale Semiconductor Inc.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/fsl,sec-v4.0.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Freescale SEC 4
+
+maintainers:
+ - '"Horia Geantă" <horia.geanta@nxp.com>'
+ - Pankaj Gupta <pankaj.gupta@nxp.com>
+ - Gaurav Jain <gaurav.jain@nxp.com>
+
+description: |
+ NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
+ Accelerator and Assurance Module (CAAM).
+
+ SEC 4 h/w can process requests from 2 types of sources.
+ 1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
+ 2. Job Rings (HW interface between cores & SEC 4 registers).
+
+ High Speed Data Path Configuration:
+
+ HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
+ such as the P4080. The number of simultaneous dequeues the QI can make is
+ equal to the number of Descriptor Controller (DECO) engines in a particular
+ SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
+ dequeue from 5 subportals simultaneously.
+
+ Job Ring Data Path Configuration:
+
+ Each JR is located on a separate 4k page, they may (or may not) be made visible
+ in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
+ up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,sec-v5.4
+ - const: fsl,sec-v5.0
+ - const: fsl,sec-v4.0
+ - items:
+ - enum:
+ - fsl,imx6ul-caam
+ - fsl,sec-v5.0
+ - const: fsl,sec-v4.0
+ - const: fsl,sec-v4.0
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ maxItems: 1
+
+ '#address-cells':
+ enum: [1, 2]
+
+ '#size-cells':
+ enum: [1, 2]
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+ items:
+ enum: [mem, aclk, ipg, emi_slow]
+
+ dma-coherent: true
+
+ interrupts:
+ maxItems: 1
+
+ fsl,sec-era:
+ description: Defines the 'ERA' of the SEC device.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+patternProperties:
+ '^jr@[0-9a-f]+$':
+ type: object
+ additionalProperties: false
+ description:
+ Job Ring (JR) Node. Defines data processing interface to SEC 4 across the
+ peripheral bus for purposes of processing cryptographic descriptors. The
+ specified address range can be made visible to one (or more) cores. The
+ interrupt defined for this node is controlled within the address range of
+ this node.
+
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,sec-v5.4-job-ring
+ - const: fsl,sec-v5.0-job-ring
+ - const: fsl,sec-v4.0-job-ring
+ - items:
+ - const: fsl,sec-v5.0-job-ring
+ - const: fsl,sec-v4.0-job-ring
+ - const: fsl,sec-v4.0-job-ring
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ fsl,liodn:
+ description:
+ Specifies the LIODN to be used in conjunction with the ppid-to-liodn
+ table that specifies the PPID to LIODN mapping. Needed if the PAMU is
+ used. Value is a 12 bit value where value is a LIODN ID for this JR.
+ This property is normally set by boot firmware.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 0xfff
+
+ '^rtic@[0-9a-f]+$':
+ type: object
+ additionalProperties: false
+ description:
+ Run Time Integrity Check (RTIC) Node. Defines a register space that
+ contains up to 5 sets of addresses and their lengths (sizes) that will be
+ checked at run time. After an initial hash result is calculated, these
+ addresses are checked by HW to monitor any change. If any memory is
+ modified, a Security Violation is triggered (see SNVS definition).
+
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,sec-v5.4-rtic
+ - const: fsl,sec-v5.0-rtic
+ - const: fsl,sec-v4.0-rtic
+ - const: fsl,sec-v4.0-rtic
+
+ reg:
+ maxItems: 1
+
+ ranges:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ patternProperties:
+ '^rtic-[a-z]@[0-9a-f]+$':
+ type: object
+ additionalProperties: false
+ description:
+ Run Time Integrity Check (RTIC) Memory Node defines individual RTIC
+ memory regions that are used to perform run-time integrity check of
+ memory areas that should not modified. The node defines a register
+ that contains the memory address & length (combined) and a second
+ register that contains the hash result in big endian format.
+
+ properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: fsl,sec-v5.4-rtic-memory
+ - const: fsl,sec-v5.0-rtic-memory
+ - const: fsl,sec-v4.0-rtic-memory
+ - const: fsl,sec-v4.0-rtic-memory
+
+ reg:
+ items:
+ - description: RTIC memory address
+ - description: RTIC hash result
+
+ fsl,liodn:
+ description:
+ Specifies the LIODN to be used in conjunction with the
+ ppid-to-liodn table that specifies the PPID to LIODN mapping.
+ Needed if the PAMU is used. Value is a 12 bit value where value
+ is a LIODN ID for this JR. This property is normally set by boot
+ firmware.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ maximum: 0xfff
+
+ fsl,rtic-region:
+ description:
+ Specifies the HW address (36 bit address) for this region
+ followed by the length of the HW partition to be checked;
+ the address is represented as a 64 bit quantity followed
+ by a 32 bit length.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+
+required:
+ - compatible
+ - reg
+ - ranges
+
+additionalProperties: false
+
+examples:
+ - |
+ crypto@300000 {
+ compatible = "fsl,sec-v4.0";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x300000 0x10000>;
+ ranges = <0 0x300000 0x10000>;
+ interrupts = <92 2>;
+
+ jr@1000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x1000 0x1000>;
+ interrupts = <88 2>;
+ };
+
+ jr@2000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x2000 0x1000>;
+ interrupts = <89 2>;
+ };
+
+ jr@3000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x3000 0x1000>;
+ interrupts = <90 2>;
+ };
+
+ jr@4000 {
+ compatible = "fsl,sec-v4.0-job-ring";
+ reg = <0x4000 0x1000>;
+ interrupts = <91 2>;
+ };
+
+ rtic@6000 {
+ compatible = "fsl,sec-v4.0-rtic";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ reg = <0x6000 0x100>;
+ ranges = <0x0 0x6100 0xe00>;
+
+ rtic-a@0 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x00 0x20>, <0x100 0x80>;
+ };
+
+ rtic-b@20 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x20 0x20>, <0x200 0x80>;
+ };
+
+ rtic-c@40 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x40 0x20>, <0x300 0x80>;
+ };
+
+ rtic-d@60 {
+ compatible = "fsl,sec-v4.0-rtic-memory";
+ reg = <0x60 0x20>, <0x500 0x80>;
+ };
+ };
+ };
+...
diff --git a/Bindings/crypto/fsl-sec4.txt b/Bindings/crypto/fsl-sec4.txt
deleted file mode 100644
index 8f359f4..0000000
--- a/Bindings/crypto/fsl-sec4.txt
+++ /dev/null
@@ -1,553 +0,0 @@
-=====================================================================
-SEC 4 Device Tree Binding
-Copyright (C) 2008-2011 Freescale Semiconductor Inc.
-
- CONTENTS
- -Overview
- -SEC 4 Node
- -Job Ring Node
- -Run Time Integrity Check (RTIC) Node
- -Run Time Integrity Check (RTIC) Memory Node
- -Secure Non-Volatile Storage (SNVS) Node
- -Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
- -Full Example
-
-NOTE: the SEC 4 is also known as Freescale's Cryptographic Accelerator
-Accelerator and Assurance Module (CAAM).
-
-=====================================================================
-Overview
-
-DESCRIPTION
-
-SEC 4 h/w can process requests from 2 types of sources.
-1. DPAA Queue Interface (HW interface between Queue Manager & SEC 4).
-2. Job Rings (HW interface between cores & SEC 4 registers).
-
-High Speed Data Path Configuration:
-
-HW interface between QM & SEC 4 and also BM & SEC 4, on DPAA-enabled parts
-such as the P4080. The number of simultaneous dequeues the QI can make is
-equal to the number of Descriptor Controller (DECO) engines in a particular
-SEC version. E.g., the SEC 4.0 in the P4080 has 5 DECOs and can thus
-dequeue from 5 subportals simultaneously.
-
-Job Ring Data Path Configuration:
-
-Each JR is located on a separate 4k page, they may (or may not) be made visible
-in the memory partition devoted to a particular core. The P4080 has 4 JRs, so
-up to 4 JRs can be configured; and all 4 JRs process requests in parallel.
-
-=====================================================================
-SEC 4 Node
-
-Description
-
- Node defines the base address of the SEC 4 block.
- This block specifies the address range of all global
- configuration registers for the SEC 4 block. It
- also receives interrupts from the Run Time Integrity Check
- (RTIC) function within the SEC 4 block.
-
-PROPERTIES
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0"
-
- - fsl,sec-era
- Usage: optional
- Value type: <u32>
- Definition: A standard property. Define the 'ERA' of the SEC
- device.
-
- - #address-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing physical addresses in child nodes.
-
- - #size-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing the size of physical addresses in
- child nodes.
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical
- address and length of the SEC4 configuration registers.
- registers
-
- - ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- range of the SEC 4.0 register space (-SNVS not included). A
- triplet that includes the child address, parent address, &
- length.
-
- - interrupts
- Usage: required
- Value type: <prop_encoded-array>
- Definition: Specifies the interrupts generated by this
- device. The value of the interrupts property
- consists of one interrupt specifier. The format
- of the specifier is defined by the binding document
- describing the node's interrupt parent.
-
- - clocks
- Usage: required if SEC 4.0 requires explicit enablement of clocks
- Value type: <prop_encoded-array>
- Definition: A list of phandle and clock specifier pairs describing
- the clocks required for enabling and disabling SEC 4.0.
-
- - clock-names
- Usage: required if SEC 4.0 requires explicit enablement of clocks
- Value type: <string>
- Definition: A list of clock name strings in the same order as the
- clocks property.
-
- Note: All other standard properties (see the Devicetree Specification)
- are allowed but are optional.
-
-
-EXAMPLE
-
-iMX6QDL/SX requires four clocks
-
- crypto@300000 {
- compatible = "fsl,sec-v4.0";
- fsl,sec-era = <2>;
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x300000 0x10000>;
- ranges = <0 0x300000 0x10000>;
- interrupt-parent = <&mpic>;
- interrupts = <92 2>;
- clocks = <&clks IMX6QDL_CLK_CAAM_MEM>,
- <&clks IMX6QDL_CLK_CAAM_ACLK>,
- <&clks IMX6QDL_CLK_CAAM_IPG>,
- <&clks IMX6QDL_CLK_EIM_SLOW>;
- clock-names = "mem", "aclk", "ipg", "emi_slow";
- };
-
-
-iMX6UL does only require three clocks
-
- crypto: crypto@2140000 {
- compatible = "fsl,sec-v4.0";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x2140000 0x3c000>;
- ranges = <0 0x2140000 0x3c000>;
- interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
-
- clocks = <&clks IMX6UL_CLK_CAAM_MEM>,
- <&clks IMX6UL_CLK_CAAM_ACLK>,
- <&clks IMX6UL_CLK_CAAM_IPG>;
- clock-names = "mem", "aclk", "ipg";
- };
-
-=====================================================================
-Job Ring (JR) Node
-
- Child of the crypto node defines data processing interface to SEC 4
- across the peripheral bus for purposes of processing
- cryptographic descriptors. The specified address
- range can be made visible to one (or more) cores.
- The interrupt defined for this node is controlled within
- the address range of this node.
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0-job-ring"
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: Specifies a two JR parameters: an offset from
- the parent physical address and the length the JR registers.
-
- - fsl,liodn
- Usage: optional-but-recommended
- Value type: <prop-encoded-array>
- Definition:
- Specifies the LIODN to be used in conjunction with
- the ppid-to-liodn table that specifies the PPID to LIODN mapping.
- Needed if the PAMU is used. Value is a 12 bit value
- where value is a LIODN ID for this JR. This property is
- normally set by boot firmware.
-
- - interrupts
- Usage: required
- Value type: <prop_encoded-array>
- Definition: Specifies the interrupts generated by this
- device. The value of the interrupts property
- consists of one interrupt specifier. The format
- of the specifier is defined by the binding document
- describing the node's interrupt parent.
-
-EXAMPLE
- jr@1000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x1000 0x1000>;
- fsl,liodn = <0x081>;
- interrupt-parent = <&mpic>;
- interrupts = <88 2>;
- };
-
-
-=====================================================================
-Run Time Integrity Check (RTIC) Node
-
- Child node of the crypto node. Defines a register space that
- contains up to 5 sets of addresses and their lengths (sizes) that
- will be checked at run time. After an initial hash result is
- calculated, these addresses are checked by HW to monitor any
- change. If any memory is modified, a Security Violation is
- triggered (see SNVS definition).
-
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0-rtic".
-
- - #address-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing physical addresses in child nodes. Must
- have a value of 1.
-
- - #size-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing the size of physical addresses in
- child nodes. Must have a value of 1.
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies a two parameters:
- an offset from the parent physical address and the length
- the SEC4 registers.
-
- - ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- range of the SEC 4 register space (-SNVS not included). A
- triplet that includes the child address, parent address, &
- length.
-
-EXAMPLE
- rtic@6000 {
- compatible = "fsl,sec-v4.0-rtic";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x6000 0x100>;
- ranges = <0x0 0x6100 0xe00>;
- };
-
-=====================================================================
-Run Time Integrity Check (RTIC) Memory Node
- A child node that defines individual RTIC memory regions that are used to
- perform run-time integrity check of memory areas that should not modified.
- The node defines a register that contains the memory address &
- length (combined) and a second register that contains the hash result
- in big endian format.
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0-rtic-memory".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies two parameters:
- an offset from the parent physical address and the length:
-
- 1. The location of the RTIC memory address & length registers.
- 2. The location RTIC hash result.
-
- - fsl,rtic-region
- Usage: optional-but-recommended
- Value type: <prop-encoded-array>
- Definition:
- Specifies the HW address (36 bit address) for this region
- followed by the length of the HW partition to be checked;
- the address is represented as a 64 bit quantity followed
- by a 32 bit length.
-
- - fsl,liodn
- Usage: optional-but-recommended
- Value type: <prop-encoded-array>
- Definition:
- Specifies the LIODN to be used in conjunction with
- the ppid-to-liodn table that specifies the PPID to LIODN
- mapping. Needed if the PAMU is used. Value is a 12 bit value
- where value is a LIODN ID for this RTIC memory region. This
- property is normally set by boot firmware.
-
-EXAMPLE
- rtic-a@0 {
- compatible = "fsl,sec-v4.0-rtic-memory";
- reg = <0x00 0x20 0x100 0x80>;
- fsl,liodn = <0x03c>;
- fsl,rtic-region = <0x12345678 0x12345678 0x12345678>;
- };
-
-=====================================================================
-Secure Non-Volatile Storage (SNVS) Node
-
- Node defines address range and the associated
- interrupt for the SNVS function. This function
- monitors security state information & reports
- security violations. This also included rtc,
- system power off and ON/OFF key.
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0-mon" and "syscon".
-
- - reg
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical
- address and length of the SEC4 configuration
- registers.
-
- - #address-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing physical addresses in child nodes. Must
- have a value of 1.
-
- - #size-cells
- Usage: required
- Value type: <u32>
- Definition: A standard property. Defines the number of cells
- for representing the size of physical addresses in
- child nodes. Must have a value of 1.
-
- - ranges
- Usage: required
- Value type: <prop-encoded-array>
- Definition: A standard property. Specifies the physical address
- range of the SNVS register space. A triplet that includes
- the child address, parent address, & length.
-
- - interrupts
- Usage: optional
- Value type: <prop_encoded-array>
- Definition: Specifies the interrupts generated by this
- device. The value of the interrupts property
- consists of one interrupt specifier. The format
- of the specifier is defined by the binding document
- describing the node's interrupt parent.
-
-EXAMPLE
- sec_mon@314000 {
- compatible = "fsl,sec-v4.0-mon", "syscon";
- reg = <0x314000 0x1000>;
- ranges = <0 0x314000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <93 2>;
- };
-
-=====================================================================
-Secure Non-Volatile Storage (SNVS) Low Power (LP) RTC Node
-
- A SNVS child node that defines SNVS LP RTC.
-
- - compatible
- Usage: required
- Value type: <string>
- Definition: Must include "fsl,sec-v4.0-mon-rtc-lp".
-
- - interrupts
- Usage: required
- Value type: <prop_encoded-array>
- Definition: Specifies the interrupts generated by this
- device. The value of the interrupts property
- consists of one interrupt specifier. The format
- of the specifier is defined by the binding document
- describing the node's interrupt parent.
-
- - regmap
- Usage: required
- Value type: <phandle>
- Definition: this is phandle to the register map node.
-
- - offset
- Usage: option
- value type: <u32>
- Definition: LP register offset. default it is 0x34.
-
- - clocks
- Usage: optional, required if SNVS LP RTC requires explicit
- enablement of clocks
- Value type: <prop_encoded-array>
- Definition: a clock specifier describing the clock required for
- enabling and disabling SNVS LP RTC.
-
- - clock-names
- Usage: optional, required if SNVS LP RTC requires explicit
- enablement of clocks
- Value type: <string>
- Definition: clock name string should be "snvs-rtc".
-
-EXAMPLE
- sec_mon_rtc_lp@1 {
- compatible = "fsl,sec-v4.0-mon-rtc-lp";
- interrupts = <93 2>;
- regmap = <&snvs>;
- offset = <0x34>;
- clocks = <&clks IMX7D_SNVS_CLK>;
- clock-names = "snvs-rtc";
- };
-
-=====================================================================
-System ON/OFF key driver
-
- The snvs-pwrkey is designed to enable POWER key function which controlled
- by SNVS ONOFF, the driver can report the status of POWER key and wakeup
- system if pressed after system suspend.
-
- - compatible:
- Usage: required
- Value type: <string>
- Definition: Mush include "fsl,sec-v4.0-pwrkey".
-
- - interrupts:
- Usage: required
- Value type: <prop_encoded-array>
- Definition: The SNVS ON/OFF interrupt number to the CPU(s).
-
- - linux,keycode:
- Usage: option
- Value type: <int>
- Definition: Keycode to emit, KEY_POWER by default.
-
- - wakeup-source:
- Usage: option
- Value type: <boo>
- Definition: Button can wake-up the system.
-
- - regmap:
- Usage: required:
- Value type: <phandle>
- Definition: this is phandle to the register map node.
-
-EXAMPLE:
- snvs-pwrkey@020cc000 {
- compatible = "fsl,sec-v4.0-pwrkey";
- regmap = <&snvs>;
- interrupts = <0 4 0x4>
- linux,keycode = <116>; /* KEY_POWER */
- wakeup-source;
- };
-
-=====================================================================
-FULL EXAMPLE
-
- crypto: crypto@300000 {
- compatible = "fsl,sec-v4.0";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x300000 0x10000>;
- ranges = <0 0x300000 0x10000>;
- interrupt-parent = <&mpic>;
- interrupts = <92 2>;
-
- sec_jr0: jr@1000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x1000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <88 2>;
- };
-
- sec_jr1: jr@2000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x2000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <89 2>;
- };
-
- sec_jr2: jr@3000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x3000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <90 2>;
- };
-
- sec_jr3: jr@4000 {
- compatible = "fsl,sec-v4.0-job-ring";
- reg = <0x4000 0x1000>;
- interrupt-parent = <&mpic>;
- interrupts = <91 2>;
- };
-
- rtic@6000 {
- compatible = "fsl,sec-v4.0-rtic";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x6000 0x100>;
- ranges = <0x0 0x6100 0xe00>;
-
- rtic_a: rtic-a@0 {
- compatible = "fsl,sec-v4.0-rtic-memory";
- reg = <0x00 0x20 0x100 0x80>;
- };
-
- rtic_b: rtic-b@20 {
- compatible = "fsl,sec-v4.0-rtic-memory";
- reg = <0x20 0x20 0x200 0x80>;
- };
-
- rtic_c: rtic-c@40 {
- compatible = "fsl,sec-v4.0-rtic-memory";
- reg = <0x40 0x20 0x300 0x80>;
- };
-
- rtic_d: rtic-d@60 {
- compatible = "fsl,sec-v4.0-rtic-memory";
- reg = <0x60 0x20 0x500 0x80>;
- };
- };
- };
-
- sec_mon: sec_mon@314000 {
- compatible = "fsl,sec-v4.0-mon";
- reg = <0x314000 0x1000>;
- ranges = <0 0x314000 0x1000>;
-
- sec_mon_rtc_lp@34 {
- compatible = "fsl,sec-v4.0-mon-rtc-lp";
- regmap = <&sec_mon>;
- offset = <0x34>;
- interrupts = <93 2>;
- clocks = <&clks IMX7D_SNVS_CLK>;
- clock-names = "snvs-rtc";
- };
-
- snvs-pwrkey@020cc000 {
- compatible = "fsl,sec-v4.0-pwrkey";
- regmap = <&sec_mon>;
- interrupts = <0 4 0x4>;
- linux,keycode = <116>; /* KEY_POWER */
- wakeup-source;
- };
- };
-
-=====================================================================
diff --git a/Bindings/crypto/qcom,inline-crypto-engine.yaml b/Bindings/crypto/qcom,inline-crypto-engine.yaml
new file mode 100644
index 0000000..92e1d76
--- /dev/null
+++ b/Bindings/crypto/qcom,inline-crypto-engine.yaml
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
+
+maintainers:
+ - Bjorn Andersson <andersson@kernel.org>
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sm8550-inline-crypto-engine
+ - const: qcom,inline-crypto-engine
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,sm8550-gcc.h>
+
+ crypto@1d88000 {
+ compatible = "qcom,sm8550-inline-crypto-engine",
+ "qcom,inline-crypto-engine";
+ reg = <0x01d88000 0x8000>;
+ clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>;
+ };
+...
diff --git a/Bindings/crypto/qcom-qce.txt b/Bindings/crypto/qcom-qce.txt
deleted file mode 100644
index fdd53b1..0000000
--- a/Bindings/crypto/qcom-qce.txt
+++ /dev/null
@@ -1,25 +0,0 @@
-Qualcomm crypto engine driver
-
-Required properties:
-
-- compatible : should be "qcom,crypto-v5.1"
-- reg : specifies base physical address and size of the registers map
-- clocks : phandle to clock-controller plus clock-specifier pair
-- clock-names : "iface" clocks register interface
- "bus" clocks data transfer interface
- "core" clocks rest of the crypto block
-- dmas : DMA specifiers for tx and rx dma channels. For more see
- Documentation/devicetree/bindings/dma/dma.txt
-- dma-names : DMA request names should be "rx" and "tx"
-
-Example:
- crypto@fd45a000 {
- compatible = "qcom,crypto-v5.1";
- reg = <0xfd45a000 0x6000>;
- clocks = <&gcc GCC_CE2_AHB_CLK>,
- <&gcc GCC_CE2_AXI_CLK>,
- <&gcc GCC_CE2_CLK>;
- clock-names = "iface", "bus", "core";
- dmas = <&cryptobam 2>, <&cryptobam 3>;
- dma-names = "rx", "tx";
- };
diff --git a/Bindings/crypto/qcom-qce.yaml b/Bindings/crypto/qcom-qce.yaml
new file mode 100644
index 0000000..e375bd9
--- /dev/null
+++ b/Bindings/crypto/qcom-qce.yaml
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/crypto/qcom-qce.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm crypto engine driver
+
+maintainers:
+ - Bhupesh Sharma <bhupesh.sharma@linaro.org>
+
+description:
+ This document defines the binding for the QCE crypto
+ controller found on Qualcomm parts.
+
+properties:
+ compatible:
+ oneOf:
+ - const: qcom,crypto-v5.1
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+
+ - const: qcom,crypto-v5.4
+ deprecated: true
+ description: Kept only for ABI backward compatibility
+
+ - items:
+ - enum:
+ - qcom,ipq6018-qce
+ - qcom,ipq8074-qce
+ - qcom,msm8996-qce
+ - qcom,sdm845-qce
+ - const: qcom,ipq4019-qce
+ - const: qcom,qce
+
+ - items:
+ - enum:
+ - qcom,sm8250-qce
+ - qcom,sm8350-qce
+ - qcom,sm8450-qce
+ - qcom,sm8550-qce
+ - const: qcom,sm8150-qce
+ - const: qcom,qce
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: iface clocks register interface.
+ - description: bus clocks data transfer interface.
+ - description: core clocks rest of the crypto block.
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+ - const: core
+
+ iommus:
+ minItems: 1
+ maxItems: 8
+ description:
+ phandle to apps_smmu node with sid mask.
+
+ interconnects:
+ maxItems: 1
+ description:
+ Interconnect path between qce crypto and main memory.
+
+ interconnect-names:
+ const: memory
+
+ dmas:
+ items:
+ - description: DMA specifiers for rx dma channel.
+ - description: DMA specifiers for tx dma channel.
+
+ dma-names:
+ items:
+ - const: rx
+ - const: tx
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,crypto-v5.1
+ - qcom,crypto-v5.4
+ - qcom,ipq4019-qce
+
+ then:
+ required:
+ - clocks
+ - clock-names
+
+required:
+ - compatible
+ - reg
+ - dmas
+ - dma-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-apq8084.h>
+ crypto-engine@fd45a000 {
+ compatible = "qcom,ipq6018-qce", "qcom,ipq4019-qce", "qcom,qce";
+ reg = <0xfd45a000 0x6000>;
+ clocks = <&gcc GCC_CE2_AHB_CLK>,
+ <&gcc GCC_CE2_AXI_CLK>,
+ <&gcc GCC_CE2_CLK>;
+ clock-names = "iface", "bus", "core";
+ dmas = <&cryptobam 2>, <&cryptobam 3>;
+ dma-names = "rx", "tx";
+ iommus = <&apps_smmu 0x584 0x0011>,
+ <&apps_smmu 0x586 0x0011>,
+ <&apps_smmu 0x594 0x0011>,
+ <&apps_smmu 0x596 0x0011>;
+ };
diff --git a/Bindings/crypto/ti,sa2ul.yaml b/Bindings/crypto/ti,sa2ul.yaml
index 0c15fef..77ec8bc 100644
--- a/Bindings/crypto/ti,sa2ul.yaml
+++ b/Bindings/crypto/ti,sa2ul.yaml
@@ -26,8 +26,8 @@
dmas:
items:
- description: TX DMA Channel
- - description: RX DMA Channel #1
- - description: RX DMA Channel #2
+ - description: 'RX DMA Channel #1'
+ - description: 'RX DMA Channel #2'
dma-names:
items:
diff --git a/Bindings/display/amlogic,meson-dw-hdmi.yaml b/Bindings/display/amlogic,meson-dw-hdmi.yaml
index 74cefdf..0c85894 100644
--- a/Bindings/display/amlogic,meson-dw-hdmi.yaml
+++ b/Bindings/display/amlogic,meson-dw-hdmi.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/amlogic,meson-dw-hdmi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic specific extensions to the Synopsys Designware HDMI Controller
diff --git a/Bindings/display/amlogic,meson-vpu.yaml b/Bindings/display/amlogic,meson-vpu.yaml
index 6655a93..0c72120 100644
--- a/Bindings/display/amlogic,meson-vpu.yaml
+++ b/Bindings/display/amlogic,meson-vpu.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/amlogic,meson-vpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Display Controller
diff --git a/Bindings/display/bridge/analogix,anx7625.yaml b/Bindings/display/bridge/analogix,anx7625.yaml
index 4590186..a1ed100 100644
--- a/Bindings/display/bridge/analogix,anx7625.yaml
+++ b/Bindings/display/bridge/analogix,anx7625.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Analogix Semiconductor, Inc.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/bridge/analogix,anx7625.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Analogix ANX7625 SlimPort (4K Mobile HD Transmitter)
@@ -16,8 +16,7 @@
properties:
compatible:
- items:
- - const: analogix,anx7625
+ const: analogix,anx7625
reg:
maxItems: 1
@@ -134,7 +133,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/anx6345.yaml b/Bindings/display/bridge/anx6345.yaml
index 9bf2cbc..514f588 100644
--- a/Bindings/display/bridge/anx6345.yaml
+++ b/Bindings/display/bridge/anx6345.yaml
@@ -61,7 +61,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/cdns,mhdp8546.yaml b/Bindings/display/bridge/cdns,mhdp8546.yaml
index b2e8bc6..c2b3694 100644
--- a/Bindings/display/bridge/cdns,mhdp8546.yaml
+++ b/Bindings/display/bridge/cdns,mhdp8546.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/bridge/cdns,mhdp8546.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence MHDP8546 bridge
diff --git a/Bindings/display/bridge/lontium,lt8912b.yaml b/Bindings/display/bridge/lontium,lt8912b.yaml
index 674891e..f201ae4 100644
--- a/Bindings/display/bridge/lontium,lt8912b.yaml
+++ b/Bindings/display/bridge/lontium,lt8912b.yaml
@@ -67,7 +67,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c4 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/nxp,ptn3460.yaml b/Bindings/display/bridge/nxp,ptn3460.yaml
index 107dd13..70ec709 100644
--- a/Bindings/display/bridge/nxp,ptn3460.yaml
+++ b/Bindings/display/bridge/nxp,ptn3460.yaml
@@ -18,7 +18,7 @@
maxItems: 1
edid-emulation:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
The EDID emulation entry to use
Value Resolution Description
@@ -71,7 +71,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/parade,ps8622.yaml b/Bindings/display/bridge/parade,ps8622.yaml
new file mode 100644
index 0000000..e6397ac
--- /dev/null
+++ b/Bindings/display/bridge/parade,ps8622.yaml
@@ -0,0 +1,115 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/parade,ps8622.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+properties:
+ compatible:
+ enum:
+ - parade,ps8622
+ - parade,ps8625
+
+ reg:
+ maxItems: 1
+
+ lane-count:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ enum: [1, 2]
+ description: Number of DP lanes to use.
+
+ use-external-pwm:
+ type: boolean
+ description: Backlight will be controlled by an external PWM.
+
+ reset-gpios:
+ maxItems: 1
+ description: GPIO connected to RST_ pin.
+
+ sleep-gpios:
+ maxItems: 1
+ description: GPIO connected to PD_ pin.
+
+ vdd12-supply: true
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for LVDS output.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description: Video port for DisplayPort input.
+
+ required:
+ - port@0
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - sleep-gpios
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: parade,ps8622
+ then:
+ properties:
+ lane-count:
+ const: 1
+ else:
+ properties:
+ lane-count:
+ const: 2
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ lvds-bridge@48 {
+ compatible = "parade,ps8625";
+ reg = <0x48>;
+ sleep-gpios = <&gpx3 5 GPIO_ACTIVE_HIGH>;
+ reset-gpios = <&gpy7 7 GPIO_ACTIVE_HIGH>;
+ lane-count = <2>;
+ use-external-pwm;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ bridge_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ bridge_in: endpoint {
+ remote-endpoint = <&dp_out>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/bridge/ps8622.txt b/Bindings/display/bridge/ps8622.txt
deleted file mode 100644
index c989c38..0000000
--- a/Bindings/display/bridge/ps8622.txt
+++ /dev/null
@@ -1,31 +0,0 @@
-ps8622-bridge bindings
-
-Required properties:
- - compatible: "parade,ps8622" or "parade,ps8625"
- - reg: first i2c address of the bridge
- - sleep-gpios: OF device-tree gpio specification for PD_ pin.
- - reset-gpios: OF device-tree gpio specification for RST_ pin.
-
-Optional properties:
- - lane-count: number of DP lanes to use
- - use-external-pwm: backlight will be controlled by an external PWM
- - video interfaces: Device node can contain video interface port
- nodes for panel according to [1].
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
- lvds-bridge@48 {
- compatible = "parade,ps8622";
- reg = <0x48>;
- sleep-gpios = <&gpc3 6 1 0 0>;
- reset-gpios = <&gpc3 1 1 0 0>;
- lane-count = <1>;
- ports {
- port@0 {
- bridge_out: endpoint {
- remote-endpoint = <&panel_in>;
- };
- };
- };
- };
diff --git a/Bindings/display/bridge/ps8640.yaml b/Bindings/display/bridge/ps8640.yaml
index 28811af..5856450 100644
--- a/Bindings/display/bridge/ps8640.yaml
+++ b/Bindings/display/bridge/ps8640.yaml
@@ -73,7 +73,7 @@
examples:
- |
#include <dt-bindings/gpio/gpio.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/samsung,mipi-dsim.yaml b/Bindings/display/bridge/samsung,mipi-dsim.yaml
new file mode 100644
index 0000000..e841659
--- /dev/null
+++ b/Bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -0,0 +1,255 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung MIPI DSIM bridge controller
+
+maintainers:
+ - Inki Dae <inki.dae@samsung.com>
+ - Jagan Teki <jagan@amarulasolutions.com>
+ - Marek Szyprowski <m.szyprowski@samsung.com>
+
+description: |
+ Samsung MIPI DSIM bridge controller can be found it on Exynos
+ and i.MX8M Mini/Nano/Plus SoC's.
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - samsung,exynos3250-mipi-dsi
+ - samsung,exynos4210-mipi-dsi
+ - samsung,exynos5410-mipi-dsi
+ - samsung,exynos5422-mipi-dsi
+ - samsung,exynos5433-mipi-dsi
+ - fsl,imx8mm-mipi-dsim
+ - fsl,imx8mp-mipi-dsim
+ - items:
+ - const: fsl,imx8mn-mipi-dsim
+ - const: fsl,imx8mm-mipi-dsim
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
+ clocks:
+ minItems: 2
+ maxItems: 5
+
+ clock-names:
+ minItems: 2
+ maxItems: 5
+
+ samsung,phy-type:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description: phandle to the samsung phy-type
+
+ power-domains:
+ maxItems: 1
+
+ samsung,power-domain:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description: phandle to the associated samsung power domain
+
+ vddcore-supply:
+ description: MIPI DSIM Core voltage supply (e.g. 1.1V)
+
+ vddio-supply:
+ description: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
+
+ samsung,burst-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM high speed burst mode frequency.
+
+ samsung,esc-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM escape mode frequency.
+
+ samsung,pll-clock-frequency:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ DSIM oscillator clock frequency.
+
+ phys:
+ maxItems: 1
+
+ phy-names:
+ const: dsim
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Input port node to receive pixel data from the
+ display controller. Exactly one endpoint must be
+ specified.
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ DSI output port node to the panel or the next bridge
+ in the chain.
+
+required:
+ - clock-names
+ - clocks
+ - compatible
+ - interrupts
+ - reg
+ - samsung,burst-clock-frequency
+ - samsung,esc-clock-frequency
+ - samsung,pll-clock-frequency
+
+allOf:
+ - $ref: ../dsi-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5433-mipi-dsi
+
+ then:
+ properties:
+ clocks:
+ minItems: 5
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: phyclk_mipidphy0_bitclkdiv8
+ - const: phyclk_mipidphy0_rxclkesc0
+ - const: sclk_rgb_vclk_to_dsim0
+ - const: sclk_mipi
+
+ ports:
+ required:
+ - port@0
+
+ required:
+ - ports
+ - vddcore-supply
+ - vddio-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos5410-mipi-dsi
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: pll_clk
+
+ required:
+ - vddcore-supply
+ - vddio-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos4210-mipi-dsi
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: sclk_mipi
+
+ required:
+ - vddcore-supply
+ - vddio-supply
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: samsung,exynos3250-mipi-dsi
+
+ then:
+ properties:
+ clocks:
+ minItems: 2
+
+ clock-names:
+ items:
+ - const: bus_clk
+ - const: pll_clk
+
+ required:
+ - vddcore-supply
+ - vddio-supply
+ - samsung,phy-type
+
+additionalProperties:
+ type: object
+
+examples:
+ - |
+ #include <dt-bindings/clock/exynos5433.h>
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ dsi@13900000 {
+ compatible = "samsung,exynos5433-mipi-dsi";
+ reg = <0x13900000 0xC0>;
+ interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
+ phys = <&mipi_phy 1>;
+ phy-names = "dsim";
+ clocks = <&cmu_disp CLK_PCLK_DSIM0>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8>,
+ <&cmu_disp CLK_PHYCLK_MIPIDPHY0_RXCLKESC0>,
+ <&cmu_disp CLK_SCLK_RGB_VCLK_TO_DSIM0>,
+ <&cmu_disp CLK_SCLK_DSIM0>;
+ clock-names = "bus_clk",
+ "phyclk_mipidphy0_bitclkdiv8",
+ "phyclk_mipidphy0_rxclkesc0",
+ "sclk_rgb_vclk_to_dsim0",
+ "sclk_mipi";
+ power-domains = <&pd_disp>;
+ vddcore-supply = <&ldo6_reg>;
+ vddio-supply = <&ldo7_reg>;
+ samsung,burst-clock-frequency = <512000000>;
+ samsung,esc-clock-frequency = <16000000>;
+ samsung,pll-clock-frequency = <24000000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&te_irq>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ dsi_to_mic: endpoint {
+ remote-endpoint = <&mic_to_dsi>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/bridge/sil,sii9234.yaml b/Bindings/display/bridge/sil,sii9234.yaml
index f88ddfe..176181d 100644
--- a/Bindings/display/bridge/sil,sii9234.yaml
+++ b/Bindings/display/bridge/sil,sii9234.yaml
@@ -71,7 +71,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/ti,dlpc3433.yaml b/Bindings/display/bridge/ti,dlpc3433.yaml
index 542193d..d3f84d2 100644
--- a/Bindings/display/bridge/ti,dlpc3433.yaml
+++ b/Bindings/display/bridge/ti,dlpc3433.yaml
@@ -83,7 +83,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/ti,sn65dsi86.yaml b/Bindings/display/bridge/ti,sn65dsi86.yaml
index 9115644..6ec6d28 100644
--- a/Bindings/display/bridge/ti,sn65dsi86.yaml
+++ b/Bindings/display/bridge/ti,sn65dsi86.yaml
@@ -90,7 +90,7 @@
properties:
endpoint:
- $ref: /schemas/graph.yaml#/$defs/endpoint-base
+ $ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
properties:
@@ -106,7 +106,6 @@
description:
If you have 1 logical lane the bridge supports routing
to either port 0 or port 1. Port 0 is suggested.
- See ../../media/video-interface.txt for details.
- minItems: 2
maxItems: 2
@@ -118,7 +117,6 @@
description:
If you have 2 logical lanes the bridge supports
reordering but only on physical ports 0 and 1.
- See ../../media/video-interface.txt for details.
- minItems: 4
maxItems: 4
@@ -132,7 +130,6 @@
description:
If you have 4 logical lanes the bridge supports
reordering in any way.
- See ../../media/video-interface.txt for details.
lane-polarities:
minItems: 1
@@ -141,7 +138,6 @@
enum:
- 0
- 1
- description: See ../../media/video-interface.txt
dependencies:
lane-polarities: [data-lanes]
diff --git a/Bindings/display/bridge/toshiba,tc358762.yaml b/Bindings/display/bridge/toshiba,tc358762.yaml
index a412a1d..81ca3cb 100644
--- a/Bindings/display/bridge/toshiba,tc358762.yaml
+++ b/Bindings/display/bridge/toshiba,tc358762.yaml
@@ -51,7 +51,7 @@
examples:
- |
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/bridge/toshiba,tc358764.txt b/Bindings/display/bridge/toshiba,tc358764.txt
deleted file mode 100644
index 8f9abf2..0000000
--- a/Bindings/display/bridge/toshiba,tc358764.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-TC358764 MIPI-DSI to LVDS panel bridge
-
-Required properties:
- - compatible: "toshiba,tc358764"
- - reg: the virtual channel number of a DSI peripheral
- - vddc-supply: core voltage supply, 1.2V
- - vddio-supply: I/O voltage supply, 1.8V or 3.3V
- - vddlvds-supply: LVDS1/2 voltage supply, 3.3V
- - reset-gpios: a GPIO spec for the reset pin
-
-The device node can contain following 'port' child nodes,
-according to the OF graph bindings defined in [1]:
- 0: DSI Input, not required, if the bridge is DSI controlled
- 1: LVDS Output, mandatory
-
-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-
- bridge@0 {
- reg = <0>;
- compatible = "toshiba,tc358764";
- vddc-supply = <&vcc_1v2_reg>;
- vddio-supply = <&vcc_1v8_reg>;
- vddlvds-supply = <&vcc_3v3_reg>;
- reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
- #address-cells = <1>;
- #size-cells = <0>;
- port@1 {
- reg = <1>;
- lvds_ep: endpoint {
- remote-endpoint = <&panel_ep>;
- };
- };
- };
diff --git a/Bindings/display/bridge/toshiba,tc358764.yaml b/Bindings/display/bridge/toshiba,tc358764.yaml
new file mode 100644
index 0000000..8666074
--- /dev/null
+++ b/Bindings/display/bridge/toshiba,tc358764.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/toshiba,tc358764.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Toshiba TC358764 MIPI-DSI to LVDS bridge
+
+maintainers:
+ - Andrzej Hajda <andrzej.hajda@intel.com>
+
+properties:
+ compatible:
+ const: toshiba,tc358764
+
+ reg:
+ description: Virtual channel number of a DSI peripheral
+ maxItems: 1
+
+ reset-gpios:
+ maxItems: 1
+
+ vddc-supply:
+ description: Core voltage supply, 1.2V
+
+ vddio-supply:
+ description: I/O voltage supply, 1.8V or 3.3V
+
+ vddlvds-supply:
+ description: LVDS1/2 voltage supply, 3.3V
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+
+ properties:
+ port@0:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Video port for MIPI DSI input, if the bridge DSI controlled
+
+ port@1:
+ $ref: /schemas/graph.yaml#/properties/port
+ description:
+ Video port for LVDS output (panel or connector).
+
+ required:
+ - port@1
+
+required:
+ - compatible
+ - reg
+ - reset-gpios
+ - vddc-supply
+ - vddio-supply
+ - vddlvds-supply
+ - ports
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bridge@0 {
+ compatible = "toshiba,tc358764";
+ reg = <0>;
+
+ reset-gpios = <&gpd1 6 GPIO_ACTIVE_LOW>;
+ vddc-supply = <&vcc_1v2_reg>;
+ vddio-supply = <&vcc_1v8_reg>;
+ vddlvds-supply = <&vcc_3v3_reg>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ lvds_ep: endpoint {
+ remote-endpoint = <&panel_ep>;
+ };
+ };
+ };
+ };
+ };
diff --git a/Bindings/display/bridge/toshiba,tc358767.yaml b/Bindings/display/bridge/toshiba,tc358767.yaml
index 1409278..e1494b5 100644
--- a/Bindings/display/bridge/toshiba,tc358767.yaml
+++ b/Bindings/display/bridge/toshiba,tc358767.yaml
@@ -23,7 +23,7 @@
i2c address of the bridge, 0x68 or 0x0f, depending on bootstrap pins
clock-names:
- const: "ref"
+ const: ref
clocks:
maxItems: 1
diff --git a/Bindings/display/bridge/toshiba,tc358768.yaml b/Bindings/display/bridge/toshiba,tc358768.yaml
index 0b6f5be..779d8c5 100644
--- a/Bindings/display/bridge/toshiba,tc358768.yaml
+++ b/Bindings/display/bridge/toshiba,tc358768.yaml
@@ -87,7 +87,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/dp-aux-bus.yaml b/Bindings/display/dp-aux-bus.yaml
index 5e4afe9..0ece7b0 100644
--- a/Bindings/display/dp-aux-bus.yaml
+++ b/Bindings/display/dp-aux-bus.yaml
@@ -26,7 +26,7 @@
properties:
$nodename:
- const: "aux-bus"
+ const: aux-bus
panel:
$ref: panel/panel-common.yaml#
diff --git a/Bindings/display/exynos/exynos_dsim.txt b/Bindings/display/exynos/exynos_dsim.txt
deleted file mode 100644
index be37778..0000000
--- a/Bindings/display/exynos/exynos_dsim.txt
+++ /dev/null
@@ -1,90 +0,0 @@
-Exynos MIPI DSI Master
-
-Required properties:
- - compatible: value should be one of the following
- "samsung,exynos3250-mipi-dsi" /* for Exynos3250/3472 SoCs */
- "samsung,exynos4210-mipi-dsi" /* for Exynos4 SoCs */
- "samsung,exynos5410-mipi-dsi" /* for Exynos5410/5420/5440 SoCs */
- "samsung,exynos5422-mipi-dsi" /* for Exynos5422/5800 SoCs */
- "samsung,exynos5433-mipi-dsi" /* for Exynos5433 SoCs */
- - reg: physical base address and length of the registers set for the device
- - interrupts: should contain DSI interrupt
- - clocks: list of clock specifiers, must contain an entry for each required
- entry in clock-names
- - clock-names: should include "bus_clk"and "sclk_mipi" entries
- the use of "pll_clk" is deprecated
- - phys: list of phy specifiers, must contain an entry for each required
- entry in phy-names
- - phy-names: should include "dsim" entry
- - vddcore-supply: MIPI DSIM Core voltage supply (e.g. 1.1V)
- - vddio-supply: MIPI DSIM I/O and PLL voltage supply (e.g. 1.8V)
- - samsung,pll-clock-frequency: specifies frequency of the oscillator clock
- - #address-cells, #size-cells: should be set respectively to <1> and <0>
- according to DSI host bindings (see MIPI DSI bindings [1])
- - samsung,burst-clock-frequency: specifies DSI frequency in high-speed burst
- mode
- - samsung,esc-clock-frequency: specifies DSI frequency in escape mode
-
-Optional properties:
- - power-domains: a phandle to DSIM power domain node
-
-Child nodes:
- Should contain DSI peripheral nodes (see MIPI DSI bindings [1]).
-
-Video interfaces:
- Device node can contain following video interface port nodes according to [2]:
- 0: RGB input,
- 1: DSI output
-
-[1]: Documentation/devicetree/bindings/display/mipi-dsi-bus.txt
-[2]: Documentation/devicetree/bindings/media/video-interfaces.txt
-
-Example:
-
- dsi@11c80000 {
- compatible = "samsung,exynos4210-mipi-dsi";
- reg = <0x11C80000 0x10000>;
- interrupts = <0 79 0>;
- clocks = <&clock 286>, <&clock 143>;
- clock-names = "bus_clk", "sclk_mipi";
- phys = <&mipi_phy 1>;
- phy-names = "dsim";
- vddcore-supply = <&vusb_reg>;
- vddio-supply = <&vmipi_reg>;
- power-domains = <&pd_lcd0>;
- #address-cells = <1>;
- #size-cells = <0>;
- samsung,pll-clock-frequency = <24000000>;
-
- panel@1 {
- reg = <0>;
- ...
- port {
- panel_ep: endpoint {
- remote-endpoint = <&dsi_ep>;
- };
- };
- };
-
- ports {
- #address-cells = <1>;
- #size-cells = <0>;
-
- port@0 {
- reg = <0>;
- decon_to_mic: endpoint {
- remote-endpoint = <&mic_to_decon>;
- };
- };
-
- port@1 {
- reg = <1>;
- dsi_ep: endpoint {
- reg = <0>;
- samsung,burst-clock-frequency = <500000000>;
- samsung,esc-clock-frequency = <20000000>;
- remote-endpoint = <&panel_ep>;
- };
- };
- };
- };
diff --git a/Bindings/display/imx/fsl,imx-lcdc.yaml b/Bindings/display/imx/fsl,imx-lcdc.yaml
index 35a8fff..c2b2962 100644
--- a/Bindings/display/imx/fsl,imx-lcdc.yaml
+++ b/Bindings/display/imx/fsl,imx-lcdc.yaml
@@ -21,6 +21,9 @@
- fsl,imx25-fb
- fsl,imx27-fb
- const: fsl,imx21-fb
+ - items:
+ - const: fsl,imx25-lcdc
+ - const: fsl,imx21-lcdc
clocks:
maxItems: 3
@@ -31,6 +34,9 @@
- const: ahb
- const: per
+ port:
+ $ref: /schemas/graph.yaml#/properties/port
+
display:
$ref: /schemas/types.yaml#/definitions/phandle
@@ -59,11 +65,35 @@
description:
LCDC Sharp Configuration Register value.
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - fsl,imx1-lcdc
+ - fsl,imx21-lcdc
+ then:
+ properties:
+ display: false
+ fsl,dmacr: false
+ fsl,lpccr: false
+ fsl,lscr1: false
+
+ required:
+ - port
+
+ else:
+ properties:
+ port: false
+
+ required:
+ - display
+
required:
- compatible
- clocks
- clock-names
- - display
- interrupts
- reg
@@ -71,6 +101,20 @@
examples:
- |
+ lcdc@53fbc000 {
+ compatible = "fsl,imx25-lcdc", "fsl,imx21-lcdc";
+ reg = <0x53fbc000 0x4000>;
+ interrupts = <39>;
+ clocks = <&clks 103>, <&clks 66>, <&clks 49>;
+ clock-names = "ipg", "ahb", "per";
+
+ port {
+ parallel_out: endpoint {
+ remote-endpoint = <&panel_in>;
+ };
+ };
+ };
+ - |
imxfb: fb@10021000 {
compatible = "fsl,imx21-fb";
interrupts = <61>;
diff --git a/Bindings/display/imx/nxp,imx8mq-dcss.yaml b/Bindings/display/imx/nxp,imx8mq-dcss.yaml
index 989ab31..4ae6328 100644
--- a/Bindings/display/imx/nxp,imx8mq-dcss.yaml
+++ b/Bindings/display/imx/nxp,imx8mq-dcss.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 NXP
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/imx/nxp,imx8mq-dcss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: iMX8MQ Display Controller Subsystem (DCSS)
diff --git a/Bindings/display/mediatek/mediatek,ccorr.yaml b/Bindings/display/mediatek/mediatek,ccorr.yaml
index b04820c..8c2a737 100644
--- a/Bindings/display/mediatek/mediatek,ccorr.yaml
+++ b/Bindings/display/mediatek/mediatek,ccorr.yaml
@@ -21,18 +21,14 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8183-disp-ccorr
- - items:
- - const: mediatek,mt8192-disp-ccorr
- - items:
- - enum:
- - mediatek,mt8188-disp-ccorr
- - mediatek,mt8195-disp-ccorr
- - const: mediatek,mt8192-disp-ccorr
+ - enum:
+ - mediatek,mt8183-disp-ccorr
+ - mediatek,mt8192-disp-ccorr
- items:
- enum:
- mediatek,mt8186-disp-ccorr
+ - mediatek,mt8188-disp-ccorr
+ - mediatek,mt8195-disp-ccorr
- const: mediatek,mt8192-disp-ccorr
reg:
diff --git a/Bindings/display/mediatek/mediatek,color.yaml b/Bindings/display/mediatek/mediatek,color.yaml
index 62306c8..d0ea77f 100644
--- a/Bindings/display/mediatek/mediatek,color.yaml
+++ b/Bindings/display/mediatek/mediatek,color.yaml
@@ -22,12 +22,10 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt2701-disp-color
- - items:
- - const: mediatek,mt8167-disp-color
- - items:
- - const: mediatek,mt8173-disp-color
+ - enum:
+ - mediatek,mt2701-disp-color
+ - mediatek,mt8167-disp-color
+ - mediatek,mt8173-disp-color
- items:
- enum:
- mediatek,mt7623-disp-color
diff --git a/Bindings/display/mediatek/mediatek,dither.yaml b/Bindings/display/mediatek/mediatek,dither.yaml
index 5c7445c..1588b3f 100644
--- a/Bindings/display/mediatek/mediatek,dither.yaml
+++ b/Bindings/display/mediatek/mediatek,dither.yaml
@@ -22,8 +22,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8183-disp-dither
+ - enum:
+ - mediatek,mt8183-disp-dither
- items:
- enum:
- mediatek,mt8186-disp-dither
diff --git a/Bindings/display/mediatek/mediatek,dsc.yaml b/Bindings/display/mediatek/mediatek,dsc.yaml
index 4924886..2cbdd9e 100644
--- a/Bindings/display/mediatek/mediatek,dsc.yaml
+++ b/Bindings/display/mediatek/mediatek,dsc.yaml
@@ -20,8 +20,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8195-disp-dsc
+ - enum:
+ - mediatek,mt8195-disp-dsc
reg:
maxItems: 1
diff --git a/Bindings/display/mediatek/mediatek,ethdr.yaml b/Bindings/display/mediatek/mediatek,ethdr.yaml
new file mode 100644
index 0000000..801fa66
--- /dev/null
+++ b/Bindings/display/mediatek/mediatek,ethdr.yaml
@@ -0,0 +1,182 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Ethdr Device
+
+maintainers:
+ - Chun-Kuang Hu <chunkuang.hu@kernel.org>
+ - Philipp Zabel <p.zabel@pengutronix.de>
+
+description:
+ ETHDR (ET High Dynamic Range) is a MediaTek internal HDR engine and is
+ designed for HDR video and graphics conversion in the external display path.
+ It handles multiple HDR input types and performs tone mapping, color
+ space/color format conversion, and then combine different layers,
+ output the required HDR or SDR signal to the subsequent display path.
+ This engine is composed of two video frontends, two graphic frontends,
+ one video backend and a mixer. ETHDR has two DMA function blocks, DS and ADL.
+ These two function blocks read the pre-programmed registers from DRAM and
+ set them to HW in the v-blanking period.
+
+properties:
+ compatible:
+ const: mediatek,mt8195-disp-ethdr
+
+ reg:
+ maxItems: 7
+
+ reg-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+
+ interrupts:
+ maxItems: 1
+
+ iommus:
+ minItems: 1
+ maxItems: 2
+
+ clocks:
+ items:
+ - description: mixer clock
+ - description: video frontend 0 clock
+ - description: video frontend 1 clock
+ - description: graphic frontend 0 clock
+ - description: graphic frontend 1 clock
+ - description: video backend clock
+ - description: autodownload and menuload clock
+ - description: video frontend 0 async clock
+ - description: video frontend 1 async clock
+ - description: graphic frontend 0 async clock
+ - description: graphic frontend 1 async clock
+ - description: video backend async clock
+ - description: ethdr top clock
+
+ clock-names:
+ items:
+ - const: mixer
+ - const: vdo_fe0
+ - const: vdo_fe1
+ - const: gfx_fe0
+ - const: gfx_fe1
+ - const: vdo_be
+ - const: adl_ds
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+ - const: ethdr_top
+
+ power-domains:
+ maxItems: 1
+
+ resets:
+ items:
+ - description: video frontend 0 async reset
+ - description: video frontend 1 async reset
+ - description: graphic frontend 0 async reset
+ - description: graphic frontend 1 async reset
+ - description: video backend async reset
+
+ reset-names:
+ items:
+ - const: vdo_fe0_async
+ - const: vdo_fe1_async
+ - const: gfx_fe0_async
+ - const: gfx_fe1_async
+ - const: vdo_be_async
+
+ mediatek,gce-client-reg:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 7
+ description: The register of display function block to be set by gce.
+ There are 4 arguments in this property, gce node, subsys id, offset and
+ register size. The subsys id is defined in the gce header of each chips
+ include/dt-bindings/gce/<chip>-gce.h, mapping to the register of display
+ function block.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - power-domains
+ - resets
+ - mediatek,gce-client-reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/gce/mt8195-gce.h>
+ #include <dt-bindings/memory/mt8195-memory-port.h>
+ #include <dt-bindings/power/mt8195-power.h>
+ #include <dt-bindings/reset/mt8195-resets.h>
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ hdr-engine@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11a000 0 0x1000>,
+ <0 0x1c11b000 0 0x1000>,
+ <0 0x1c11c000 0 0x1000>;
+ reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds";
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>,
+ <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR>;
+ clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
+ "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async",
+ "gfx_fe0_async", "gfx_fe1_async","vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /* disp mixer */
+ resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>;
+ reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
+ "gfx_fe1_async", "vdo_be_async";
+ };
+ };
+...
diff --git a/Bindings/display/mediatek/mediatek,gamma.yaml b/Bindings/display/mediatek/mediatek,gamma.yaml
index a5c6a91..6c2be9d 100644
--- a/Bindings/display/mediatek/mediatek,gamma.yaml
+++ b/Bindings/display/mediatek/mediatek,gamma.yaml
@@ -21,10 +21,9 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8173-disp-gamma
- - items:
- - const: mediatek,mt8183-disp-gamma
+ - enum:
+ - mediatek,mt8173-disp-gamma
+ - mediatek,mt8183-disp-gamma
- items:
- enum:
- mediatek,mt8186-disp-gamma
diff --git a/Bindings/display/mediatek/mediatek,hdmi.yaml b/Bindings/display/mediatek/mediatek,hdmi.yaml
index 8afdd67..b90b6d1 100644
--- a/Bindings/display/mediatek/mediatek,hdmi.yaml
+++ b/Bindings/display/mediatek/mediatek,hdmi.yaml
@@ -50,7 +50,7 @@
- const: hdmi
mediatek,syscon-hdmi:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to system configuration registers
diff --git a/Bindings/display/mediatek/mediatek,merge.yaml b/Bindings/display/mediatek/mediatek,merge.yaml
index 69ba757..2f8e2f4 100644
--- a/Bindings/display/mediatek/mediatek,merge.yaml
+++ b/Bindings/display/mediatek/mediatek,merge.yaml
@@ -21,10 +21,9 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8173-disp-merge
- - items:
- - const: mediatek,mt8195-disp-merge
+ - enum:
+ - mediatek,mt8173-disp-merge
+ - mediatek,mt8195-disp-merge
reg:
maxItems: 1
diff --git a/Bindings/display/mediatek/mediatek,od.yaml b/Bindings/display/mediatek/mediatek,od.yaml
index 853fcb9..29f9fa8 100644
--- a/Bindings/display/mediatek/mediatek,od.yaml
+++ b/Bindings/display/mediatek/mediatek,od.yaml
@@ -21,10 +21,9 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt2712-disp-od
- - items:
- - const: mediatek,mt8173-disp-od
+ - enum:
+ - mediatek,mt2712-disp-od
+ - mediatek,mt8173-disp-od
reg:
maxItems: 1
diff --git a/Bindings/display/mediatek/mediatek,ovl-2l.yaml b/Bindings/display/mediatek/mediatek,ovl-2l.yaml
index 4e94f4e..c7dd0ef 100644
--- a/Bindings/display/mediatek/mediatek,ovl-2l.yaml
+++ b/Bindings/display/mediatek/mediatek,ovl-2l.yaml
@@ -21,10 +21,9 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8183-disp-ovl-2l
- - items:
- - const: mediatek,mt8192-disp-ovl-2l
+ - enum:
+ - mediatek,mt8183-disp-ovl-2l
+ - mediatek,mt8192-disp-ovl-2l
- items:
- enum:
- mediatek,mt8186-disp-ovl-2l
diff --git a/Bindings/display/mediatek/mediatek,ovl.yaml b/Bindings/display/mediatek/mediatek,ovl.yaml
index 065e526..92e320d 100644
--- a/Bindings/display/mediatek/mediatek,ovl.yaml
+++ b/Bindings/display/mediatek/mediatek,ovl.yaml
@@ -21,14 +21,11 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt2701-disp-ovl
- - items:
- - const: mediatek,mt8173-disp-ovl
- - items:
- - const: mediatek,mt8183-disp-ovl
- - items:
- - const: mediatek,mt8192-disp-ovl
+ - enum:
+ - mediatek,mt2701-disp-ovl
+ - mediatek,mt8173-disp-ovl
+ - mediatek,mt8183-disp-ovl
+ - mediatek,mt8192-disp-ovl
- items:
- enum:
- mediatek,mt7623-disp-ovl
diff --git a/Bindings/display/mediatek/mediatek,postmask.yaml b/Bindings/display/mediatek/mediatek,postmask.yaml
index 27de644..11fe32e 100644
--- a/Bindings/display/mediatek/mediatek,postmask.yaml
+++ b/Bindings/display/mediatek/mediatek,postmask.yaml
@@ -21,8 +21,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8192-disp-postmask
+ - enum:
+ - mediatek,mt8192-disp-postmask
- items:
- enum:
- mediatek,mt8186-disp-postmask
diff --git a/Bindings/display/mediatek/mediatek,rdma.yaml b/Bindings/display/mediatek/mediatek,rdma.yaml
index 3ade2ec..42059ef 100644
--- a/Bindings/display/mediatek/mediatek,rdma.yaml
+++ b/Bindings/display/mediatek/mediatek,rdma.yaml
@@ -23,14 +23,11 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt2701-disp-rdma
- - items:
- - const: mediatek,mt8173-disp-rdma
- - items:
- - const: mediatek,mt8183-disp-rdma
- - items:
- - const: mediatek,mt8195-disp-rdma
+ - enum:
+ - mediatek,mt2701-disp-rdma
+ - mediatek,mt8173-disp-rdma
+ - mediatek,mt8183-disp-rdma
+ - mediatek,mt8195-disp-rdma
- items:
- enum:
- mediatek,mt8188-disp-rdma
diff --git a/Bindings/display/mediatek/mediatek,split.yaml b/Bindings/display/mediatek/mediatek,split.yaml
index 35ace1f..21a4e96 100644
--- a/Bindings/display/mediatek/mediatek,split.yaml
+++ b/Bindings/display/mediatek/mediatek,split.yaml
@@ -21,8 +21,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8173-disp-split
+ - enum:
+ - mediatek,mt8173-disp-split
reg:
maxItems: 1
diff --git a/Bindings/display/mediatek/mediatek,ufoe.yaml b/Bindings/display/mediatek/mediatek,ufoe.yaml
index b8bb135..62fad23 100644
--- a/Bindings/display/mediatek/mediatek,ufoe.yaml
+++ b/Bindings/display/mediatek/mediatek,ufoe.yaml
@@ -22,8 +22,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8173-disp-ufoe
+ - enum:
+ - mediatek,mt8173-disp-ufoe
reg:
maxItems: 1
diff --git a/Bindings/display/mediatek/mediatek,wdma.yaml b/Bindings/display/mediatek/mediatek,wdma.yaml
index 7d7cc1a..9911831 100644
--- a/Bindings/display/mediatek/mediatek,wdma.yaml
+++ b/Bindings/display/mediatek/mediatek,wdma.yaml
@@ -21,8 +21,8 @@
properties:
compatible:
oneOf:
- - items:
- - const: mediatek,mt8173-disp-wdma
+ - enum:
+ - mediatek,mt8173-disp-wdma
reg:
maxItems: 1
diff --git a/Bindings/display/msm/dsi-controller-main.yaml b/Bindings/display/msm/dsi-controller-main.yaml
index 51808b1..130e16d 100644
--- a/Bindings/display/msm/dsi-controller-main.yaml
+++ b/Bindings/display/msm/dsi-controller-main.yaml
@@ -74,7 +74,7 @@
syscon-sfpb:
description: A phandle to mmss_sfpb syscon node (only for DSIv2).
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
qcom,dual-dsi-mode:
type: boolean
@@ -117,14 +117,14 @@
type: object
ports:
- $ref: "/schemas/graph.yaml#/properties/ports"
+ $ref: /schemas/graph.yaml#/properties/ports
description: |
Contains DSI controller input and output ports as children, each
containing one endpoint subnode.
properties:
port@0:
- $ref: "/schemas/graph.yaml#/$defs/port-base"
+ $ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
Input endpoints of the controller.
@@ -140,7 +140,7 @@
enum: [ 0, 1, 2, 3 ]
port@1:
- $ref: "/schemas/graph.yaml#/$defs/port-base"
+ $ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: |
Output endpoints of the controller.
diff --git a/Bindings/display/msm/dsi-phy-10nm.yaml b/Bindings/display/msm/dsi-phy-10nm.yaml
index 3ec466c..e6b00d7 100644
--- a/Bindings/display/msm/dsi-phy-10nm.yaml
+++ b/Bindings/display/msm/dsi-phy-10nm.yaml
@@ -58,7 +58,7 @@
maximum: 31
qcom,phy-drive-ldo-level:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
The PHY LDO has an amplitude tuning feature to adjust the LDO output
for the HSTX drive. Use supported levels (mV) to offset the drive level
diff --git a/Bindings/display/msm/gmu.yaml b/Bindings/display/msm/gmu.yaml
index ab14e81..029d728 100644
--- a/Bindings/display/msm/gmu.yaml
+++ b/Bindings/display/msm/gmu.yaml
@@ -3,8 +3,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/msm/gmu.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/msm/gmu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GMU attached to certain Adreno GPUs
diff --git a/Bindings/display/msm/gpu.yaml b/Bindings/display/msm/gpu.yaml
index d4191cc..5dabe7b 100644
--- a/Bindings/display/msm/gpu.yaml
+++ b/Bindings/display/msm/gpu.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/msm/gpu.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/msm/gpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Adreno or Snapdragon GPUs
diff --git a/Bindings/display/msm/mdp4.yaml b/Bindings/display/msm/mdp4.yaml
index 58c13f5..35204a2 100644
--- a/Bindings/display/msm/mdp4.yaml
+++ b/Bindings/display/msm/mdp4.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/msm/mdp4.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/msm/mdp4.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Adreno/Snapdragon MDP4 display controller
diff --git a/Bindings/display/msm/qcom,mdp5.yaml b/Bindings/display/msm/qcom,mdp5.yaml
index ef461ad..a763cf8 100644
--- a/Bindings/display/msm/qcom,mdp5.yaml
+++ b/Bindings/display/msm/qcom,mdp5.yaml
@@ -61,7 +61,7 @@
- const: lut
- const: tbu
- const: tbu_rt
- #MSM8996 has additional iommu clock
+ # MSM8996 has additional iommu clock
- items:
- const: iface
- const: bus
diff --git a/Bindings/display/msm/qcom,mdss.yaml b/Bindings/display/msm/qcom,mdss.yaml
index 20889e4..b010010 100644
--- a/Bindings/display/msm/qcom,mdss.yaml
+++ b/Bindings/display/msm/qcom,mdss.yaml
@@ -101,6 +101,7 @@
patternProperties:
"^display-controller@[1-9a-f][0-9a-f]*$":
type: object
+ additionalProperties: true
properties:
compatible:
contains:
@@ -108,6 +109,7 @@
"^dsi@[1-9a-f][0-9a-f]*$":
type: object
+ additionalProperties: true
properties:
compatible:
contains:
@@ -115,6 +117,7 @@
"^phy@[1-9a-f][0-9a-f]*$":
type: object
+ additionalProperties: true
properties:
compatible:
enum:
@@ -132,6 +135,7 @@
"^hdmi-tx@[1-9a-f][0-9a-f]*$":
type: object
+ additionalProperties: true
properties:
compatible:
enum:
diff --git a/Bindings/display/panel/advantech,idk-1110wr.yaml b/Bindings/display/panel/advantech,idk-1110wr.yaml
index 3a8c2c1..f6fea90 100644
--- a/Bindings/display/panel/advantech,idk-1110wr.yaml
+++ b/Bindings/display/panel/advantech,idk-1110wr.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/boe,tv101wum-nl6.yaml b/Bindings/display/panel/boe,tv101wum-nl6.yaml
index a2384bd..aed5560 100644
--- a/Bindings/display/panel/boe,tv101wum-nl6.yaml
+++ b/Bindings/display/panel/boe,tv101wum-nl6.yaml
@@ -30,6 +30,8 @@
- boe,tv110c9m-ll3
# INX HJ110IZ-01A 10.95" WUXGA TFT LCD panel
- innolux,hj110iz-01a
+ # STARRY 2081101QFH032011-53G 10.1" WUXGA TFT LCD panel
+ - starry,2081101qfh032011-53g
reg:
description: the virtual channel number of a DSI peripheral
@@ -53,6 +55,7 @@
description: phandle of the backlight device attached to the panel
port: true
+ rotation: true
required:
- compatible
diff --git a/Bindings/display/panel/elida,kd35t133.yaml b/Bindings/display/panel/elida,kd35t133.yaml
index 7adb83e..265ab6d 100644
--- a/Bindings/display/panel/elida,kd35t133.yaml
+++ b/Bindings/display/panel/elida,kd35t133.yaml
@@ -17,7 +17,9 @@
const: elida,kd35t133
reg: true
backlight: true
+ port: true
reset-gpios: true
+ rotation: true
iovcc-supply:
description: regulator that supplies the iovcc voltage
vdd-supply:
@@ -27,6 +29,7 @@
- compatible
- reg
- backlight
+ - port
- iovcc-supply
- vdd-supply
@@ -43,6 +46,12 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vdd-supply = <&vcc3v3_lcd>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
};
};
diff --git a/Bindings/display/panel/feiyang,fy07024di26a30d.yaml b/Bindings/display/panel/feiyang,fy07024di26a30d.yaml
index 1cf84c8..92df69e 100644
--- a/Bindings/display/panel/feiyang,fy07024di26a30d.yaml
+++ b/Bindings/display/panel/feiyang,fy07024di26a30d.yaml
@@ -26,6 +26,7 @@
dvdd-supply:
description: 3v3 digital regulator
+ port: true
reset-gpios: true
backlight: true
@@ -35,6 +36,7 @@
- reg
- avdd-supply
- dvdd-supply
+ - port
additionalProperties: false
@@ -53,5 +55,11 @@
dvdd-supply = <®_dldo2>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
backlight = <&backlight>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
};
};
diff --git a/Bindings/display/panel/innolux,ee101ia-01d.yaml b/Bindings/display/panel/innolux,ee101ia-01d.yaml
index 566e11f..ab6b7be 100644
--- a/Bindings/display/panel/innolux,ee101ia-01d.yaml
+++ b/Bindings/display/panel/innolux,ee101ia-01d.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/innolux,p120zdg-bf1.yaml b/Bindings/display/panel/innolux,p120zdg-bf1.yaml
deleted file mode 100644
index 243dac2..0000000
--- a/Bindings/display/panel/innolux,p120zdg-bf1.yaml
+++ /dev/null
@@ -1,43 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0
-%YAML 1.2
----
-$id: http://devicetree.org/schemas/display/panel/innolux,p120zdg-bf1.yaml#
-$schema: http://devicetree.org/meta-schemas/core.yaml#
-
-title: Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
-
-maintainers:
- - Sandeep Panda <spanda@codeaurora.org>
- - Douglas Anderson <dianders@chromium.org>
-
-allOf:
- - $ref: panel-common.yaml#
-
-properties:
- compatible:
- const: innolux,p120zdg-bf1
-
- enable-gpios: true
- power-supply: true
- backlight: true
- no-hpd: true
-
-required:
- - compatible
- - power-supply
-
-additionalProperties: false
-
-examples:
- - |
- #include <dt-bindings/gpio/gpio.h>
-
- panel_edp: panel-edp {
- compatible = "innolux,p120zdg-bf1";
- enable-gpios = <&msmgpio 31 GPIO_ACTIVE_LOW>;
- power-supply = <&pm8916_l2>;
- backlight = <&backlight>;
- no-hpd;
- };
-
-...
diff --git a/Bindings/display/panel/mitsubishi,aa104xd12.yaml b/Bindings/display/panel/mitsubishi,aa104xd12.yaml
index 5cf3c58..3623ffa 100644
--- a/Bindings/display/panel/mitsubishi,aa104xd12.yaml
+++ b/Bindings/display/panel/mitsubishi,aa104xd12.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/mitsubishi,aa121td01.yaml b/Bindings/display/panel/mitsubishi,aa121td01.yaml
index 54750cc..37f01d8 100644
--- a/Bindings/display/panel/mitsubishi,aa121td01.yaml
+++ b/Bindings/display/panel/mitsubishi,aa121td01.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/nec,nl8048hl11.yaml b/Bindings/display/panel/nec,nl8048hl11.yaml
index 3b09b35..accf933 100644
--- a/Bindings/display/panel/nec,nl8048hl11.yaml
+++ b/Bindings/display/panel/nec,nl8048hl11.yaml
@@ -41,7 +41,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/display/panel/novatek,nt36523.yaml b/Bindings/display/panel/novatek,nt36523.yaml
new file mode 100644
index 0000000..0039561
--- /dev/null
+++ b/Bindings/display/panel/novatek,nt36523.yaml
@@ -0,0 +1,85 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/novatek,nt36523.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Novatek NT36523 based DSI display Panels
+
+maintainers:
+ - Jianhua Lu <lujianhua000@gmail.com>
+
+description: |
+ The Novatek NT36523 is a generic DSI Panel IC used to drive dsi
+ panels. Support video mode panels from China Star Optoelectronics
+ Technology (CSOT) and BOE Technology.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - xiaomi,elish-boe-nt36523
+ - xiaomi,elish-csot-nt36523
+ - const: novatek,nt36523
+
+ reset-gpios:
+ maxItems: 1
+ description: phandle of gpio for reset line - This should be 8mA
+
+ vddio-supply:
+ description: regulator that supplies the I/O voltage
+
+ reg: true
+ ports: true
+ backlight: true
+
+required:
+ - compatible
+ - reg
+ - vddio-supply
+ - reset-gpios
+ - ports
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel@0 {
+ compatible = "xiaomi,elish-csot-nt36523", "novatek,nt36523";
+ reg = <0>;
+
+ vddio-supply = <&vreg_l14a_1p88>;
+ reset-gpios = <&tlmm 75 GPIO_ACTIVE_LOW>;
+ backlight = <&backlight>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ panel_in_0: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+
+ port@1{
+ reg = <1>;
+ panel_in_1: endpoint {
+ remote-endpoint = <&dsi1_out>;
+ };
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/display/panel/novatek,nt36672a.yaml b/Bindings/display/panel/novatek,nt36672a.yaml
index 41ee315..ae821f4 100644
--- a/Bindings/display/panel/novatek,nt36672a.yaml
+++ b/Bindings/display/panel/novatek,nt36672a.yaml
@@ -34,7 +34,7 @@
description: phandle of gpio for reset line - This should be 8mA, gpio
can be configured using mux, pinctrl, pinctrl-names (active high)
- vddi0-supply:
+ vddio-supply:
description: phandle of the regulator that provides the supply voltage
Power IC supply
@@ -51,7 +51,7 @@
required:
- compatible
- reg
- - vddi0-supply
+ - vddio-supply
- vddpos-supply
- vddneg-supply
- reset-gpios
@@ -70,7 +70,7 @@
panel@0 {
compatible = "tianma,fhd-video", "novatek,nt36672a";
reg = <0>;
- vddi0-supply = <&vreg_l14a_1p88>;
+ vddio-supply = <&vreg_l14a_1p88>;
vddpos-supply = <&lab>;
vddneg-supply = <&ibb>;
diff --git a/Bindings/display/panel/panel-lvds.yaml b/Bindings/display/panel/panel-lvds.yaml
index c77ee03..929fe04 100644
--- a/Bindings/display/panel/panel-lvds.yaml
+++ b/Bindings/display/panel/panel-lvds.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/panel-simple-dsi.yaml b/Bindings/display/panel/panel-simple-dsi.yaml
index 2c00813..90c04cf 100644
--- a/Bindings/display/panel/panel-simple-dsi.yaml
+++ b/Bindings/display/panel/panel-simple-dsi.yaml
@@ -19,9 +19,6 @@
If the panel is more advanced a dedicated binding file is required.
-allOf:
- - $ref: panel-common.yaml#
-
properties:
compatible:
@@ -67,12 +64,31 @@
reset-gpios: true
port: true
power-supply: true
+ vddio-supply: true
+
+allOf:
+ - $ref: panel-common.yaml#
+ - if:
+ properties:
+ compatible:
+ enum:
+ - samsung,s6e3fc2x01
+ - samsung,sofef00
+ then:
+ properties:
+ power-supply: false
+ required:
+ - vddio-supply
+ else:
+ properties:
+ vddio-supply: false
+ required:
+ - power-supply
additionalProperties: false
required:
- compatible
- - power-supply
- reg
examples:
diff --git a/Bindings/display/panel/panel-simple.yaml b/Bindings/display/panel/panel-simple.yaml
index 18241f4..01560fe 100644
--- a/Bindings/display/panel/panel-simple.yaml
+++ b/Bindings/display/panel/panel-simple.yaml
@@ -192,6 +192,8 @@
- innolux,n125hce-gn1
# InnoLux 15.6" WXGA TFT LCD panel
- innolux,n156bge-l21
+ # Innolux P120ZDG-BF1 12.02 inch eDP 2K display panel
+ - innolux,p120zdg-bf1
# Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel
- innolux,zj070na-01p
# King & Display KD116N21-30NV-A010 eDP TFT LCD panel
diff --git a/Bindings/display/panel/panel-timing.yaml b/Bindings/display/panel/panel-timing.yaml
index 0d317e6..aea69b8 100644
--- a/Bindings/display/panel/panel-timing.yaml
+++ b/Bindings/display/panel/panel-timing.yaml
@@ -17,29 +17,29 @@
The parameters are defined as seen in the following illustration.
- +----------+-------------------------------------+----------+-------+
- | | ^ | | |
- | | |vback_porch | | |
- | | v | | |
- +----------#######################################----------+-------+
- | # ^ # | |
- | # | # | |
- | hback # | # hfront | hsync |
- | porch # | hactive # porch | len |
- |<-------->#<-------+--------------------------->#<-------->|<----->|
- | # | # | |
- | # |vactive # | |
- | # | # | |
- | # v # | |
- +----------#######################################----------+-------+
- | | ^ | | |
- | | |vfront_porch | | |
- | | v | | |
- +----------+-------------------------------------+----------+-------+
- | | ^ | | |
- | | |vsync_len | | |
- | | v | | |
- +----------+-------------------------------------+----------+-------+
+ +-------+----------+-------------------------------------+----------+
+ | | | ^ | |
+ | | | |vsync_len | |
+ | | | v | |
+ +-------+----------+-------------------------------------+----------+
+ | | | ^ | |
+ | | | |vback_porch | |
+ | | | v | |
+ +-------+----------#######################################----------+
+ | | # ^ # |
+ | | # | # |
+ | hsync | hback # | # hfront |
+ | len | porch # | hactive # porch |
+ |<----->|<-------->#<-------+--------------------------->#<-------->|
+ | | # | # |
+ | | # |vactive # |
+ | | # | # |
+ | | # v # |
+ +-------+----------#######################################----------+
+ | | | ^ | |
+ | | | |vfront_porch | |
+ | | | v | |
+ +-------+----------+-------------------------------------+----------+
The following is the panel timings shown with time on the x-axis.
diff --git a/Bindings/display/panel/ronbo,rb070d30.yaml b/Bindings/display/panel/ronbo,rb070d30.yaml
index d67617f..95ce22c 100644
--- a/Bindings/display/panel/ronbo,rb070d30.yaml
+++ b/Bindings/display/panel/ronbo,rb070d30.yaml
@@ -37,7 +37,7 @@
backlight:
description: Backlight used by the panel
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
diff --git a/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml b/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
index 44ce98f..b749e9e 100644
--- a/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
+++ b/Bindings/display/panel/samsung,s6e88a0-ams452ef01.yaml
@@ -16,6 +16,7 @@
compatible:
const: samsung,s6e88a0-ams452ef01
reg: true
+ port: true
reset-gpios: true
vdd3-supply:
description: core voltage supply
@@ -25,6 +26,7 @@
required:
- compatible
- reg
+ - port
- vdd3-supply
- vci-supply
- reset-gpios
@@ -46,5 +48,11 @@
vdd3-supply = <&pm8916_l17>;
vci-supply = <®_vlcd_vci>;
reset-gpios = <&msmgpio 25 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
};
};
diff --git a/Bindings/display/panel/seiko,43wvf1g.yaml b/Bindings/display/panel/seiko,43wvf1g.yaml
index cfaa50c..1df3cbb 100644
--- a/Bindings/display/panel/seiko,43wvf1g.yaml
+++ b/Bindings/display/panel/seiko,43wvf1g.yaml
@@ -7,7 +7,7 @@
title: Seiko Instruments Inc. 4.3" WVGA (800 x RGB x 480) TFT with Touch-Panel
maintainers:
- - Marco Franchi <marco.franchi@nxp.com>
+ - Fabio Estevam <festevam@gmail.com>
allOf:
- $ref: panel-common.yaml#
@@ -25,6 +25,8 @@
avdd-supply:
description: 5v analog regulator
+ enable-gpios: true
+
required:
- compatible
- dvdd-supply
diff --git a/Bindings/display/panel/sgd,gktw70sdae4se.yaml b/Bindings/display/panel/sgd,gktw70sdae4se.yaml
index 2e75e37..e32d918 100644
--- a/Bindings/display/panel/sgd,gktw70sdae4se.yaml
+++ b/Bindings/display/panel/sgd,gktw70sdae4se.yaml
@@ -12,7 +12,7 @@
allOf:
- $ref: panel-common.yaml#
- - $ref: /schemas/display/lvds.yaml/#
+ - $ref: /schemas/display/lvds.yaml#
select:
properties:
diff --git a/Bindings/display/panel/sharp,lq101r1sx01.yaml b/Bindings/display/panel/sharp,lq101r1sx01.yaml
index 9ec0e8a..57b44a0 100644
--- a/Bindings/display/panel/sharp,lq101r1sx01.yaml
+++ b/Bindings/display/panel/sharp,lq101r1sx01.yaml
@@ -34,8 +34,8 @@
- items:
- const: sharp,lq101r1sx03
- const: sharp,lq101r1sx01
- - items:
- - const: sharp,lq101r1sx01
+ - enum:
+ - sharp,lq101r1sx01
reg: true
power-supply: true
diff --git a/Bindings/display/panel/sitronix,st7701.yaml b/Bindings/display/panel/sitronix,st7701.yaml
index 34d5e20..4dc0cd4 100644
--- a/Bindings/display/panel/sitronix,st7701.yaml
+++ b/Bindings/display/panel/sitronix,st7701.yaml
@@ -28,6 +28,7 @@
items:
- enum:
- densitron,dmt028vghmcmi-1a
+ - elida,kd50t048a
- techstar,ts8550b
- const: sitronix,st7701
@@ -41,7 +42,9 @@
IOVCC-supply:
description: I/O system regulator
+ port: true
reset-gpios: true
+ rotation: true
backlight: true
@@ -50,6 +53,7 @@
- reg
- VCC-supply
- IOVCC-supply
+ - port
- reset-gpios
additionalProperties: false
@@ -69,5 +73,11 @@
IOVCC-supply = <®_dldo2>;
reset-gpios = <&pio 3 24 GPIO_ACTIVE_HIGH>; /* LCD-RST: PD24 */
backlight = <&backlight>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
};
};
diff --git a/Bindings/display/panel/sitronix,st7789v.yaml b/Bindings/display/panel/sitronix,st7789v.yaml
index d984b59..fa65563 100644
--- a/Bindings/display/panel/sitronix,st7789v.yaml
+++ b/Bindings/display/panel/sitronix,st7789v.yaml
@@ -26,6 +26,10 @@
spi-cpha: true
spi-cpol: true
+ dc-gpios:
+ maxItems: 1
+ description: DCX pin, Display data/command selection pin in parallel interface
+
required:
- compatible
- reg
diff --git a/Bindings/display/panel/sony,td4353-jdi.yaml b/Bindings/display/panel/sony,td4353-jdi.yaml
new file mode 100644
index 0000000..b6b885b
--- /dev/null
+++ b/Bindings/display/panel/sony,td4353-jdi.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/panel/sony,td4353-jdi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Sony TD4353 JDI 5 / 5.7" 2160x1080 MIPI-DSI Panel
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@somainline.org>
+
+description: |
+ The Sony TD4353 JDI is a 5 (XZ2c) / 5.7 (XZ2) inch 2160x1080
+ MIPI-DSI panel, used in Xperia XZ2 and XZ2 Compact smartphones.
+
+allOf:
+ - $ref: panel-common.yaml#
+
+properties:
+ compatible:
+ const: sony,td4353-jdi-tama
+
+ reg: true
+
+ backlight: true
+
+ vddio-supply:
+ description: VDDIO 1.8V supply
+
+ vsp-supply:
+ description: Positive 5.5V supply
+
+ vsn-supply:
+ description: Negative 5.5V supply
+
+ panel-reset-gpios:
+ description: Display panel reset pin
+
+ touch-reset-gpios:
+ description: Touch panel reset pin
+
+ port: true
+
+required:
+ - compatible
+ - reg
+ - vddio-supply
+ - vsp-supply
+ - vsn-supply
+ - panel-reset-gpios
+ - touch-reset-gpios
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ panel: panel@0 {
+ compatible = "sony,td4353-jdi-tama";
+ reg = <0>;
+
+ backlight = <&pmi8998_wled>;
+ vddio-supply = <&vreg_l14a_1p8>;
+ vsp-supply = <&lab>;
+ vsn-supply = <&ibb>;
+ panel-reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
+ touch-reset-gpios = <&tlmm 99 GPIO_ACTIVE_HIGH>;
+
+ port {
+ panel_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/display/panel/visionox,rm69299.yaml b/Bindings/display/panel/visionox,rm69299.yaml
index 481ef05..444ac2a 100644
--- a/Bindings/display/panel/visionox,rm69299.yaml
+++ b/Bindings/display/panel/visionox,rm69299.yaml
@@ -19,6 +19,8 @@
compatible:
const: visionox,rm69299-1080p-display
+ reg: true
+
vdda-supply:
description: |
Phandle of the regulator that provides the vdda supply voltage.
@@ -34,6 +36,7 @@
required:
- compatible
+ - reg
- vdda-supply
- vdd3p3-supply
- reset-gpios
@@ -41,16 +44,22 @@
examples:
- |
- panel {
- compatible = "visionox,rm69299-1080p-display";
+ dsi {
+ #address-cells = <1>;
+ #size-cells = <0>;
- vdda-supply = <&src_pp1800_l8c>;
- vdd3p3-supply = <&src_pp2800_l18a>;
+ panel@0 {
+ compatible = "visionox,rm69299-1080p-display";
+ reg = <0>;
- reset-gpios = <&pm6150l_gpio 3 0>;
- port {
- panel0_in: endpoint {
- remote-endpoint = <&dsi0_out>;
+ vdda-supply = <&src_pp1800_l8c>;
+ vdd3p3-supply = <&src_pp2800_l18a>;
+
+ reset-gpios = <&pm6150l_gpio 3 0>;
+ port {
+ panel0_in: endpoint {
+ remote-endpoint = <&dsi0_out>;
+ };
};
};
};
diff --git a/Bindings/display/panel/xinpeng,xpp055c272.yaml b/Bindings/display/panel/xinpeng,xpp055c272.yaml
index d5c46a3..c407deb 100644
--- a/Bindings/display/panel/xinpeng,xpp055c272.yaml
+++ b/Bindings/display/panel/xinpeng,xpp055c272.yaml
@@ -17,6 +17,7 @@
const: xinpeng,xpp055c272
reg: true
backlight: true
+ port: true
reset-gpios: true
iovcc-supply:
description: regulator that supplies the iovcc voltage
@@ -27,6 +28,7 @@
- compatible
- reg
- backlight
+ - port
- iovcc-supply
- vci-supply
@@ -44,6 +46,12 @@
backlight = <&backlight>;
iovcc-supply = <&vcc_1v8>;
vci-supply = <&vcc3v3_lcd>;
+
+ port {
+ mipi_in_panel: endpoint {
+ remote-endpoint = <&mipi_out_panel>;
+ };
+ };
};
};
diff --git a/Bindings/display/renesas,du.yaml b/Bindings/display/renesas,du.yaml
index d4830f5..c5b9e68 100644
--- a/Bindings/display/renesas,du.yaml
+++ b/Bindings/display/renesas,du.yaml
@@ -76,7 +76,7 @@
unevaluatedProperties: false
renesas,cmms:
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
description:
@@ -84,7 +84,7 @@
available DU channel.
renesas,vsps:
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle to VSP instance that serves the DU channel
diff --git a/Bindings/display/solomon,ssd1307fb.yaml b/Bindings/display/solomon,ssd1307fb.yaml
index 669f70b..94bb5ef 100644
--- a/Bindings/display/solomon,ssd1307fb.yaml
+++ b/Bindings/display/solomon,ssd1307fb.yaml
@@ -14,20 +14,18 @@
compatible:
oneOf:
# Deprecated compatible strings
- - items:
- - enum:
- - solomon,ssd1305fb-i2c
- - solomon,ssd1306fb-i2c
- - solomon,ssd1307fb-i2c
- - solomon,ssd1309fb-i2c
+ - enum:
+ - solomon,ssd1305fb-i2c
+ - solomon,ssd1306fb-i2c
+ - solomon,ssd1307fb-i2c
+ - solomon,ssd1309fb-i2c
deprecated: true
- - items:
- - enum:
- - sinowealth,sh1106
- - solomon,ssd1305
- - solomon,ssd1306
- - solomon,ssd1307
- - solomon,ssd1309
+ - enum:
+ - sinowealth,sh1106
+ - solomon,ssd1305
+ - solomon,ssd1306
+ - solomon,ssd1307
+ - solomon,ssd1309
reg:
maxItems: 1
@@ -226,7 +224,7 @@
examples:
- |
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -239,7 +237,7 @@
ssd1306_i2c: oled@3d {
compatible = "solomon,ssd1306";
- reg = <0x3c>;
+ reg = <0x3d>;
pwms = <&pwm 4 3000>;
reset-gpios = <&gpio2 7>;
solomon,com-lrremap;
diff --git a/Bindings/display/tegra/nvidia,tegra114-mipi.yaml b/Bindings/display/tegra/nvidia,tegra114-mipi.yaml
index d5ca8cf..f448624 100644
--- a/Bindings/display/tegra/nvidia,tegra114-mipi.yaml
+++ b/Bindings/display/tegra/nvidia,tegra114-mipi.yaml
@@ -38,7 +38,7 @@
description: The number of cells in a MIPI calibration specifier.
Should be 1. The single cell specifies a bitmask of the pads that
need to be calibrated for a given device.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
const: 1
additionalProperties: false
diff --git a/Bindings/display/tegra/nvidia,tegra124-sor.yaml b/Bindings/display/tegra/nvidia,tegra124-sor.yaml
index 907fb0b..70f0e45 100644
--- a/Bindings/display/tegra/nvidia,tegra124-sor.yaml
+++ b/Bindings/display/tegra/nvidia,tegra124-sor.yaml
@@ -69,12 +69,12 @@
# Tegra186 and later
nvidia,interface:
description: index of the SOR interface
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
@@ -82,23 +82,23 @@
nvidia,edid:
description: supplies a binary EDID blob
- $ref: "/schemas/types.yaml#/definitions/uint8-array"
+ $ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel, required for eDP
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
nvidia,xbar-cfg:
description: 5 cells containing the crossbar configuration.
Each lane of the SOR, identified by the cell's index, is
mapped via the crossbar to the pad specified by the cell's
value.
- $ref: "/schemas/types.yaml#/definitions/uint32-array"
+ $ref: /schemas/types.yaml#/definitions/uint32-array
# optional when driving an eDP output
nvidia,dpaux:
description: phandle to a DispayPort AUX interface
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
allOf:
- if:
diff --git a/Bindings/display/tegra/nvidia,tegra186-dc.yaml b/Bindings/display/tegra/nvidia,tegra186-dc.yaml
index 265a60d..ce45894 100644
--- a/Bindings/display/tegra/nvidia,tegra186-dc.yaml
+++ b/Bindings/display/tegra/nvidia,tegra186-dc.yaml
@@ -60,13 +60,13 @@
nvidia,outputs:
description: A list of phandles of outputs that this display
controller can drive.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: /schemas/types.yaml#/definitions/phandle-array
nvidia,head:
description: The number of the display controller head. This
is used to setup the various types of output to receive
video data from the given head.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
additionalProperties: false
diff --git a/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml b/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
index e5a6145..da75b71 100644
--- a/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
+++ b/Bindings/display/tegra/nvidia,tegra186-dsi-padctl.yaml
@@ -29,7 +29,7 @@
- const: dsi
allOf:
- - $ref: "/schemas/reset/reset.yaml"
+ - $ref: /schemas/reset/reset.yaml
additionalProperties: false
diff --git a/Bindings/display/tegra/nvidia,tegra20-dsi.yaml b/Bindings/display/tegra/nvidia,tegra20-dsi.yaml
index 511cbe7..59e1dc0 100644
--- a/Bindings/display/tegra/nvidia,tegra20-dsi.yaml
+++ b/Bindings/display/tegra/nvidia,tegra20-dsi.yaml
@@ -59,12 +59,12 @@
description: Should contain a phandle and a specifier specifying
which pads are used by this DSI output and need to be
calibrated. See nvidia,tegra114-mipi.yaml for details.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: /schemas/types.yaml#/definitions/phandle-array
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
@@ -72,19 +72,19 @@
nvidia,edid:
description: supplies a binary EDID blob
- $ref: "/schemas/types.yaml#/definitions/uint8-array"
+ $ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
nvidia,ganged-mode:
description: contains a phandle to a second DSI controller to
gang up with in order to support up to 8 data lanes
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
allOf:
- - $ref: "../dsi-controller.yaml#"
+ - $ref: ../dsi-controller.yaml#
- if:
properties:
compatible:
diff --git a/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml b/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml
index f65e59c..f77197e 100644
--- a/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml
+++ b/Bindings/display/tegra/nvidia,tegra20-hdmi.yaml
@@ -68,7 +68,7 @@
nvidia,ddc-i2c-bus:
description: phandle of an I2C controller used for DDC EDID
probing
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
nvidia,hpd-gpio:
description: specifies a GPIO used for hotplug detection
@@ -76,11 +76,11 @@
nvidia,edid:
description: supplies a binary EDID blob
- $ref: "/schemas/types.yaml#/definitions/uint8-array"
+ $ref: /schemas/types.yaml#/definitions/uint8-array
nvidia,panel:
description: phandle of a display panel
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
"#sound-dai-cells":
const: 0
diff --git a/Bindings/display/ti/ti,am65x-dss.yaml b/Bindings/display/ti/ti,am65x-dss.yaml
index 5c7d2cb..b6b402f 100644
--- a/Bindings/display/ti/ti,am65x-dss.yaml
+++ b/Bindings/display/ti/ti,am65x-dss.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/ti/ti,am65x-dss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments AM65x Display Subsystem
@@ -88,7 +88,7 @@
The DSS DPI output port node from video port 2
ti,am65x-oldi-io-ctrl:
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
description:
phandle to syscon device node mapping OLDI IO_CTRL registers.
The mapped range should point to OLDI_DAT0_IO_CTRL, map it and
diff --git a/Bindings/display/ti/ti,j721e-dss.yaml b/Bindings/display/ti/ti,j721e-dss.yaml
index 2986f9a..fad7cba 100644
--- a/Bindings/display/ti/ti,j721e-dss.yaml
+++ b/Bindings/display/ti/ti,j721e-dss.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/ti/ti,j721e-dss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments J721E Display Subsystem
diff --git a/Bindings/display/ti/ti,k2g-dss.yaml b/Bindings/display/ti/ti,k2g-dss.yaml
index 7ce7bba..96b1439 100644
--- a/Bindings/display/ti/ti,k2g-dss.yaml
+++ b/Bindings/display/ti/ti,k2g-dss.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Texas Instruments Incorporated
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/ti/ti,k2g-dss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments K2G Display Subsystem
diff --git a/Bindings/display/xylon,logicvc-display.yaml b/Bindings/display/xylon,logicvc-display.yaml
index fc02c5d..76b804b 100644
--- a/Bindings/display/xylon,logicvc-display.yaml
+++ b/Bindings/display/xylon,logicvc-display.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 Bootlin
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/display/xylon,logicvc-display.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xylon LogiCVC display controller
@@ -89,25 +89,25 @@
description: Display output colorspace (C_DISPLAY_COLOR_SPACE).
xylon,display-depth:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Display output depth (C_PIXEL_DATA_WIDTH).
xylon,row-stride:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Fixed number of pixels in a framebuffer row (C_ROW_STRIDE).
xylon,dithering:
- $ref: "/schemas/types.yaml#/definitions/flag"
+ $ref: /schemas/types.yaml#/definitions/flag
description: Dithering module is enabled (C_XCOLOR)
xylon,background-layer:
- $ref: "/schemas/types.yaml#/definitions/flag"
+ $ref: /schemas/types.yaml#/definitions/flag
description: |
The last layer is used to display a black background (C_USE_BACKGROUND).
The layer must still be registered.
xylon,layers-configurable:
- $ref: "/schemas/types.yaml#/definitions/flag"
+ $ref: /schemas/types.yaml#/definitions/flag
description: |
Configuration of layers' size, position and offset is enabled
(C_USE_SIZE_POSITION).
@@ -131,7 +131,7 @@
maxItems: 1
xylon,layer-depth:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description: Layer depth (C_LAYER_X_DATA_WIDTH).
xylon,layer-colorspace:
@@ -151,19 +151,19 @@
description: Alpha mode for the layer (C_LAYER_X_ALPHA_MODE).
xylon,layer-base-offset:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Offset in number of lines (C_LAYER_X_OFFSET) starting from the
video RAM base (C_VMEM_BASEADDR), only for version 3.
xylon,layer-buffer-offset:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
Offset in number of lines (C_BUFFER_*_OFFSET) starting from the
layer base offset for the second buffer used in double-buffering.
xylon,layer-primary:
- $ref: "/schemas/types.yaml#/definitions/flag"
+ $ref: /schemas/types.yaml#/definitions/flag
description: |
Layer should be registered as a primary plane (exactly one is
required).
diff --git a/Bindings/dma/apple,admac.yaml b/Bindings/dma/apple,admac.yaml
index 05163d1..ab193bc 100644
--- a/Bindings/dma/apple,admac.yaml
+++ b/Bindings/dma/apple,admac.yaml
@@ -26,6 +26,7 @@
- enum:
- apple,t6000-admac
- apple,t8103-admac
+ - apple,t8112-admac
- const: apple,admac
reg:
diff --git a/Bindings/dma/qcom,gpi.yaml b/Bindings/dma/qcom,gpi.yaml
index fc5de7b..f61145c 100644
--- a/Bindings/dma/qcom,gpi.yaml
+++ b/Bindings/dma/qcom,gpi.yaml
@@ -24,6 +24,7 @@
- qcom,sm6350-gpi-dma
- items:
- enum:
+ - qcom,qcm2290-gpi-dma
- qcom,qdu1000-gpi-dma
- qcom,sc7280-gpi-dma
- qcom,sm6115-gpi-dma
diff --git a/Bindings/dma/renesas,rz-dmac.yaml b/Bindings/dma/renesas,rz-dmac.yaml
index f638d39..c284abc 100644
--- a/Bindings/dma/renesas,rz-dmac.yaml
+++ b/Bindings/dma/renesas,rz-dmac.yaml
@@ -54,6 +54,11 @@
- description: DMA main clock
- description: DMA register access clock
+ clock-names:
+ items:
+ - const: main
+ - const: register
+
'#dma-cells':
const: 1
description:
@@ -77,16 +82,23 @@
- description: Reset for DMA ARESETN reset terminal
- description: Reset for DMA RST_ASYNC reset terminal
+ reset-names:
+ items:
+ - const: arst
+ - const: rst_async
+
required:
- compatible
- reg
- interrupts
- interrupt-names
- clocks
+ - clock-names
- '#dma-cells'
- dma-channels
- power-domains
- resets
+ - reset-names
additionalProperties: false
@@ -124,9 +136,11 @@
"ch12", "ch13", "ch14", "ch15";
clocks = <&cpg CPG_MOD R9A07G044_DMAC_ACLK>,
<&cpg CPG_MOD R9A07G044_DMAC_PCLK>;
+ clock-names = "main", "register";
power-domains = <&cpg>;
resets = <&cpg R9A07G044_DMAC_ARESETN>,
<&cpg R9A07G044_DMAC_RST_ASYNC>;
+ reset-names = "arst", "rst_async";
#dma-cells = <1>;
dma-channels = <16>;
};
diff --git a/Bindings/dma/snps,dw-axi-dmac.yaml b/Bindings/dma/snps,dw-axi-dmac.yaml
index 5c81194..363cf8b 100644
--- a/Bindings/dma/snps,dw-axi-dmac.yaml
+++ b/Bindings/dma/snps,dw-axi-dmac.yaml
@@ -20,6 +20,7 @@
enum:
- snps,axi-dma-1.01a
- intel,kmb-axi-dma
+ - starfive,jh7110-axi-dma
reg:
minItems: 1
@@ -58,7 +59,8 @@
maximum: 8
resets:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
snps,dma-masters:
description: |
@@ -109,6 +111,25 @@
- snps,priority
- snps,block-size
+if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - starfive,jh7110-axi-dma
+then:
+ properties:
+ resets:
+ minItems: 2
+ items:
+ - description: AXI reset line
+ - description: AHB reset line
+ - description: module reset
+else:
+ properties:
+ resets:
+ maxItems: 1
+
additionalProperties: false
examples:
diff --git a/Bindings/dma/ti/k3-udma.yaml b/Bindings/dma/ti/k3-udma.yaml
index 97f6ae9..22f6c5e 100644
--- a/Bindings/dma/ti/k3-udma.yaml
+++ b/Bindings/dma/ti/k3-udma.yaml
@@ -43,7 +43,7 @@
configuration of the legacy peripheral.
allOf:
- - $ref: "../dma-controller.yaml#"
+ - $ref: ../dma-controller.yaml#
- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
properties:
diff --git a/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml b/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
index c0a1408..23ada8f 100644
--- a/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
+++ b/Bindings/dma/xilinx/xlnx,zynqmp-dma-1.0.yaml
@@ -15,7 +15,7 @@
- Michael Tretter <m.tretter@pengutronix.de>
allOf:
- - $ref: "../dma-controller.yaml#"
+ - $ref: ../dma-controller.yaml#
properties:
"#dma-cells":
diff --git a/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml b/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
index 825294e..d6cbd95 100644
--- a/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
+++ b/Bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml
@@ -16,7 +16,7 @@
- Laurent Pinchart <laurent.pinchart@ideasonboard.com>
allOf:
- - $ref: "../dma-controller.yaml#"
+ - $ref: ../dma-controller.yaml#
properties:
"#dma-cells":
diff --git a/Bindings/eeprom/at25.yaml b/Bindings/eeprom/at25.yaml
index 0f5a8ef..11e2a95 100644
--- a/Bindings/eeprom/at25.yaml
+++ b/Bindings/eeprom/at25.yaml
@@ -122,7 +122,7 @@
examples:
- |
#include <dt-bindings/gpio/gpio.h>
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/example-schema.yaml b/Bindings/example-schema.yaml
index dfcf4c2..f4eec4c 100644
--- a/Bindings/example-schema.yaml
+++ b/Bindings/example-schema.yaml
@@ -176,6 +176,8 @@
description: Child nodes are just another property from a json-schema
perspective.
type: object # DT nodes are json objects
+ # Child nodes also need additionalProperties or unevaluatedProperties
+ additionalProperties: false
properties:
vendor,a-child-node-property:
description: Child node properties have all the same schema
diff --git a/Bindings/extcon/extcon-usbc-cros-ec.yaml b/Bindings/extcon/extcon-usbc-cros-ec.yaml
index 2e5b398..e00c807 100644
--- a/Bindings/extcon/extcon-usbc-cros-ec.yaml
+++ b/Bindings/extcon/extcon-usbc-cros-ec.yaml
@@ -34,7 +34,7 @@
examples:
- |
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
cros-ec@0 {
diff --git a/Bindings/extcon/extcon-usbc-tusb320.yaml b/Bindings/extcon/extcon-usbc-tusb320.yaml
index 71a9f2e..126107d 100644
--- a/Bindings/extcon/extcon-usbc-tusb320.yaml
+++ b/Bindings/extcon/extcon-usbc-tusb320.yaml
@@ -30,7 +30,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
tusb320@61 {
diff --git a/Bindings/firmware/arm,scmi.yaml b/Bindings/firmware/arm,scmi.yaml
index 2f7c51c..5824c43 100644
--- a/Bindings/firmware/arm,scmi.yaml
+++ b/Bindings/firmware/arm,scmi.yaml
@@ -56,17 +56,38 @@
description:
Specifies the mailboxes used to communicate with SCMI compliant
firmware.
- items:
- - const: tx
- - const: rx
+ oneOf:
+ - items:
+ - const: tx
+ - const: rx
+ minItems: 1
+ - items:
+ - const: tx
+ - const: tx_reply
+ - const: rx
+ minItems: 2
mboxes:
description:
List of phandle and mailbox channel specifiers. It should contain
- exactly one or two mailboxes, one for transmitting messages("tx")
- and another optional for receiving the notifications("rx") if supported.
+ exactly one, two or three mailboxes; the first one or two for transmitting
+ messages ("tx") and another optional ("rx") for receiving notifications
+ and delayed responses, if supported by the platform.
+ The number of mailboxes needed for transmitting messages depends on the
+ type of channels exposed by the specific underlying mailbox controller;
+ one single channel descriptor is enough if such channel is bidirectional,
+ while two channel descriptors are needed to represent the SCMI ("tx")
+ channel if the underlying mailbox channels are of unidirectional type.
+ The effective combination in numbers of mboxes and shmem descriptors let
+ the SCMI subsystem determine unambiguosly which type of SCMI channels are
+ made available by the underlying mailbox controller and how to use them.
+ 1 mbox / 1 shmem => SCMI TX over 1 mailbox bidirectional channel
+ 2 mbox / 2 shmem => SCMI TX and RX over 2 mailbox bidirectional channels
+ 2 mbox / 1 shmem => SCMI TX over 2 mailbox unidirectional channels
+ 3 mbox / 2 shmem => SCMI TX and RX over 3 mailbox unidirectional channels
+ Any other combination of mboxes and shmem is invalid.
minItems: 1
- maxItems: 2
+ maxItems: 3
shmem:
description:
@@ -228,13 +249,20 @@
maxItems: 1
mbox-names:
- items:
- - const: tx
- - const: rx
+ oneOf:
+ - items:
+ - const: tx
+ - const: rx
+ minItems: 1
+ - items:
+ - const: tx
+ - const: tx_reply
+ - const: rx
+ minItems: 2
mboxes:
minItems: 1
- maxItems: 2
+ maxItems: 3
shmem:
minItems: 1
diff --git a/Bindings/firmware/qcom,scm.yaml b/Bindings/firmware/qcom,scm.yaml
index a66e998..367d04a 100644
--- a/Bindings/firmware/qcom,scm.yaml
+++ b/Bindings/firmware/qcom,scm.yaml
@@ -24,9 +24,11 @@
- qcom,scm-apq8064
- qcom,scm-apq8084
- qcom,scm-ipq4019
+ - qcom,scm-ipq5332
- qcom,scm-ipq6018
- qcom,scm-ipq806x
- qcom,scm-ipq8074
+ - qcom,scm-ipq9574
- qcom,scm-mdm9607
- qcom,scm-msm8226
- qcom,scm-msm8660
@@ -38,10 +40,12 @@
- qcom,scm-msm8994
- qcom,scm-msm8996
- qcom,scm-msm8998
+ - qcom,scm-qcm2290
- qcom,scm-qdu1000
- qcom,scm-sa8775p
- qcom,scm-sc7180
- qcom,scm-sc7280
+ - qcom,scm-sc8180x
- qcom,scm-sc8280xp
- qcom,scm-sdm670
- qcom,scm-sdm845
@@ -107,6 +111,7 @@
- qcom,scm-msm8960
- qcom,scm-msm8974
- qcom,scm-msm8976
+ - qcom,scm-qcm2290
- qcom,scm-sm6375
then:
required:
@@ -125,6 +130,7 @@
- qcom,scm-apq8064
- qcom,scm-msm8660
- qcom,scm-msm8960
+ - qcom,scm-qcm2290
- qcom,scm-sm6375
then:
properties:
@@ -166,6 +172,7 @@
compatible:
contains:
enum:
+ - qcom,scm-qdu1000
- qcom,scm-sm8450
- qcom,scm-sm8550
then:
diff --git a/Bindings/fpga/xilinx-pr-decoupler.txt b/Bindings/fpga/xilinx-pr-decoupler.txt
deleted file mode 100644
index 0acdfa6..0000000
--- a/Bindings/fpga/xilinx-pr-decoupler.txt
+++ /dev/null
@@ -1,54 +0,0 @@
-Xilinx LogiCORE Partial Reconfig Decoupler Softcore
-
-The Xilinx LogiCORE Partial Reconfig Decoupler manages one or more
-decouplers / fpga bridges.
-The controller can decouple/disable the bridges which prevents signal
-changes from passing through the bridge. The controller can also
-couple / enable the bridges which allows traffic to pass through the
-bridge normally.
-
-Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager
-Softcore is compatible with the Xilinx LogiCORE pr-decoupler.
-
-The Dynamic Function eXchange AXI shutdown manager prevents AXI traffic
-from passing through the bridge. The controller safely handles AXI4MM
-and AXI4-Lite interfaces on a Reconfigurable Partition when it is
-undergoing dynamic reconfiguration, preventing the system deadlock
-that can occur if AXI transactions are interrupted by DFX
-
-The Driver supports only MMIO handling. A PR region can have multiple
-PR Decouplers which can be handled independently or chained via decouple/
-decouple_status signals.
-
-Required properties:
-- compatible : Should contain "xlnx,pr-decoupler-1.00" followed by
- "xlnx,pr-decoupler" or
- "xlnx,dfx-axi-shutdown-manager-1.00" followed by
- "xlnx,dfx-axi-shutdown-manager"
-- regs : base address and size for decoupler module
-- clocks : input clock to IP
-- clock-names : should contain "aclk"
-
-See Documentation/devicetree/bindings/fpga/fpga-region.txt and
-Documentation/devicetree/bindings/fpga/fpga-bridge.txt for generic bindings.
-
-Example:
-Partial Reconfig Decoupler:
- fpga-bridge@100000450 {
- compatible = "xlnx,pr-decoupler-1.00",
- "xlnx-pr-decoupler";
- regs = <0x10000045 0x10>;
- clocks = <&clkc 15>;
- clock-names = "aclk";
- bridge-enable = <0>;
- };
-
-Dynamic Function eXchange AXI shutdown manager:
- fpga-bridge@100000450 {
- compatible = "xlnx,dfx-axi-shutdown-manager-1.00",
- "xlnx,dfx-axi-shutdown-manager";
- regs = <0x10000045 0x10>;
- clocks = <&clkc 15>;
- clock-names = "aclk";
- bridge-enable = <0>;
- };
diff --git a/Bindings/fpga/xilinx-slave-serial.txt b/Bindings/fpga/xilinx-slave-serial.txt
deleted file mode 100644
index 5ef659c..0000000
--- a/Bindings/fpga/xilinx-slave-serial.txt
+++ /dev/null
@@ -1,51 +0,0 @@
-Xilinx Slave Serial SPI FPGA Manager
-
-Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the
-bitstream over what is referred to as "slave serial" interface.
-The slave serial link is not technically SPI, and might require extra
-circuits in order to play nicely with other SPI slaves on the same bus.
-
-See:
-- https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
-- https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
-- https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
-
-Required properties:
-- compatible: should contain "xlnx,fpga-slave-serial"
-- reg: spi chip select of the FPGA
-- prog_b-gpios: config pin (referred to as PROGRAM_B in the manual)
-- done-gpios: config status pin (referred to as DONE in the manual)
-
-Optional properties:
-- init-b-gpios: initialization status and configuration error pin
- (referred to as INIT_B in the manual)
-
-Example for full FPGA configuration:
-
- fpga-region0 {
- compatible = "fpga-region";
- fpga-mgr = <&fpga_mgr_spi>;
- #address-cells = <0x1>;
- #size-cells = <0x1>;
- };
-
- spi1: spi@10680 {
- compatible = "marvell,armada-xp-spi", "marvell,orion-spi";
- pinctrl-0 = <&spi0_pins>;
- pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
- cell-index = <1>;
- interrupts = <92>;
- clocks = <&coreclk 0>;
-
- fpga_mgr_spi: fpga-mgr@0 {
- compatible = "xlnx,fpga-slave-serial";
- spi-max-frequency = <60000000>;
- spi-cpha;
- reg = <0>;
- prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
- init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
- done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
- };
- };
diff --git a/Bindings/fpga/xlnx,fpga-slave-serial.yaml b/Bindings/fpga/xlnx,fpga-slave-serial.yaml
new file mode 100644
index 0000000..614d86a
--- /dev/null
+++ b/Bindings/fpga/xlnx,fpga-slave-serial.yaml
@@ -0,0 +1,80 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx Slave Serial SPI FPGA
+
+maintainers:
+ - Nava kishore Manne <nava.kishore.manne@amd.com>
+
+description: |
+ Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
+ over what is referred to as slave serial interface.The slave serial link is
+ not technically SPI, and might require extra circuits in order to play nicely
+ with other SPI slaves on the same bus.
+
+ Datasheets:
+ https://www.xilinx.com/support/documentation/user_guides/ug380.pdf
+ https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
+ https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
+
+allOf:
+ - $ref: /schemas/spi/spi-peripheral-props.yaml#
+
+properties:
+ compatible:
+ enum:
+ - xlnx,fpga-slave-serial
+
+ spi-cpha: true
+
+ spi-max-frequency:
+ maximum: 60000000
+
+ reg:
+ maxItems: 1
+
+ prog_b-gpios:
+ description:
+ config pin (referred to as PROGRAM_B in the manual)
+ maxItems: 1
+
+ done-gpios:
+ description:
+ config status pin (referred to as DONE in the manual)
+ maxItems: 1
+
+ init-b-gpios:
+ description:
+ initialization status and configuration error pin
+ (referred to as INIT_B in the manual)
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - prog_b-gpios
+ - done-gpios
+ - init-b-gpios
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ spi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ fpga_mgr_spi: fpga-mgr@0 {
+ compatible = "xlnx,fpga-slave-serial";
+ spi-max-frequency = <60000000>;
+ spi-cpha;
+ reg = <0>;
+ prog_b-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
+ init-b-gpios = <&gpio0 28 GPIO_ACTIVE_LOW>;
+ done-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>;
+ };
+ };
+...
diff --git a/Bindings/fpga/xlnx,pr-decoupler.yaml b/Bindings/fpga/xlnx,pr-decoupler.yaml
new file mode 100644
index 0000000..a7d4b8e
--- /dev/null
+++ b/Bindings/fpga/xlnx,pr-decoupler.yaml
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/fpga/xlnx,pr-decoupler.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Xilinx LogiCORE Partial Reconfig Decoupler/AXI shutdown manager Softcore
+
+maintainers:
+ - Nava kishore Manne <nava.kishore.manne@amd.com>
+
+description: |
+ The Xilinx LogiCORE Partial Reconfig(PR) Decoupler manages one or more
+ decouplers/fpga bridges. The controller can decouple/disable the bridges
+ which prevents signal changes from passing through the bridge. The controller
+ can also couple / enable the bridges which allows traffic to pass through the
+ bridge normally.
+ Xilinx LogiCORE Dynamic Function eXchange(DFX) AXI shutdown manager Softcore
+ is compatible with the Xilinx LogiCORE pr-decoupler. The Dynamic Function
+ eXchange AXI shutdown manager prevents AXI traffic from passing through the
+ bridge. The controller safely handles AXI4MM and AXI4-Lite interfaces on a
+ Reconfigurable Partition when it is undergoing dynamic reconfiguration,
+ preventing the system deadlock that can occur if AXI transactions are
+ interrupted by DFX.
+ Please refer to fpga-region.txt and fpga-bridge.txt in this directory for
+ common binding part and usage.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - const: xlnx,pr-decoupler-1.00
+ - const: xlnx,pr-decoupler
+ - items:
+ - const: xlnx,dfx-axi-shutdown-manager-1.00
+ - const: xlnx,dfx-axi-shutdown-manager
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: aclk
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+
+additionalProperties: false
+
+examples:
+ - |
+ fpga-bridge@100000450 {
+ compatible = "xlnx,pr-decoupler-1.00", "xlnx,pr-decoupler";
+ reg = <0x10000045 0x10>;
+ clocks = <&clkc 15>;
+ clock-names = "aclk";
+ };
+...
diff --git a/Bindings/gpio/fcs,fxl6408.yaml b/Bindings/gpio/fcs,fxl6408.yaml
new file mode 100644
index 0000000..65b6970
--- /dev/null
+++ b/Bindings/gpio/fcs,fxl6408.yaml
@@ -0,0 +1,58 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/fcs,fxl6408.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fairchild FXL6408 I2C GPIO Expander
+
+maintainers:
+ - Emanuele Ghidoli <emanuele.ghidoli@toradex.com>
+
+properties:
+ compatible:
+ enum:
+ - fcs,fxl6408
+
+ reg:
+ maxItems: 1
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ gpio-line-names:
+ minItems: 1
+ maxItems: 8
+
+patternProperties:
+ "^(hog-[0-9]+|.+-hog(-[0-9]+)?)$":
+ required:
+ - gpio-hog
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ gpio_expander_43: gpio-expander@43 {
+ compatible = "fcs,fxl6408";
+ reg = <0x43>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-line-names = "Wi-Fi_W_DISABLE", "Wi-Fi_WKUP_WLAN",
+ "PWR_EN_+V3.3_WiFi_N", "PCIe_REF_CLK_EN",
+ "USB_RESET_N", "USB_BYPASS_N", "Wi-Fi_PDn",
+ "Wi-Fi_WKUP_BT";
+ };
+ };
diff --git a/Bindings/gpio/gpio-pca9570.yaml b/Bindings/gpio/gpio-pca9570.yaml
index 48bf414..5b01343 100644
--- a/Bindings/gpio/gpio-pca9570.yaml
+++ b/Bindings/gpio/gpio-pca9570.yaml
@@ -34,7 +34,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/gpio/gpio-pca95xx.yaml b/Bindings/gpio/gpio-pca95xx.yaml
index 1b70e9f..fa11614 100644
--- a/Bindings/gpio/gpio-pca95xx.yaml
+++ b/Bindings/gpio/gpio-pca95xx.yaml
@@ -151,7 +151,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -177,7 +177,7 @@
- |
#include <dt-bindings/interrupt-controller/irq.h>
- i2c1 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -203,7 +203,7 @@
- |
#include <dt-bindings/interrupt-controller/irq.h>
- i2c2 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -221,7 +221,7 @@
};
- |
- i2c3 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/gpio/gpio.txt b/Bindings/gpio/gpio.txt
index 5663e71..d82c322 100644
--- a/Bindings/gpio/gpio.txt
+++ b/Bindings/gpio/gpio.txt
@@ -154,18 +154,35 @@
Optionally, a GPIO controller may have a "gpio-line-names" property. This is
an array of strings defining the names of the GPIO lines going out of the
-GPIO controller. This name should be the most meaningful producer name
-for the system, such as a rail name indicating the usage. Package names
-such as pin name are discouraged: such lines have opaque names (since they
-are by definition generic purpose) and such names are usually not very
-helpful. For example "MMC-CD", "Red LED Vdd" and "ethernet reset" are
-reasonable line names as they describe what the line is used for. "GPIO0"
-is not a good name to give to a GPIO line. Placeholders are discouraged:
-rather use the "" (blank string) if the use of the GPIO line is undefined
-in your design. The names are assigned starting from line offset 0 from
-left to right from the passed array. An incomplete array (where the number
-of passed named are less than ngpios) will still be used up until the last
-provided valid line index.
+GPIO controller.
+
+For lines which are routed to on-board devices, this name should be
+the most meaningful producer name for the system, such as a rail name
+indicating the usage. Package names, such as a pin name, are discouraged:
+such lines have opaque names (since they are by definition general-purpose)
+and such names are usually not very helpful. For example "MMC-CD", "Red LED
+Vdd" and "ethernet reset" are reasonable line names as they describe what
+the line is used for. "GPIO0" is not a good name to give to a GPIO line
+that is hard-wired to a specific device.
+
+However, in the case of lines that are routed to a general purpose header
+(e.g. the Raspberry Pi 40-pin header), and therefore are not hard-wired to
+specific devices, using a pin number or the names on the header is fine
+provided these are real (preferably unique) names. Using an SoC's pad name
+or package name, or names made up from kernel-internal software constructs,
+are strongly discouraged. For example "pin8 [gpio14/uart0_txd]" is fine
+if the board's documentation labels pin 8 as such. However "PortB_24" (an
+example of a name from an SoC's reference manual) would not be desirable.
+
+In either case placeholders are discouraged: rather use the "" (blank
+string) if the use of the GPIO line is undefined in your design. Ideally,
+try to add comments to the dts file describing the naming the convention
+you have chosen, and specifying from where the names are derived.
+
+The names are assigned starting from line offset 0, from left to right,
+from the passed array. An incomplete array (where the number of passed
+names is less than ngpios) will be used up until the last provided valid
+line index.
Example:
diff --git a/Bindings/gpio/loongson,ls-gpio.yaml b/Bindings/gpio/loongson,ls-gpio.yaml
new file mode 100644
index 0000000..fb86e8c
--- /dev/null
+++ b/Bindings/gpio/loongson,ls-gpio.yaml
@@ -0,0 +1,126 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/loongson,ls-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson GPIO controller.
+
+maintainers:
+ - Yinbo Zhu <zhuyinbo@loongson.cn>
+
+properties:
+ compatible:
+ enum:
+ - loongson,ls2k-gpio
+ - loongson,ls7a-gpio
+
+ reg:
+ maxItems: 1
+
+ ngpios:
+ minimum: 1
+ maximum: 64
+
+ "#gpio-cells":
+ const: 2
+
+ gpio-controller: true
+
+ gpio-ranges: true
+
+ interrupts:
+ minItems: 1
+ maxItems: 64
+
+required:
+ - compatible
+ - reg
+ - ngpios
+ - "#gpio-cells"
+ - gpio-controller
+ - gpio-ranges
+ - interrupts
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ gpio0: gpio@1fe00500 {
+ compatible = "loongson,ls2k-gpio";
+ reg = <0x1fe00500 0x38>;
+ ngpios = <64>;
+ #gpio-cells = <2>;
+ gpio-controller;
+ gpio-ranges = <&pctrl 0 0 15>,
+ <&pctrl 16 16 15>,
+ <&pctrl 32 32 10>,
+ <&pctrl 44 44 20>;
+ interrupt-parent = <&liointc1>;
+ interrupts = <28 IRQ_TYPE_LEVEL_LOW>,
+ <29 IRQ_TYPE_LEVEL_LOW>,
+ <30 IRQ_TYPE_LEVEL_LOW>,
+ <30 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <26 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <>,
+ <>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>,
+ <27 IRQ_TYPE_LEVEL_LOW>;
+ };
diff --git a/Bindings/gpio/loongson,ls1x-gpio.yaml b/Bindings/gpio/loongson,ls1x-gpio.yaml
new file mode 100644
index 0000000..1a472c0
--- /dev/null
+++ b/Bindings/gpio/loongson,ls1x-gpio.yaml
@@ -0,0 +1,49 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/gpio/loongson,ls1x-gpio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Loongson-1 GPIO controller
+
+maintainers:
+ - Keguang Zhang <keguang.zhang@gmail.com>
+
+properties:
+ compatible:
+ const: loongson,ls1x-gpio
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ "#gpio-cells":
+ const: 2
+
+ ngpios:
+ minimum: 1
+ maximum: 32
+
+required:
+ - compatible
+ - reg
+ - gpio-controller
+ - "#gpio-cells"
+ - ngpios
+
+additionalProperties: false
+
+examples:
+ - |
+ gpio0: gpio@1fd010c0 {
+ compatible = "loongson,ls1x-gpio";
+ reg = <0x1fd010c0 0x4>;
+
+ gpio-controller;
+ #gpio-cells = <2>;
+
+ ngpios = <32>;
+ };
+
+...
diff --git a/Bindings/gpio/nxp,pcf8575.yaml b/Bindings/gpio/nxp,pcf8575.yaml
index f0ff66c..3718103 100644
--- a/Bindings/gpio/nxp,pcf8575.yaml
+++ b/Bindings/gpio/nxp,pcf8575.yaml
@@ -39,6 +39,10 @@
reg:
maxItems: 1
+ gpio-line-names:
+ minItems: 1
+ maxItems: 16
+
gpio-controller: true
'#gpio-cells':
diff --git a/Bindings/gpio/x-powers,axp209-gpio.yaml b/Bindings/gpio/x-powers,axp209-gpio.yaml
index 7f26f6b..31906c2 100644
--- a/Bindings/gpio/x-powers,axp209-gpio.yaml
+++ b/Bindings/gpio/x-powers,axp209-gpio.yaml
@@ -35,6 +35,7 @@
patternProperties:
"^.*-pins?$":
$ref: /schemas/pinctrl/pinmux-node.yaml#
+ additionalProperties: false
properties:
pins:
diff --git a/Bindings/gpu/arm,mali-bifrost.yaml b/Bindings/gpu/arm,mali-bifrost.yaml
index 78964c1..0400a36 100644
--- a/Bindings/gpu/arm,mali-bifrost.yaml
+++ b/Bindings/gpu/arm,mali-bifrost.yaml
@@ -19,6 +19,8 @@
- enum:
- amlogic,meson-g12a-mali
- mediatek,mt8183-mali
+ - mediatek,mt8183b-mali
+ - mediatek,mt8186-mali
- realtek,rtd1619-mali
- renesas,r9a07g044-mali
- renesas,r9a07g054-mali
@@ -27,6 +29,11 @@
- const: arm,mali-bifrost # Mali Bifrost GPU model/revision is fully discoverable
- items:
- enum:
+ - mediatek,mt8195-mali
+ - const: mediatek,mt8192-mali
+ - const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
+ - items:
+ - enum:
- mediatek,mt8192-mali
- const: arm,mali-valhall-jm # Mali Valhall GPU model/revision is fully discoverable
@@ -63,7 +70,11 @@
power-domains:
minItems: 1
- maxItems: 3
+ maxItems: 5
+
+ power-domain-names:
+ minItems: 2
+ maxItems: 5
resets:
minItems: 1
@@ -93,6 +104,13 @@
dma-coherent: true
+ nvmem-cell-names:
+ items:
+ - const: speed-bin
+
+ nvmem-cells:
+ maxItems: 1
+
required:
- compatible
- reg
@@ -109,6 +127,10 @@
contains:
const: amlogic,meson-g12a-mali
then:
+ properties:
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
required:
- resets
- if:
@@ -131,6 +153,9 @@
- const: gpu
- const: bus
- const: bus_ace
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
resets:
minItems: 3
reset-names:
@@ -152,6 +177,7 @@
properties:
power-domains:
minItems: 3
+ maxItems: 3
power-domain-names:
items:
- const: core0
@@ -164,13 +190,65 @@
- power-domain-names
else:
properties:
- power-domains:
- maxItems: 1
sram-supply: false
- if:
properties:
compatible:
contains:
+ const: mediatek,mt8183b-mali
+ then:
+ properties:
+ power-domains:
+ minItems: 3
+ maxItems: 3
+ power-domain-names:
+ items:
+ - const: core0
+ - const: core1
+ - const: core2
+ required:
+ - power-domains
+ - power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8186-mali
+ then:
+ properties:
+ power-domains:
+ minItems: 2
+ maxItems: 2
+ power-domain-names:
+ items:
+ - const: core0
+ - const: core1
+ required:
+ - power-domains
+ - power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: mediatek,mt8192-mali
+ then:
+ properties:
+ power-domains:
+ minItems: 5
+ power-domain-names:
+ items:
+ - const: core0
+ - const: core1
+ - const: core2
+ - const: core3
+ - const: core4
+ required:
+ - power-domains
+ - power-domain-names
+ - if:
+ properties:
+ compatible:
+ contains:
const: rockchip,rk3568-mali
then:
properties:
@@ -180,6 +258,9 @@
items:
- const: gpu
- const: bus
+ power-domains:
+ maxItems: 1
+ power-domain-names: false
required:
- clock-names
diff --git a/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml b/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
index ed9554c..ba4c647 100644
--- a/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
+++ b/Bindings/gpu/host1x/nvidia,tegra210-nvdec.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvdec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVDEC
diff --git a/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml b/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
index 8199e5f..c23dae7 100644
--- a/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
+++ b/Bindings/gpu/host1x/nvidia,tegra210-nvenc.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVENC
diff --git a/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml b/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
index 895fb34..99a33a5 100644
--- a/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
+++ b/Bindings/gpu/host1x/nvidia,tegra210-nvjpg.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvjpg.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra NVJPG
diff --git a/Bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml b/Bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
index 4bdc19a..0b7561c 100644
--- a/Bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
+++ b/Bindings/gpu/host1x/nvidia,tegra234-nvdec.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra234-nvdec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NVIDIA Tegra234 NVDEC
diff --git a/Bindings/hwmon/adi,ltc2992.yaml b/Bindings/hwmon/adi,ltc2992.yaml
index dba74f4..b39c632 100644
--- a/Bindings/hwmon/adi,ltc2992.yaml
+++ b/Bindings/hwmon/adi,ltc2992.yaml
@@ -32,6 +32,7 @@
patternProperties:
"^channel@([0-1])$":
type: object
+ additionalProperties: false
description: |
Represents the two supplies to be monitored.
diff --git a/Bindings/hwmon/pwm-fan.txt b/Bindings/hwmon/pwm-fan.txt
index 4509e68..48886f0 100644
--- a/Bindings/hwmon/pwm-fan.txt
+++ b/Bindings/hwmon/pwm-fan.txt
@@ -1,67 +1 @@
-Bindings for a fan connected to the PWM lines
-
-Required properties:
-- compatible : "pwm-fan"
-- pwms : the PWM that is used to control the PWM fan
-- cooling-levels : PWM duty cycle values in a range from 0 to 255
- which correspond to thermal cooling states
-
-Optional properties:
-- fan-supply : phandle to the regulator that provides power to the fan
-- interrupts : This contains an interrupt specifier for each fan
- tachometer output connected to an interrupt source.
- The output signal must generate a defined number of
- interrupts per fan revolution, which require that
- it must be self resetting edge interrupts. See
- interrupt-controller/interrupts.txt for the format.
-- pulses-per-revolution : define the number of pulses per fan revolution for
- each tachometer input as an integer (default is 2
- interrupts per revolution). The value must be
- greater than zero.
-
-Example:
- fan0: pwm-fan {
- compatible = "pwm-fan";
- #cooling-cells = <2>;
- pwms = <&pwm 0 10000 0>;
- cooling-levels = <0 102 170 230>;
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- thermal-sensors = <&tmu 0>;
- polling-delay-passive = <0>;
- polling-delay = <0>;
- trips {
- cpu_alert1: cpu-alert1 {
- temperature = <100000>; /* millicelsius */
- hysteresis = <2000>; /* millicelsius */
- type = "passive";
- };
- };
- cooling-maps {
- map0 {
- trip = <&cpu_alert1>;
- cooling-device = <&fan0 0 1>;
- };
- };
- };
-
-Example 2:
- fan0: pwm-fan {
- compatible = "pwm-fan";
- pwms = <&pwm 0 40000 0>;
- fan-supply = <®_fan>;
- interrupt-parent = <&gpio5>;
- interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
- pulses-per-revolution = <2>;
- };
-
-Example 3:
- fan0: pwm-fan {
- compatible = "pwm-fan";
- pwms = <&pwm1 0 25000 0>;
- interrupts-extended = <&gpio1 1 IRQ_TYPE_EDGE_FALLING>,
- <&gpio2 5 IRQ_TYPE_EDGE_FALLING>;
- pulses-per-revolution = <2>, <1>;
- };
+This file has moved to pwm-fan.yaml.
diff --git a/Bindings/hwmon/pwm-fan.yaml b/Bindings/hwmon/pwm-fan.yaml
new file mode 100644
index 0000000..4e5abf7
--- /dev/null
+++ b/Bindings/hwmon/pwm-fan.yaml
@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/pwm-fan.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Fan connected to PWM lines
+
+maintainers:
+ - Jean Delvare <jdelvare@suse.com>
+ - Guenter Roeck <linux@roeck-us.net>
+
+properties:
+ compatible:
+ const: pwm-fan
+
+ cooling-levels:
+ description: PWM duty cycle values corresponding to thermal cooling states.
+ $ref: /schemas/types.yaml#/definitions/uint32-array
+ items:
+ maximum: 255
+
+ fan-supply:
+ description: Phandle to the regulator that provides power to the fan.
+
+ interrupts:
+ description:
+ This contains an interrupt specifier for each fan tachometer output
+ connected to an interrupt source. The output signal must generate a
+ defined number of interrupts per fan revolution, which require that
+ it must be self resetting edge interrupts.
+ maxItems: 1
+
+ pulses-per-revolution:
+ description:
+ Define the number of pulses per fan revolution for each tachometer
+ input as an integer.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 4
+ default: 2
+
+ pwms:
+ description: The PWM that is used to control the fan.
+ maxItems: 1
+
+ "#cooling-cells": true
+
+required:
+ - compatible
+ - pwms
+
+additionalProperties: false
+
+examples:
+ - |
+ pwm-fan {
+ compatible = "pwm-fan";
+ cooling-levels = <0 102 170 230>;
+ pwms = <&pwm 0 10000 0>;
+ #cooling-cells = <2>;
+ };
+
+ thermal-zones {
+ cpu_thermal: cpu-thermal {
+ thermal-sensors = <&tmu 0>;
+ polling-delay-passive = <0>;
+ polling-delay = <0>;
+
+ trips {
+ cpu_alert1: cpu-alert1 {
+ temperature = <100000>; /* millicelsius */
+ hysteresis = <2000>; /* millicelsius */
+ type = "passive";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&fan0 0 1>;
+ };
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ pwm-fan {
+ compatible = "pwm-fan";
+ pwms = <&pwm 0 40000 0>;
+ fan-supply = <®_fan>;
+ interrupt-parent = <&gpio5>;
+ interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
+ pulses-per-revolution = <2>;
+ };
diff --git a/Bindings/hwmon/starfive,jh71x0-temp.yaml b/Bindings/hwmon/starfive,jh71x0-temp.yaml
new file mode 100644
index 0000000..f5b3452
--- /dev/null
+++ b/Bindings/hwmon/starfive,jh71x0-temp.yaml
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/starfive,jh71x0-temp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH71x0 Temperature Sensor
+
+maintainers:
+ - Emil Renner Berthing <kernel@esmil.dk>
+
+description: |
+ StarFive Technology Co. JH71x0 embedded temperature sensor
+
+properties:
+ compatible:
+ enum:
+ - starfive,jh7100-temp
+ - starfive,jh7110-temp
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ minItems: 2
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: "sense"
+ - const: "bus"
+
+ '#thermal-sensor-cells':
+ const: 0
+
+ resets:
+ minItems: 2
+ maxItems: 2
+
+ reset-names:
+ items:
+ - const: "sense"
+ - const: "bus"
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/starfive-jh7100.h>
+ #include <dt-bindings/reset/starfive-jh7100.h>
+
+ temperature-sensor@124a0000 {
+ compatible = "starfive,jh7100-temp";
+ reg = <0x124a0000 0x10000>;
+ clocks = <&clkgen JH7100_CLK_TEMP_SENSE>,
+ <&clkgen JH7100_CLK_TEMP_APB>;
+ clock-names = "sense", "bus";
+ #thermal-sensor-cells = <0>;
+ resets = <&rstgen JH7100_RSTN_TEMP_SENSE>,
+ <&rstgen JH7100_RSTN_TEMP_APB>;
+ reset-names = "sense", "bus";
+ };
diff --git a/Bindings/hwmon/ti,ina2xx.yaml b/Bindings/hwmon/ti,ina2xx.yaml
index 47af97b..8648877 100644
--- a/Bindings/hwmon/ti,ina2xx.yaml
+++ b/Bindings/hwmon/ti,ina2xx.yaml
@@ -57,6 +57,10 @@
$ref: /schemas/types.yaml#/definitions/uint32
enum: [1, 2, 4, 8]
+ vs-supply:
+ description: phandle to the regulator that provides the VS supply typically
+ in range from 2.7 V to 5.5 V.
+
required:
- compatible
- reg
@@ -73,5 +77,6 @@
compatible = "ti,ina220";
reg = <0x44>;
shunt-resistor = <1000>;
+ vs-supply = <&vdd_3v0>;
};
};
diff --git a/Bindings/hwmon/ti,tmp464.yaml b/Bindings/hwmon/ti,tmp464.yaml
index e7493e2..f9c00cb 100644
--- a/Bindings/hwmon/ti,tmp464.yaml
+++ b/Bindings/hwmon/ti,tmp464.yaml
@@ -7,7 +7,7 @@
title: TMP464 and TMP468 temperature sensors
maintainers:
- - Agathe Porte <agathe.porte@nokia.com>
+ - Guenter Roeck <linux@roeck-us.net>
description: |
±0.0625°C Remote and Local temperature sensor
diff --git a/Bindings/i2c/amlogic,meson6-i2c.yaml b/Bindings/i2c/amlogic,meson6-i2c.yaml
index 199a354..26bed55 100644
--- a/Bindings/i2c/amlogic,meson6-i2c.yaml
+++ b/Bindings/i2c/amlogic,meson6-i2c.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/i2c/amlogic,meson6-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson I2C Controller
diff --git a/Bindings/i2c/apple,i2c.yaml b/Bindings/i2c/apple,i2c.yaml
index 4ac61fe..077d2a5 100644
--- a/Bindings/i2c/apple,i2c.yaml
+++ b/Bindings/i2c/apple,i2c.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/i2c/apple,i2c.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/i2c/apple,i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Apple/PASemi I2C controller
@@ -23,6 +23,7 @@
items:
- enum:
- apple,t8103-i2c
+ - apple,t8112-i2c
- apple,t6000-i2c
- const: apple,i2c
diff --git a/Bindings/i2c/aspeed,i2c.yaml b/Bindings/i2c/aspeed,i2c.yaml
index 869b4d6..6df27b4 100644
--- a/Bindings/i2c/aspeed,i2c.yaml
+++ b/Bindings/i2c/aspeed,i2c.yaml
@@ -60,7 +60,7 @@
examples:
- |
#include <dt-bindings/clock/aspeed-clock.h>
- i2c0: i2c-bus@40 {
+ i2c@40 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "aspeed,ast2500-i2c-bus";
diff --git a/Bindings/i2c/atmel,at91sam-i2c.yaml b/Bindings/i2c/atmel,at91sam-i2c.yaml
index ea2303c..6adedd3 100644
--- a/Bindings/i2c/atmel,at91sam-i2c.yaml
+++ b/Bindings/i2c/atmel,at91sam-i2c.yaml
@@ -75,7 +75,7 @@
- clocks
allOf:
- - $ref: "i2c-controller.yaml"
+ - $ref: i2c-controller.yaml
- if:
properties:
compatible:
diff --git a/Bindings/i2c/brcm,kona-i2c.txt b/Bindings/i2c/brcm,kona-i2c.txt
deleted file mode 100644
index 1b87b74..0000000
--- a/Bindings/i2c/brcm,kona-i2c.txt
+++ /dev/null
@@ -1,35 +0,0 @@
-Broadcom Kona Family I2C
-=========================
-
-This I2C controller is used in the following Broadcom SoCs:
-
- BCM11130
- BCM11140
- BCM11351
- BCM28145
- BCM28155
-
-Required Properties
--------------------
-- compatible: "brcm,bcm11351-i2c", "brcm,kona-i2c"
-- reg: Physical base address and length of controller registers
-- interrupts: The interrupt number used by the controller
-- clocks: clock specifier for the kona i2c external clock
-- clock-frequency: The I2C bus frequency in Hz
-- #address-cells: Should be <1>
-- #size-cells: Should be <0>
-
-Refer to clocks/clock-bindings.txt for generic clock consumer
-properties.
-
-Example:
-
-i2c@3e016000 {
- compatible = "brcm,bcm11351-i2c","brcm,kona-i2c";
- reg = <0x3e016000 0x80>;
- interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&bsc1_clk>;
- clock-frequency = <400000>;
- #address-cells = <1>;
- #size-cells = <0>;
-};
diff --git a/Bindings/i2c/brcm,kona-i2c.yaml b/Bindings/i2c/brcm,kona-i2c.yaml
new file mode 100644
index 0000000..7a694af
--- /dev/null
+++ b/Bindings/i2c/brcm,kona-i2c.yaml
@@ -0,0 +1,59 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/brcm,kona-i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Broadcom Kona family I2C controller
+
+maintainers:
+ - Florian Fainelli <f.fainelli@gmail.com>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - brcm,bcm11351-i2c
+ - brcm,bcm21664-i2c
+ - brcm,bcm23550-i2c
+ - const: brcm,kona-i2c
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-frequency:
+ enum: [ 100000, 400000, 1000000, 3400000 ]
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-frequency
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ i2c@3e016000 {
+ compatible = "brcm,bcm11351-i2c", "brcm,kona-i2c";
+ reg = <0x3e016000 0x80>;
+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&bsc1_clk>;
+ clock-frequency = <400000>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+...
diff --git a/Bindings/i2c/cdns,i2c-r1p10.yaml b/Bindings/i2c/cdns,i2c-r1p10.yaml
index 2e95cda..cb24d7b 100644
--- a/Bindings/i2c/cdns,i2c-r1p10.yaml
+++ b/Bindings/i2c/cdns,i2c-r1p10.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/i2c/cdns,i2c-r1p10.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Cadence I2C controller
@@ -24,6 +24,9 @@
clocks:
minItems: 1
+ resets:
+ maxItems: 1
+
interrupts:
maxItems: 1
@@ -38,6 +41,13 @@
description: |
Input clock name.
+ fifo-depth:
+ description:
+ Size of the data FIFO in bytes.
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 16
+ enum: [2, 4, 8, 16, 32, 64, 128, 256]
+
required:
- compatible
- reg
@@ -52,9 +62,11 @@
i2c@e0004000 {
compatible = "cdns,i2c-r1p10";
clocks = <&clkc 38>;
+ resets = <&rstc 288>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
reg = <0xe0004000 0x1000>;
clock-frequency = <400000>;
#address-cells = <1>;
#size-cells = <0>;
+ fifo-depth = <8>;
};
diff --git a/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml b/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml
index cf52361..ab151c9 100644
--- a/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml
+++ b/Bindings/i2c/google,cros-ec-i2c-tunnel.yaml
@@ -39,7 +39,7 @@
examples:
- |
- spi0 {
+ spi {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/i2c/i2c-mpc.yaml b/Bindings/i2c/i2c-mpc.yaml
index 018e1b9..70fb69b 100644
--- a/Bindings/i2c/i2c-mpc.yaml
+++ b/Bindings/i2c/i2c-mpc.yaml
@@ -43,6 +43,7 @@
fsl,timeout:
$ref: /schemas/types.yaml#/definitions/uint32
+ deprecated: true
description: |
I2C bus timeout in microseconds
@@ -95,6 +96,6 @@
interrupts = <43 2>;
interrupt-parent = <&mpic>;
clock-frequency = <400000>;
- fsl,timeout = <10000>;
+ i2c-scl-clk-low-timeout-us = <10000>;
};
...
diff --git a/Bindings/i2c/i2c-mt65xx.yaml b/Bindings/i2c/i2c-mt65xx.yaml
index 72ae2e0..fda0467 100644
--- a/Bindings/i2c/i2c-mt65xx.yaml
+++ b/Bindings/i2c/i2c-mt65xx.yaml
@@ -23,6 +23,7 @@
- const: mediatek,mt6577-i2c
- const: mediatek,mt6589-i2c
- const: mediatek,mt7622-i2c
+ - const: mediatek,mt7981-i2c
- const: mediatek,mt7986-i2c
- const: mediatek,mt8168-i2c
- const: mediatek,mt8173-i2c
@@ -47,6 +48,10 @@
- const: mediatek,mt8168-i2c
- items:
- enum:
+ - mediatek,mt6795-i2c
+ - const: mediatek,mt8173-i2c
+ - items:
+ - enum:
- mediatek,mt8195-i2c
- const: mediatek,mt8192-i2c
diff --git a/Bindings/i2c/i2c-mux-gpio.yaml b/Bindings/i2c/i2c-mux-gpio.yaml
index 6e0a568..f34cc7a 100644
--- a/Bindings/i2c/i2c-mux-gpio.yaml
+++ b/Bindings/i2c/i2c-mux-gpio.yaml
@@ -45,7 +45,7 @@
i2c-parent:
description: phandle of the I2C bus that this multiplexer's master-side port is connected to
- $ref: "/schemas/types.yaml#/definitions/phandle"
+ $ref: /schemas/types.yaml#/definitions/phandle
mux-gpios:
description: list of GPIOs used to control the muxer
@@ -55,7 +55,7 @@
idle-state:
description: Value to set the muxer to when idle. When no value is given, it defaults to the
last value used.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
allOf:
- $ref: i2c-mux.yaml
diff --git a/Bindings/i2c/qcom,i2c-geni-qcom.yaml b/Bindings/i2c/qcom,i2c-geni-qcom.yaml
index 0e88c85..9f66a3b 100644
--- a/Bindings/i2c/qcom,i2c-geni-qcom.yaml
+++ b/Bindings/i2c/qcom,i2c-geni-qcom.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/i2c/qcom,i2c-geni-qcom.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Geni based QUP I2C Controller
diff --git a/Bindings/i2c/renesas,rzv2m.yaml b/Bindings/i2c/renesas,rzv2m.yaml
index 92e8999..5d1e788 100644
--- a/Bindings/i2c/renesas,rzv2m.yaml
+++ b/Bindings/i2c/renesas,rzv2m.yaml
@@ -7,7 +7,7 @@
title: Renesas RZ/V2M I2C Bus Interface
maintainers:
- - Phil Edworthy <phil.edworthy@renesas.com>
+ - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
allOf:
- $ref: /schemas/i2c/i2c-controller.yaml#
diff --git a/Bindings/i2c/samsung,s3c2410-i2c.yaml b/Bindings/i2c/samsung,s3c2410-i2c.yaml
index 3d5782d..b204e35 100644
--- a/Bindings/i2c/samsung,s3c2410-i2c.yaml
+++ b/Bindings/i2c/samsung,s3c2410-i2c.yaml
@@ -37,7 +37,7 @@
for "samsung,s3c2440-hdmiphy-i2c" whose input/output lines are
permanently wired to the respective client.
This property is deprecated. Use "pinctrl-0" and "pinctrl-names" instead.
- deprecated: yes
+ deprecated: true
interrupts:
maxItems: 1
diff --git a/Bindings/i2c/st,stm32-i2c.yaml b/Bindings/i2c/st,stm32-i2c.yaml
index bf396e9..94b75d9 100644
--- a/Bindings/i2c/st,stm32-i2c.yaml
+++ b/Bindings/i2c/st,stm32-i2c.yaml
@@ -90,7 +90,7 @@
st,syscfg-fmp:
description: Use to set Fast Mode Plus bit within SYSCFG when Fast Mode
Plus speed is selected by slave.
- $ref: "/schemas/types.yaml#/definitions/phandle-array"
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
- items:
- description: phandle to syscfg
diff --git a/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml b/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
index 1b59863..658ae92 100644
--- a/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+++ b/Bindings/i2c/xlnx,xps-iic-2.00.a.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/i2c/xlnx,xps-iic-2.00.a.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx IIC controller
diff --git a/Bindings/i3c/aspeed,ast2600-i3c.yaml b/Bindings/i3c/aspeed,ast2600-i3c.yaml
new file mode 100644
index 0000000..fcc3dbf
--- /dev/null
+++ b/Bindings/i3c/aspeed,ast2600-i3c.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i3c/aspeed,ast2600-i3c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ASPEED AST2600 i3c controller
+
+maintainers:
+ - Jeremy Kerr <jk@codeconstruct.com.au>
+
+allOf:
+ - $ref: i3c.yaml#
+
+properties:
+ compatible:
+ const: aspeed,ast2600-i3c
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ resets:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ sda-pullup-ohms:
+ enum: [545, 750, 2000]
+ default: 2000
+ description: |
+ Value to configure SDA pullup resistor, in Ohms.
+
+ aspeed,global-regs:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ items:
+ - items:
+ - description: phandle to i3c global register syscon node
+ - description: index of this i3c controller in the global register set
+ description: |
+ A (phandle, controller index) reference to the i3c global register set
+ used for this device.
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - interrupts
+ - aspeed,global-regs
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i3c-master@2000 {
+ compatible = "aspeed,ast2600-i3c";
+ reg = <0x2000 0x1000>;
+ #address-cells = <3>;
+ #size-cells = <0>;
+ clocks = <&syscon 0>;
+ resets = <&syscon 0>;
+ aspeed,global-regs = <&i3c_global 0>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i3c1_default>;
+ interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
+ };
+...
diff --git a/Bindings/iio/adc/renesas,rcar-gyroadc.yaml b/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
index c115e2e..1c7aee5 100644
--- a/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
+++ b/Bindings/iio/adc/renesas,rcar-gyroadc.yaml
@@ -34,9 +34,11 @@
clock-names:
const: fck
- power-domains: true
+ power-domains:
+ maxItems: 1
- resets: true
+ resets:
+ maxItems: 1
"#address-cells":
const: 1
@@ -51,6 +53,8 @@
- reg
- clocks
- clock-names
+ - power-domains
+ - resets
- "#address-cells"
- "#size-cells"
@@ -108,36 +112,30 @@
examples:
- |
- #include <dt-bindings/clock/r8a7791-clock.h>
+ #include <dt-bindings/clock/r8a7791-cpg-mssr.h>
#include <dt-bindings/power/r8a7791-sysc.h>
- soc {
- #address-cells = <2>;
- #size-cells = <2>;
- adc@e6e54000 {
- compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
- reg = <0 0xe6e54000 0 64>;
- clocks = <&mstp9_clks R8A7791_CLK_GYROADC>;
- clock-names = "fck";
- power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ adc@e6e54000 {
+ compatible = "renesas,r8a7791-gyroadc", "renesas,rcar-gyroadc";
+ reg = <0xe6e54000 64>;
+ clocks = <&cpg CPG_MOD 901>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
+ resets = <&cpg 901>;
- pinctrl-0 = <&adc_pins>;
- pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
- #address-cells = <1>;
- #size-cells = <0>;
+ adc@0 {
+ reg = <0>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
+ };
- adc@0 {
- reg = <0>;
- compatible = "maxim,max1162";
- vref-supply = <&vref_max1162>;
- };
-
- adc@1 {
- reg = <1>;
- compatible = "maxim,max1162";
- vref-supply = <&vref_max1162>;
- };
+ adc@1 {
+ reg = <1>;
+ compatible = "maxim,max1162";
+ vref-supply = <&vref_max1162>;
};
};
...
diff --git a/Bindings/iio/adc/ti,ads1100.yaml b/Bindings/iio/adc/ti,ads1100.yaml
new file mode 100644
index 0000000..970ccab
--- /dev/null
+++ b/Bindings/iio/adc/ti,ads1100.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/adc/ti,ads1100.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: TI ADS1100/ADS1000 single channel I2C analog to digital converter
+
+maintainers:
+ - Mike Looijmans <mike.looijmans@topic.nl>
+
+description: |
+ Datasheet at: https://www.ti.com/lit/gpn/ads1100
+
+properties:
+ compatible:
+ enum:
+ - ti,ads1100
+ - ti,ads1000
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+ "#io-channel-cells":
+ const: 0
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ adc@49 {
+ compatible = "ti,ads1100";
+ reg = <0x49>;
+ };
+ };
+...
diff --git a/Bindings/iio/addac/adi,ad74413r.yaml b/Bindings/iio/addac/adi,ad74413r.yaml
index 9eb3ecc..590ea79 100644
--- a/Bindings/iio/addac/adi,ad74413r.yaml
+++ b/Bindings/iio/addac/adi,ad74413r.yaml
@@ -101,6 +101,15 @@
When not configured as a comparator, the GPO will be treated as an
output-only GPIO.
+ drive-strength-microamp:
+ description: |
+ For channels configured as digital input, this configures the sink
+ current.
+ minimum: 0
+ maximum: 1800
+ default: 0
+ multipleOf: 120
+
required:
- reg
diff --git a/Bindings/iio/imu/st,lsm6dsx.yaml b/Bindings/iio/imu/st,lsm6dsx.yaml
index decf022..b39f521 100644
--- a/Bindings/iio/imu/st,lsm6dsx.yaml
+++ b/Bindings/iio/imu/st,lsm6dsx.yaml
@@ -46,6 +46,9 @@
- items:
- const: st,ism330is
- const: st,lsm6dso16is
+ - items:
+ - const: st,asm330lhb
+ - const: st,asm330lhh
reg:
maxItems: 1
diff --git a/Bindings/iio/light/rohm,bu27034.yaml b/Bindings/iio/light/rohm,bu27034.yaml
new file mode 100644
index 0000000..30a109a
--- /dev/null
+++ b/Bindings/iio/light/rohm,bu27034.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iio/light/rohm,bu27034.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BU27034 ambient light sensor
+
+maintainers:
+ - Matti Vaittinen <mazziesaccount@gmail.com>
+
+description: |
+ ROHM BU27034 is an ambient light sesnor with 3 channels and 3 photo diodes
+ capable of detecting a very wide range of illuminance. Typical application
+ is adjusting LCD and backlight power of TVs and mobile phones.
+ https://fscdn.rohm.com/en/products/databook/datasheet/ic/sensor/light/bu27034nuc-e.pdf
+
+properties:
+ compatible:
+ const: rohm,bu27034
+
+ reg:
+ maxItems: 1
+
+ vdd-supply: true
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ light-sensor@38 {
+ compatible = "rohm,bu27034";
+ reg = <0x38>;
+ vdd-supply = <&vdd>;
+ };
+ };
+
+...
diff --git a/Bindings/iio/pressure/bmp085.yaml b/Bindings/iio/pressure/bmp085.yaml
index 63885af..6fda887 100644
--- a/Bindings/iio/pressure/bmp085.yaml
+++ b/Bindings/iio/pressure/bmp085.yaml
@@ -17,6 +17,7 @@
https://www.bosch-sensortec.com/bst/products/all_products/bmp280
https://www.bosch-sensortec.com/bst/products/all_products/bme280
https://www.bosch-sensortec.com/bst/products/all_products/bmp380
+ https://www.bosch-sensortec.com/bst/products/all_products/bmp580
properties:
compatible:
@@ -26,6 +27,7 @@
- bosch,bmp280
- bosch,bme280
- bosch,bmp380
+ - bosch,bmp580
reg:
maxItems: 1
diff --git a/Bindings/iio/st,st-sensors.yaml b/Bindings/iio/st,st-sensors.yaml
index c620197..1ff3afc 100644
--- a/Bindings/iio/st,st-sensors.yaml
+++ b/Bindings/iio/st,st-sensors.yaml
@@ -11,9 +11,6 @@
what type of sensor it is.
Note that whilst this covers many STMicro MEMs sensors, some more complex
IMUs need their own bindings.
- The STMicroelectronics sensor devices are pretty straight-forward I2C or
- SPI devices, all sharing the same device tree descriptions no matter what
- type of sensor it is.
maintainers:
- Denis Ciocca <denis.ciocca@st.com>
@@ -48,6 +45,9 @@
- st,lsm330d-accel
- st,lsm330dl-accel
- st,lsm330dlc-accel
+ - items:
+ - const: st,iis328dq
+ - const: st,h3lis331dl-accel
- description: Silan Accelerometers
enum:
- silan,sc7a20
diff --git a/Bindings/iio/temperature/adi,ltc2983.yaml b/Bindings/iio/temperature/adi,ltc2983.yaml
index f44fc32..dbb8513 100644
--- a/Bindings/iio/temperature/adi,ltc2983.yaml
+++ b/Bindings/iio/temperature/adi,ltc2983.yaml
@@ -18,6 +18,28 @@
https://www.analog.com/media/en/technical-documentation/data-sheets/29861fa.pdf
https://www.analog.com/media/en/technical-documentation/data-sheets/ltm2985.pdf
+$defs:
+ sensor-node:
+ type: object
+ description: Sensor node common constraints
+
+ properties:
+ reg:
+ description:
+ Channel number. Connects the sensor to the channel with this number
+ of the device.
+ minimum: 1
+ maximum: 20
+
+ adi,sensor-type:
+ description: Type of sensor connected to the device.
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ required:
+ - reg
+ - adi,sensor-type
+
+
properties:
compatible:
oneOf:
@@ -64,28 +86,10 @@
const: 0
patternProperties:
- "@([0-9a-f]+)$":
- type: object
- description: Sensor.
-
- properties:
- reg:
- description:
- Channel number. Connects the sensor to the channel with this number
- of the device.
- minimum: 1
- maximum: 20
-
- adi,sensor-type:
- description: Type of sensor connected to the device.
- $ref: /schemas/types.yaml#/definitions/uint32
-
- required:
- - reg
- - adi,sensor-type
-
"^thermocouple@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
+
description: Thermocouple sensor.
properties:
@@ -123,7 +127,7 @@
description:
Used for digitizing custom thermocouples.
See Page 59 of the datasheet.
- $ref: /schemas/types.yaml#/definitions/uint64-matrix
+ $ref: /schemas/types.yaml#/definitions/int64-matrix
minItems: 3
maxItems: 64
items:
@@ -141,7 +145,9 @@
- adi,custom-thermocouple
"^diode@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
+
description: Diode sensor.
properties:
@@ -184,7 +190,8 @@
default: 0
"^rtd@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
description: RTD sensor.
properties:
@@ -282,7 +289,8 @@
- adi,custom-rtd
"^thermistor@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
description: Thermistor sensor.
properties:
@@ -383,7 +391,8 @@
- adi,custom-thermistor
"^adc@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
description: Direct ADC sensor.
properties:
@@ -397,7 +406,8 @@
type: boolean
"^temp@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
description: Active analog temperature sensor.
properties:
@@ -426,7 +436,8 @@
- adi,custom-temp
"^rsense@":
- type: object
+ $ref: '#/$defs/sensor-node'
+ unevaluatedProperties: false
description: Sense resistor sensor.
properties:
diff --git a/Bindings/iio/temperature/ti,tmp117.yaml b/Bindings/iio/temperature/ti,tmp117.yaml
index c4f1c69..8c6d773 100644
--- a/Bindings/iio/temperature/ti,tmp117.yaml
+++ b/Bindings/iio/temperature/ti,tmp117.yaml
@@ -7,9 +7,10 @@
title: TI TMP117 - Digital temperature sensor with integrated NV memory
description: |
- TI TMP117 - Digital temperature sensor with integrated NV memory that supports
- I2C interface.
- https://www.ti.com/lit/gpn/tmp1
+ TI TMP116/117 - Digital temperature sensor with integrated NV memory that
+ supports I2C interface.
+ https://www.ti.com/lit/gpn/tmp116
+ https://www.ti.com/lit/gpn/tmp117
maintainers:
- Puranjay Mohan <puranjay12@gmail.com>
@@ -17,6 +18,7 @@
properties:
compatible:
enum:
+ - ti,tmp116
- ti,tmp117
reg:
diff --git a/Bindings/input/adc-joystick.yaml b/Bindings/input/adc-joystick.yaml
index da0f8df..6c244d6 100644
--- a/Bindings/input/adc-joystick.yaml
+++ b/Bindings/input/adc-joystick.yaml
@@ -2,8 +2,8 @@
# Copyright 2019-2020 Artur Rojek
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/input/adc-joystick.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/input/adc-joystick.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ADC attached joystick
diff --git a/Bindings/input/google,cros-ec-keyb.yaml b/Bindings/input/google,cros-ec-keyb.yaml
index e05690b..fefaaf4 100644
--- a/Bindings/input/google,cros-ec-keyb.yaml
+++ b/Bindings/input/google,cros-ec-keyb.yaml
@@ -45,7 +45,7 @@
when the keyboard has a custom design for the top row keys.
dependencies:
- function-row-phsymap: [ 'linux,keymap' ]
+ function-row-physmap: [ 'linux,keymap' ]
google,needs-ghost-filter: [ 'linux,keymap' ]
required:
@@ -57,7 +57,7 @@
contains:
const: google,cros-ec-keyb
then:
- $ref: "/schemas/input/matrix-keymap.yaml#"
+ $ref: /schemas/input/matrix-keymap.yaml#
required:
- keypad,num-rows
- keypad,num-columns
diff --git a/Bindings/input/imx-keypad.yaml b/Bindings/input/imx-keypad.yaml
index 7514df6..b110eb1 100644
--- a/Bindings/input/imx-keypad.yaml
+++ b/Bindings/input/imx-keypad.yaml
@@ -10,7 +10,7 @@
- Liu Ying <gnuiyl@gmail.com>
allOf:
- - $ref: "/schemas/input/matrix-keymap.yaml#"
+ - $ref: /schemas/input/matrix-keymap.yaml#
description: |
The KPP is designed to interface with a keypad matrix with 2-point contact
diff --git a/Bindings/input/matrix-keymap.yaml b/Bindings/input/matrix-keymap.yaml
index 4d6dbe9..a715c2a 100644
--- a/Bindings/input/matrix-keymap.yaml
+++ b/Bindings/input/matrix-keymap.yaml
@@ -21,7 +21,7 @@
properties:
linux,keymap:
- $ref: '/schemas/types.yaml#/definitions/uint32-array'
+ $ref: /schemas/types.yaml#/definitions/uint32-array
description: |
An array of packed 1-cell entries containing the equivalent of row,
column and linux key-code. The 32-bit big endian cell is packed as:
diff --git a/Bindings/input/mediatek,mt6779-keypad.yaml b/Bindings/input/mediatek,mt6779-keypad.yaml
index d768c30..47aac87 100644
--- a/Bindings/input/mediatek,mt6779-keypad.yaml
+++ b/Bindings/input/mediatek,mt6779-keypad.yaml
@@ -10,7 +10,7 @@
- Mattijs Korpershoek <mkorpershoek@baylibre.com>
allOf:
- - $ref: "/schemas/input/matrix-keymap.yaml#"
+ - $ref: /schemas/input/matrix-keymap.yaml#
description: |
Mediatek's Keypad controller is used to interface a SoC with a matrix-type
diff --git a/Bindings/input/microchip,cap11xx.yaml b/Bindings/input/microchip,cap11xx.yaml
index 5fa625b..5b5d4f7 100644
--- a/Bindings/input/microchip,cap11xx.yaml
+++ b/Bindings/input/microchip,cap11xx.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/input/microchip,cap11xx.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/input/microchip,cap11xx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip CAP11xx based capacitive touch sensors
diff --git a/Bindings/input/pwm-beeper.txt b/Bindings/input/pwm-beeper.txt
deleted file mode 100644
index 8fc0e48..0000000
--- a/Bindings/input/pwm-beeper.txt
+++ /dev/null
@@ -1,24 +0,0 @@
-* PWM beeper device tree bindings
-
-Registers a PWM device as beeper.
-
-Required properties:
-- compatible: should be "pwm-beeper"
-- pwms: phandle to the physical PWM device
-
-Optional properties:
-- amp-supply: phandle to a regulator that acts as an amplifier for the beeper
-- beeper-hz: bell frequency in Hz
-
-Example:
-
-beeper_amp: amplifier {
- compatible = "fixed-regulator";
- gpios = <&gpio0 1 GPIO_ACTIVE_HIGH>;
-};
-
-beeper {
- compatible = "pwm-beeper";
- pwms = <&pwm0>;
- amp-supply = <&beeper_amp>;
-};
diff --git a/Bindings/input/pwm-beeper.yaml b/Bindings/input/pwm-beeper.yaml
new file mode 100644
index 0000000..a7611c2
--- /dev/null
+++ b/Bindings/input/pwm-beeper.yaml
@@ -0,0 +1,41 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/input/pwm-beeper.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: PWM beeper
+
+maintainers:
+ - Sascha Hauer <s.hauer@pengutronix.de>
+
+properties:
+ compatible:
+ const: pwm-beeper
+
+ pwms:
+ maxItems: 1
+
+ amp-supply:
+ description: an amplifier for the beeper
+
+ beeper-hz:
+ description: bell frequency in Hz
+ minimum: 10
+ maximum: 10000
+
+required:
+ - compatible
+ - pwms
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+ beeper {
+ compatible = "pwm-beeper";
+ pwms = <&pwm0>;
+ amp-supply = <&beeper_amp>;
+ beeper-hz = <1000>;
+ };
diff --git a/Bindings/input/pwm-vibrator.yaml b/Bindings/input/pwm-vibrator.yaml
index a70a636..d32716c 100644
--- a/Bindings/input/pwm-vibrator.yaml
+++ b/Bindings/input/pwm-vibrator.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/input/pwm-vibrator.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/input/pwm-vibrator.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: PWM vibrator
diff --git a/Bindings/input/regulator-haptic.yaml b/Bindings/input/regulator-haptic.yaml
index 627891e..cf63f83 100644
--- a/Bindings/input/regulator-haptic.yaml
+++ b/Bindings/input/regulator-haptic.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/input/regulator-haptic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/input/regulator-haptic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Regulator Haptic
diff --git a/Bindings/input/snvs-pwrkey.txt b/Bindings/input/snvs-pwrkey.txt
deleted file mode 100644
index 70c1425..0000000
--- a/Bindings/input/snvs-pwrkey.txt
+++ /dev/null
@@ -1 +0,0 @@
-See Documentation/devicetree/bindings/crypto/fsl-sec4.txt
diff --git a/Bindings/input/touchscreen/elan,elants_i2c.yaml b/Bindings/input/touchscreen/elan,elants_i2c.yaml
index f9053e5..3255c2c 100644
--- a/Bindings/input/touchscreen/elan,elants_i2c.yaml
+++ b/Bindings/input/touchscreen/elan,elants_i2c.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/input/touchscreen/elan,elants_i2c.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Elantech I2C Touchscreen
diff --git a/Bindings/interconnect/qcom,msm8998-bwmon.yaml b/Bindings/interconnect/qcom,msm8998-bwmon.yaml
index 12a0d3e..5d17bdc 100644
--- a/Bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -22,14 +22,14 @@
properties:
compatible:
oneOf:
+ - const: qcom,msm8998-bwmon # BWMON v4
- items:
- enum:
- qcom,sc7280-cpu-bwmon
- qcom,sc8280xp-cpu-bwmon
- - qcom,sdm845-bwmon
+ - qcom,sdm845-cpu-bwmon
- qcom,sm8550-cpu-bwmon
- - const: qcom,msm8998-bwmon
- - const: qcom,msm8998-bwmon # BWMON v4
+ - const: qcom,sdm845-bwmon # BWMON v4, unified register space
- items:
- enum:
- qcom,sc8280xp-llcc-bwmon
@@ -49,9 +49,13 @@
type: object
reg:
- # BWMON v4 (currently described) and BWMON v5 use one register address
- # space. BWMON v2 uses two register spaces - not yet described.
- maxItems: 1
+ # BWMON v5 uses one register address space, v1-v4 use one or two.
+ minItems: 1
+ maxItems: 2
+
+ reg-names:
+ minItems: 1
+ maxItems: 2
required:
- compatible
@@ -63,13 +67,36 @@
additionalProperties: false
+allOf:
+ - if:
+ properties:
+ compatible:
+ const: qcom,msm8998-bwmon
+ then:
+ properties:
+ reg:
+ minItems: 2
+
+ reg-names:
+ items:
+ - const: monitor
+ - const: global
+
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
+ reg-names:
+ maxItems: 1
+
examples:
- |
#include <dt-bindings/interconnect/qcom,sdm845.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pmu@1436400 {
- compatible = "qcom,sdm845-bwmon", "qcom,msm8998-bwmon";
+ compatible = "qcom,sdm845-cpu-bwmon", "qcom,sdm845-bwmon";
reg = <0x01436400 0x600>;
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
interconnects = <&gladiator_noc MASTER_APPSS_PROC 3 &mem_noc SLAVE_LLCC 3>;
diff --git a/Bindings/interconnect/qcom,osm-l3.yaml b/Bindings/interconnect/qcom,osm-l3.yaml
index 576992a..9d0a98d 100644
--- a/Bindings/interconnect/qcom,osm-l3.yaml
+++ b/Bindings/interconnect/qcom,osm-l3.yaml
@@ -29,6 +29,7 @@
- enum:
- qcom,sc7280-epss-l3
- qcom,sc8280xp-epss-l3
+ - qcom,sm6375-cpucp-l3
- qcom,sm8250-epss-l3
- qcom,sm8350-epss-l3
- const: qcom,epss-l3
diff --git a/Bindings/interconnect/qcom,rpm.yaml b/Bindings/interconnect/qcom,rpm.yaml
index d9d243c..4f95d51 100644
--- a/Bindings/interconnect/qcom,rpm.yaml
+++ b/Bindings/interconnect/qcom,rpm.yaml
@@ -66,6 +66,7 @@
patternProperties:
'^interconnect-[a-z0-9]+$':
type: object
+ additionalProperties: false
description:
snoc-mm is a child of snoc, sharing snoc's register address space.
diff --git a/Bindings/interrupt-controller/actions,owl-sirq.yaml b/Bindings/interrupt-controller/actions,owl-sirq.yaml
index 5da333c..27756d0 100644
--- a/Bindings/interrupt-controller/actions,owl-sirq.yaml
+++ b/Bindings/interrupt-controller/actions,owl-sirq.yaml
@@ -32,7 +32,7 @@
The first cell is the input IRQ number, between 0 and 2, while the second
cell is the trigger type as defined in interrupt.txt in this directory.
- 'interrupts':
+ interrupts:
description: |
Contains the GIC SPI IRQs mapped to the external interrupt lines.
They shall be specified sequentially from output 0 to 2.
@@ -44,7 +44,7 @@
- reg
- interrupt-controller
- '#interrupt-cells'
- - 'interrupts'
+ - interrupts
additionalProperties: false
diff --git a/Bindings/interrupt-controller/apple,aic2.yaml b/Bindings/interrupt-controller/apple,aic2.yaml
index 06948c0..2bde6cc 100644
--- a/Bindings/interrupt-controller/apple,aic2.yaml
+++ b/Bindings/interrupt-controller/apple,aic2.yaml
@@ -31,19 +31,22 @@
properties:
compatible:
items:
- - const: apple,t6000-aic
+ - enum:
+ - apple,t8112-aic
+ - apple,t6000-aic
- const: apple,aic2
interrupt-controller: true
'#interrupt-cells':
- const: 4
+ minimum: 3
+ maximum: 4
description: |
The 1st cell contains the interrupt type:
- 0: Hardware IRQ
- 1: FIQ
- The 2nd cell contains the die ID.
+ The 2nd cell contains the die ID (only present on apple,t6000-aic).
The next cell contains the interrupt number.
- HW IRQs: interrupt number
@@ -109,6 +112,19 @@
allOf:
- $ref: /schemas/interrupt-controller.yaml#
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: apple,t8112-aic
+ then:
+ properties:
+ '#interrupt-cells':
+ const: 3
+ else:
+ properties:
+ '#interrupt-cells':
+ const: 4
examples:
- |
diff --git a/Bindings/interrupt-controller/arm,gic-v3.yaml b/Bindings/interrupt-controller/arm,gic-v3.yaml
index 8449e14..9211726 100644
--- a/Bindings/interrupt-controller/arm,gic-v3.yaml
+++ b/Bindings/interrupt-controller/arm,gic-v3.yaml
@@ -133,12 +133,14 @@
ppi-partitions:
type: object
+ additionalProperties: false
description:
PPI affinity can be expressed as a single "ppi-partitions" node,
containing a set of sub-nodes.
patternProperties:
"^interrupt-partition-[0-9]+$":
type: object
+ additionalProperties: false
properties:
affinity:
$ref: /schemas/types.yaml#/definitions/phandle-array
diff --git a/Bindings/interrupt-controller/arm,gic.yaml b/Bindings/interrupt-controller/arm,gic.yaml
index 2202569..a2846e4 100644
--- a/Bindings/interrupt-controller/arm,gic.yaml
+++ b/Bindings/interrupt-controller/arm,gic.yaml
@@ -133,8 +133,8 @@
- items: # for "arm,cortex-a9-gic"
- const: PERIPHCLK
- const: PERIPHCLKEN
- - const: clk # for "arm,gic-400" and "nvidia,tegra210"
- - const: gclk #for "arm,pl390"
+ - const: clk # for "arm,gic-400" and "nvidia,tegra210"
+ - const: gclk # for "arm,pl390"
power-domains:
maxItems: 1
diff --git a/Bindings/interrupt-controller/fsl,irqsteer.yaml b/Bindings/interrupt-controller/fsl,irqsteer.yaml
index bcb5e20..20ad4ad 100644
--- a/Bindings/interrupt-controller/fsl,irqsteer.yaml
+++ b/Bindings/interrupt-controller/fsl,irqsteer.yaml
@@ -48,13 +48,13 @@
const: 1
fsl,channel:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
u32 value representing the output channel that all input IRQs should be
steered into.
fsl,num-irqs:
- $ref: '/schemas/types.yaml#/definitions/uint32'
+ $ref: /schemas/types.yaml#/definitions/uint32
description: |
u32 value representing the number of input interrupts of this channel,
should be multiple of 32 input interrupts and up to 512 interrupts.
diff --git a/Bindings/interrupt-controller/intel,ce4100-ioapic.yaml b/Bindings/interrupt-controller/intel,ce4100-ioapic.yaml
index 39ab8cd..a3ac818 100644
--- a/Bindings/interrupt-controller/intel,ce4100-ioapic.yaml
+++ b/Bindings/interrupt-controller/intel,ce4100-ioapic.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-ioapic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
diff --git a/Bindings/interrupt-controller/intel,ce4100-lapic.yaml b/Bindings/interrupt-controller/intel,ce4100-lapic.yaml
index d2d0145..6b20a5f 100644
--- a/Bindings/interrupt-controller/intel,ce4100-lapic.yaml
+++ b/Bindings/interrupt-controller/intel,ce4100-lapic.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ce4100-lapic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel Local Advanced Programmable Interrupt Controller (LAPIC)
diff --git a/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml b/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
index 14dced1..a02a6b5 100644
--- a/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
+++ b/Bindings/interrupt-controller/intel,ixp4xx-interrupt.yaml
@@ -2,8 +2,8 @@
# Copyright 2018 Linaro Ltd.
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/intel,ixp4xx-interrupt.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Intel IXP4xx XScale Networking Processors Interrupt Controller
diff --git a/Bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml b/Bindings/interrupt-controller/loongson,cpu-interrupt-controller.yaml
similarity index 72%
rename from Bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
rename to Bindings/interrupt-controller/loongson,cpu-interrupt-controller.yaml
index 2a1cf88..adf9899 100644
--- a/Bindings/interrupt-controller/loongarch,cpu-interrupt-controller.yaml
+++ b/Bindings/interrupt-controller/loongson,cpu-interrupt-controller.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/interrupt-controller/loongarch,cpu-interrupt-controller.yaml#
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,cpu-interrupt-controller.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: LoongArch CPU Interrupt Controller
@@ -11,7 +11,7 @@
properties:
compatible:
- const: loongarch,cpu-interrupt-controller
+ const: loongson,cpu-interrupt-controller
'#interrupt-cells':
const: 1
@@ -28,7 +28,7 @@
examples:
- |
interrupt-controller {
- compatible = "loongarch,cpu-interrupt-controller";
+ compatible = "loongson,cpu-interrupt-controller";
#interrupt-cells = <1>;
interrupt-controller;
};
diff --git a/Bindings/interrupt-controller/loongson,htpic.yaml b/Bindings/interrupt-controller/loongson,htpic.yaml
index d6bc1a6..f0acd56 100644
--- a/Bindings/interrupt-controller/loongson,htpic.yaml
+++ b/Bindings/interrupt-controller/loongson,htpic.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-3 HyperTransport Interrupt Controller
diff --git a/Bindings/interrupt-controller/loongson,htvec.yaml b/Bindings/interrupt-controller/loongson,htvec.yaml
index 87a7455..1d14576 100644
--- a/Bindings/interrupt-controller/loongson,htvec.yaml
+++ b/Bindings/interrupt-controller/loongson,htvec.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,htvec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson-3 HyperTransport Interrupt Vector Controller
diff --git a/Bindings/interrupt-controller/loongson,liointc.yaml b/Bindings/interrupt-controller/loongson,liointc.yaml
index 750cc44..00b570c 100644
--- a/Bindings/interrupt-controller/loongson,liointc.yaml
+++ b/Bindings/interrupt-controller/loongson,liointc.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson Local I/O Interrupt Controller
@@ -54,7 +54,7 @@
'#interrupt-cells':
const: 2
- 'loongson,parent_int_map':
+ loongson,parent_int_map:
description: |
This property points how the children interrupts will be mapped into CPU
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
@@ -71,7 +71,7 @@
- interrupts
- interrupt-controller
- '#interrupt-cells'
- - 'loongson,parent_int_map'
+ - loongson,parent_int_map
unevaluatedProperties: false
diff --git a/Bindings/interrupt-controller/loongson,pch-msi.yaml b/Bindings/interrupt-controller/loongson,pch-msi.yaml
index 1f6fd73..a71fc22 100644
--- a/Bindings/interrupt-controller/loongson,pch-msi.yaml
+++ b/Bindings/interrupt-controller/loongson,pch-msi.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-msi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson PCH MSI Controller
@@ -25,7 +25,7 @@
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH MSI.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 255
@@ -33,7 +33,7 @@
description:
u32 value of the number of parent HyperTransport vectors allocated
to PCH MSI.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 1
maximum: 256
@@ -46,7 +46,7 @@
- loongson,msi-base-vec
- loongson,msi-num-vecs
-additionalProperties: true #fixme
+additionalProperties: true # fixme
examples:
- |
diff --git a/Bindings/interrupt-controller/loongson,pch-pic.yaml b/Bindings/interrupt-controller/loongson,pch-pic.yaml
index fdd6a38..b7bc5cb 100644
--- a/Bindings/interrupt-controller/loongson,pch-pic.yaml
+++ b/Bindings/interrupt-controller/loongson,pch-pic.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/loongson,pch-pic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Loongson PCH PIC Controller
@@ -25,7 +25,7 @@
description:
u32 value of the base of parent HyperTransport vector allocated
to PCH PIC.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 192
diff --git a/Bindings/interrupt-controller/mediatek,sysirq.txt b/Bindings/interrupt-controller/mediatek,sysirq.txt
index 84ced3f..3ffc601 100644
--- a/Bindings/interrupt-controller/mediatek,sysirq.txt
+++ b/Bindings/interrupt-controller/mediatek,sysirq.txt
@@ -25,6 +25,7 @@
"mediatek,mt6577-sysirq": for MT6577
"mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712
"mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701
+ "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365
- interrupt-controller : Identifies the node as an interrupt controller
- #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
- reg: Physical base address of the intpol registers and length of memory
diff --git a/Bindings/interrupt-controller/mrvl,intc.yaml b/Bindings/interrupt-controller/mrvl,intc.yaml
index 9acc210..b7c5022 100644
--- a/Bindings/interrupt-controller/mrvl,intc.yaml
+++ b/Bindings/interrupt-controller/mrvl,intc.yaml
@@ -53,8 +53,8 @@
maxItems: 1
reg-names:
items:
- - const: 'mux status'
- - const: 'mux mask'
+ - const: mux status
+ - const: mux mask
required:
- interrupts
else:
diff --git a/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml b/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
index 27b798b..4ff609f 100644
--- a/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
+++ b/Bindings/interrupt-controller/mscc,ocelot-icpu-intr.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microsemi Ocelot SoC ICPU Interrupt Controller
diff --git a/Bindings/interrupt-controller/qcom,pdc.yaml b/Bindings/interrupt-controller/qcom,pdc.yaml
index 94791e2..a106ba6 100644
--- a/Bindings/interrupt-controller/qcom,pdc.yaml
+++ b/Bindings/interrupt-controller/qcom,pdc.yaml
@@ -26,6 +26,8 @@
compatible:
items:
- enum:
+ - qcom,qdu1000-pdc
+ - qcom,sa8775p-pdc
- qcom,sc7180-pdc
- qcom,sc7280-pdc
- qcom,sc8280xp-pdc
@@ -53,7 +55,7 @@
qcom,pdc-ranges:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
- maxItems: 32 # no hard limit
+ maxItems: 128 # no hard limit
items:
items:
- description: starting PDC port
diff --git a/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 63bc89e..f75736a 100644
--- a/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -59,6 +59,7 @@
- enum:
- sifive,fu540-c000-plic
- starfive,jh7100-plic
+ - starfive,jh7110-plic
- canaan,k210-plic
- const: sifive,plic-1.0.0
- items:
@@ -90,7 +91,7 @@
riscv,cpu-intc node, which has a riscv node as parent.
riscv,ndev:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Specifies how many external interrupts are supported by this controller.
diff --git a/Bindings/interrupt-controller/st,sti-irq-syscfg.txt b/Bindings/interrupt-controller/st,sti-irq-syscfg.txt
index ced6014..977d7ed 100644
--- a/Bindings/interrupt-controller/st,sti-irq-syscfg.txt
+++ b/Bindings/interrupt-controller/st,sti-irq-syscfg.txt
@@ -6,11 +6,7 @@
This driver is used to unmask them prior to use.
Required properties:
-- compatible : Should be set to one of:
- "st,stih415-irq-syscfg"
- "st,stih416-irq-syscfg"
- "st,stih407-irq-syscfg"
- "st,stid127-irq-syscfg"
+- compatible : Should be "st,stih407-irq-syscfg"
- st,syscfg : Phandle to Cortex-A9 IRQ system config registers
- st,irq-device : Array of IRQs to enable - should be 2 in length
- st,fiq-device : Array of FIQs to enable - should be 2 in length
@@ -25,11 +21,10 @@
Example:
irq-syscfg {
- compatible = "st,stih416-irq-syscfg";
+ compatible = "st,stih407-irq-syscfg";
st,syscfg = <&syscfg_cpu>;
st,irq-device = <ST_IRQ_SYSCFG_PMU_0>,
<ST_IRQ_SYSCFG_PMU_1>;
st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
<ST_IRQ_SYSCFG_DISABLED>;
- st,invert-ext = <(ST_IRQ_SYSCFG_EXT_1_INV | ST_IRQ_SYSCFG_EXT_3_INV)>;
};
diff --git a/Bindings/interrupt-controller/ti,sci-inta.yaml b/Bindings/interrupt-controller/ti,sci-inta.yaml
index 1151518..6a49d74 100644
--- a/Bindings/interrupt-controller/ti,sci-inta.yaml
+++ b/Bindings/interrupt-controller/ti,sci-inta.yaml
@@ -85,6 +85,9 @@
description:
Array of phandles to DMA controllers where the unmapped events originate.
+ power-domains:
+ maxItems: 1
+
required:
- compatible
- reg
diff --git a/Bindings/iommu/apple,sart.yaml b/Bindings/iommu/apple,sart.yaml
index 1524fa3..e87c152 100644
--- a/Bindings/iommu/apple,sart.yaml
+++ b/Bindings/iommu/apple,sart.yaml
@@ -28,9 +28,13 @@
properties:
compatible:
- enum:
- - apple,t6000-sart
- - apple,t8103-sart
+ oneOf:
+ - items:
+ - const: apple,t8112-sart
+ - const: apple,t6000-sart
+ - enum:
+ - apple,t6000-sart
+ - apple,t8103-sart
reg:
maxItems: 1
diff --git a/Bindings/iommu/arm,smmu.yaml b/Bindings/iommu/arm,smmu.yaml
index 807cb51..ba677d4 100644
--- a/Bindings/iommu/arm,smmu.yaml
+++ b/Bindings/iommu/arm,smmu.yaml
@@ -53,6 +53,7 @@
- qcom,sm8250-smmu-500
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
+ - qcom,sm8550-smmu-500
- const: qcom,smmu-500
- const: arm,mmu-500
@@ -75,11 +76,24 @@
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
- const: arm,mmu-500
-
- - description: Qcom Adreno GPUs implementing "arm,smmu-500"
+ - description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
items:
- enum:
- qcom,sc7280-smmu-500
+ - qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
+ - qcom,sm8150-smmu-500
+ - qcom,sm8250-smmu-500
+ - qcom,sm8350-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+ - description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
+ deprecated: true
+ items:
+ # Do not add additional SoC to this list. Instead use previous list.
+ - enum:
+ - qcom,sc7280-smmu-500
- qcom,sm8150-smmu-500
- qcom,sm8250-smmu-500
- const: qcom,adreno-smmu
@@ -364,6 +378,30 @@
- description: interface clock required to access smmu's registers
through the TCU's programming interface.
+ - if:
+ properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,sm6115-smmu-500
+ - qcom,sm6125-smmu-500
+ - const: qcom,adreno-smmu
+ - const: qcom,smmu-500
+ - const: arm,mmu-500
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: mem
+ - const: hlos
+ - const: iface
+
+ clocks:
+ items:
+ - description: GPU memory bus clock
+ - description: Voter clock required for HLOS SMMU access
+ - description: Interface clock required for register access
+
# Disallow clocks for all other platforms with specific compatibles
- if:
properties:
@@ -383,12 +421,11 @@
- qcom,sdm845-smmu-500
- qcom,sdx55-smmu-500
- qcom,sdx65-smmu-500
- - qcom,sm6115-smmu-500
- - qcom,sm6125-smmu-500
- qcom,sm6350-smmu-500
- qcom,sm6375-smmu-500
- qcom,sm8350-smmu-500
- qcom,sm8450-smmu-500
+ - qcom,sm8550-smmu-500
then:
properties:
clock-names: false
diff --git a/Bindings/iommu/qcom,iommu.txt b/Bindings/iommu/qcom,iommu.txt
deleted file mode 100644
index e6cecfd..0000000
--- a/Bindings/iommu/qcom,iommu.txt
+++ /dev/null
@@ -1,122 +0,0 @@
-* QCOM IOMMU v1 Implementation
-
-Qualcomm "B" family devices which are not compatible with arm-smmu have
-a similar looking IOMMU but without access to the global register space,
-and optionally requiring additional configuration to route context irqs
-to non-secure vs secure interrupt line.
-
-** Required properties:
-
-- compatible : Should be one of:
-
- "qcom,msm8916-iommu"
- "qcom,msm8953-iommu"
-
- Followed by "qcom,msm-iommu-v1".
-
-- clock-names : Should be a pair of "iface" (required for IOMMUs
- register group access) and "bus" (required for
- the IOMMUs underlying bus access).
-
-- clocks : Phandles for respective clocks described by
- clock-names.
-
-- #address-cells : must be 1.
-
-- #size-cells : must be 1.
-
-- #iommu-cells : Must be 1. Index identifies the context-bank #.
-
-- ranges : Base address and size of the iommu context banks.
-
-- qcom,iommu-secure-id : secure-id.
-
-- List of sub-nodes, one per translation context bank. Each sub-node
- has the following required properties:
-
- - compatible : Should be one of:
- - "qcom,msm-iommu-v1-ns" : non-secure context bank
- - "qcom,msm-iommu-v1-sec" : secure context bank
- - reg : Base address and size of context bank within the iommu
- - interrupts : The context fault irq.
-
-** Optional properties:
-
-- reg : Base address and size of the SMMU local base, should
- be only specified if the iommu requires configuration
- for routing of context bank irq's to secure vs non-
- secure lines. (Ie. if the iommu contains secure
- context banks)
-
-
-** Examples:
-
- apps_iommu: iommu@1e20000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #iommu-cells = <1>;
- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
- ranges = <0 0x1e20000 0x40000>;
- reg = <0x1ef0000 0x3000>;
- clocks = <&gcc GCC_SMMU_CFG_CLK>,
- <&gcc GCC_APSS_TCU_CLK>;
- clock-names = "iface", "bus";
- qcom,iommu-secure-id = <17>;
-
- // mdp_0:
- iommu-ctx@4000 {
- compatible = "qcom,msm-iommu-v1-ns";
- reg = <0x4000 0x1000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- // venus_ns:
- iommu-ctx@5000 {
- compatible = "qcom,msm-iommu-v1-sec";
- reg = <0x5000 0x1000>;
- interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- gpu_iommu: iommu@1f08000 {
- #address-cells = <1>;
- #size-cells = <1>;
- #iommu-cells = <1>;
- compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
- ranges = <0 0x1f08000 0x10000>;
- clocks = <&gcc GCC_SMMU_CFG_CLK>,
- <&gcc GCC_GFX_TCU_CLK>;
- clock-names = "iface", "bus";
- qcom,iommu-secure-id = <18>;
-
- // gfx3d_user:
- iommu-ctx@1000 {
- compatible = "qcom,msm-iommu-v1-ns";
- reg = <0x1000 0x1000>;
- interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
- };
-
- // gfx3d_priv:
- iommu-ctx@2000 {
- compatible = "qcom,msm-iommu-v1-ns";
- reg = <0x2000 0x1000>;
- interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>;
- };
- };
-
- ...
-
- venus: video-codec@1d00000 {
- ...
- iommus = <&apps_iommu 5>;
- };
-
- mdp: mdp@1a01000 {
- ...
- iommus = <&apps_iommu 4>;
- };
-
- gpu@1c00000 {
- ...
- iommus = <&gpu_iommu 1>, <&gpu_iommu 2>;
- };
diff --git a/Bindings/iommu/qcom,iommu.yaml b/Bindings/iommu/qcom,iommu.yaml
new file mode 100644
index 0000000..d9fabdf
--- /dev/null
+++ b/Bindings/iommu/qcom,iommu.yaml
@@ -0,0 +1,113 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Technologies legacy IOMMU implementations
+
+maintainers:
+ - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description: |
+ Qualcomm "B" family devices which are not compatible with arm-smmu have
+ a similar looking IOMMU, but without access to the global register space
+ and optionally requiring additional configuration to route context IRQs
+ to non-secure vs secure interrupt line.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,msm8916-iommu
+ - qcom,msm8953-iommu
+ - const: qcom,msm-iommu-v1
+
+ clocks:
+ items:
+ - description: Clock required for IOMMU register group access
+ - description: Clock required for underlying bus access
+
+ clock-names:
+ items:
+ - const: iface
+ - const: bus
+
+ power-domains:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ ranges: true
+
+ qcom,iommu-secure-id:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The SCM secure ID of the IOMMU instance.
+
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 1
+
+ '#iommu-cells':
+ const: 1
+
+patternProperties:
+ "^iommu-ctx@[0-9a-f]+$":
+ type: object
+ additionalProperties: false
+ properties:
+ compatible:
+ enum:
+ - qcom,msm-iommu-v1-ns
+ - qcom,msm-iommu-v1-sec
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+ required:
+ - compatible
+ - interrupts
+ - reg
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - ranges
+ - '#address-cells'
+ - '#size-cells'
+ - '#iommu-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8916.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ apps_iommu: iommu@1e20000 {
+ compatible = "qcom,msm8916-iommu", "qcom,msm-iommu-v1";
+ reg = <0x01ef0000 0x3000>;
+ clocks = <&gcc GCC_SMMU_CFG_CLK>,
+ <&gcc GCC_APSS_TCU_CLK>;
+ clock-names = "iface", "bus";
+ qcom,iommu-secure-id = <17>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #iommu-cells = <1>;
+ ranges = <0 0x01e20000 0x40000>;
+
+ /* mdp_0: */
+ iommu-ctx@4000 {
+ compatible = "qcom,msm-iommu-v1-ns";
+ reg = <0x4000 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
+ };
+ };
diff --git a/Bindings/iommu/renesas,ipmmu-vmsa.yaml b/Bindings/iommu/renesas,ipmmu-vmsa.yaml
index 72308a4..be90f68 100644
--- a/Bindings/iommu/renesas,ipmmu-vmsa.yaml
+++ b/Bindings/iommu/renesas,ipmmu-vmsa.yaml
@@ -74,16 +74,16 @@
renesas,ipmmu-main:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
- - items:
+ - minItems: 1
+ items:
- description: phandle to main IPMMU
- - description: the interrupt bit number associated with the particular
- cache IPMMU device. The interrupt bit number needs to match the main
- IPMMU IMSSTR register. Only used by cache IPMMU instances.
+ - description:
+ The interrupt bit number associated with the particular cache
+ IPMMU device. If present, the interrupt bit number needs to match
+ the main IPMMU IMSSTR register. Only used by cache IPMMU
+ instances.
description:
- Reference to the main IPMMU phandle plus 1 cell. The cell is
- the interrupt bit number associated with the particular cache IPMMU
- device. The interrupt bit number needs to match the main IPMMU IMSSTR
- register. Only used by cache IPMMU instances.
+ Reference to the main IPMMU.
required:
- compatible
@@ -109,6 +109,22 @@
required:
- power-domains
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,rcar-gen4-ipmmu-vmsa
+ then:
+ properties:
+ renesas,ipmmu-main:
+ items:
+ - maxItems: 1
+ else:
+ properties:
+ renesas,ipmmu-main:
+ items:
+ - minItems: 2
+
examples:
- |
#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
diff --git a/Bindings/leds/common.yaml b/Bindings/leds/common.yaml
index 15e3f66..11aedf1 100644
--- a/Bindings/leds/common.yaml
+++ b/Bindings/leds/common.yaml
@@ -90,22 +90,51 @@
- heartbeat
# LED indicates disk activity
- disk-activity
+ # LED indicates disk read activity
- disk-read
+ # LED indicates disk write activity
- disk-write
# LED flashes at a fixed, configurable rate
- timer
# LED alters the brightness for the specified duration with one software
# timer (requires "led-pattern" property)
- pattern
+ # LED indicates mic mute state
+ - audio-micmute
+ # LED indicates audio mute state
+ - audio-mute
+ # LED indicates bluetooth power state
+ - bluetooth-power
+ # LED indicates activity of all CPUs
+ - cpu
+ # LED indicates camera flash state
+ - flash
+ # LED indicated keyboard capslock
+ - kbd-capslock
+ # LED indicates MTD memory activity
+ - mtd
+ # LED indicates NAND memory activity (deprecated),
+ # in new implementations use "mtd"
+ - nand-disk
+ # No trigger assigned to the LED. This is the default mode
+ # if trigger is absent
+ - none
+ # LED indicates camera torch state
+ - torch
+ # LED indicates USB gadget activity
- usb-gadget
+ # LED indicates USB host activity
- usb-host
+ # LED indicates USB port state
+ - usbport
+ # LED is triggered by CPU activity
- pattern: "^cpu[0-9]*$"
- - pattern: "^hci[0-9]+-power$"
# LED is triggered by Bluetooth activity
- - pattern: "^mmc[0-9]+$"
+ - pattern: "^hci[0-9]+-power$"
# LED is triggered by SD/MMC activity
- - pattern: "^phy[0-9]+tx$"
+ - pattern: "^mmc[0-9]+$"
# LED is triggered by WLAN activity
+ - pattern: "^phy[0-9]+tx$"
led-pattern:
description: |
diff --git a/Bindings/leds/cznic,turris-omnia-leds.yaml b/Bindings/leds/cznic,turris-omnia-leds.yaml
index 14bebe1..34ef521 100644
--- a/Bindings/leds/cznic,turris-omnia-leds.yaml
+++ b/Bindings/leds/cznic,turris-omnia-leds.yaml
@@ -58,7 +58,7 @@
#include <dt-bindings/leds/common.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/leds/issi,is31fl319x.yaml b/Bindings/leds/issi,is31fl319x.yaml
index d1b01ba..3c0431c 100644
--- a/Bindings/leds/issi,is31fl319x.yaml
+++ b/Bindings/leds/issi,is31fl319x.yaml
@@ -165,7 +165,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/leds/leds-aw2013.yaml b/Bindings/leds/leds-aw2013.yaml
index 6c3ea0f..08f3e1c 100644
--- a/Bindings/leds/leds-aw2013.yaml
+++ b/Bindings/leds/leds-aw2013.yaml
@@ -54,7 +54,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/leds/leds-pca9532.txt b/Bindings/leds/leds-pca9532.txt
deleted file mode 100644
index f769c52..0000000
--- a/Bindings/leds/leds-pca9532.txt
+++ /dev/null
@@ -1,49 +0,0 @@
-*NXP - pca9532 PWM LED Driver
-
-The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
-The PWM support 256 steps.
-
-Required properties:
- - compatible:
- "nxp,pca9530"
- "nxp,pca9531"
- "nxp,pca9532"
- "nxp,pca9533"
- - reg - I2C slave address
-
-Each led is represented as a sub-node of the nxp,pca9530.
-
-Optional sub-node properties:
- - label: see Documentation/devicetree/bindings/leds/common.txt
- - type: Output configuration, see dt-bindings/leds/leds-pca9532.h (default NONE)
- - linux,default-trigger: see Documentation/devicetree/bindings/leds/common.txt
- - default-state: see Documentation/devicetree/bindings/leds/common.txt
- This property is only valid for sub-nodes of type <PCA9532_TYPE_LED>.
-
-Example:
- #include <dt-bindings/leds/leds-pca9532.h>
-
- leds: pca9530@60 {
- compatible = "nxp,pca9530";
- reg = <0x60>;
-
- red-power {
- label = "pca:red:power";
- type = <PCA9532_TYPE_LED>;
- };
- green-power {
- label = "pca:green:power";
- type = <PCA9532_TYPE_LED>;
- };
- kernel-booting {
- type = <PCA9532_TYPE_LED>;
- default-state = "on";
- };
- sys-stat {
- type = <PCA9532_TYPE_LED>;
- default-state = "keep"; // don't touch, was set by U-Boot
- };
- };
-
-For more product information please see the link below:
-http://nxp.com/documents/data_sheet/PCA9532.pdf
diff --git a/Bindings/leds/leds-qcom-lpg.yaml b/Bindings/leds/leds-qcom-lpg.yaml
index 1df8377..6295c91 100644
--- a/Bindings/leds/leds-qcom-lpg.yaml
+++ b/Bindings/leds/leds-qcom-lpg.yaml
@@ -27,6 +27,7 @@
- qcom,pmc8180c-lpg
- qcom,pmi8994-lpg
- qcom,pmi8998-lpg
+ - qcom,pmk8550-pwm
"#pwm-cells":
const: 2
diff --git a/Bindings/leds/leds-rt4505.yaml b/Bindings/leds/leds-rt4505.yaml
index cb71fec..bfd0e24 100644
--- a/Bindings/leds/leds-rt4505.yaml
+++ b/Bindings/leds/leds-rt4505.yaml
@@ -39,7 +39,7 @@
- |
#include <dt-bindings/leds/common.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/leds/nxp,pca953x.yaml b/Bindings/leds/nxp,pca953x.yaml
new file mode 100644
index 0000000..edf6f55
--- /dev/null
+++ b/Bindings/leds/nxp,pca953x.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/nxp,pca953x.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: NXP PCA9532 LED Dimmer
+
+maintainers:
+ - Riku Voipio <riku.voipio@iki.fi>
+
+description: |
+ The PCA9532 family is SMBus I/O expander optimized for dimming LEDs.
+ The PWM support 256 steps.
+
+ For more product information please see the link below:
+ https://www.nxp.com/docs/en/data-sheet/PCA9532.pdf
+
+properties:
+ compatible:
+ enum:
+ - nxp,pca9530
+ - nxp,pca9531
+ - nxp,pca9532
+ - nxp,pca9533
+
+ reg:
+ maxItems: 1
+
+ gpio-controller: true
+
+ '#gpio-cells':
+ const: 2
+
+patternProperties:
+ "^led-[0-9a-z]+$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ type:
+ description: |
+ Output configuration, see include/dt-bindings/leds/leds-pca9532.h
+ $ref: /schemas/types.yaml#/definitions/uint32
+ default: 0
+ minimum: 0
+ maximum: 4
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/leds-pca9532.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@62 {
+ compatible = "nxp,pca9533";
+ reg = <0x62>;
+
+ led-1 {
+ label = "pca:red:power";
+ type = <PCA9532_TYPE_LED>;
+ };
+
+ led-2 {
+ label = "pca:green:power";
+ type = <PCA9532_TYPE_LED>;
+ };
+
+ led-3 {
+ type = <PCA9532_TYPE_LED>;
+ default-state = "on";
+ };
+
+ led-4 {
+ type = <PCA9532_TYPE_LED>;
+ default-state = "keep";
+ };
+ };
+ };
+
+...
diff --git a/Bindings/leds/qcom,spmi-flash-led.yaml b/Bindings/leds/qcom,spmi-flash-led.yaml
new file mode 100644
index 0000000..ffacf70
--- /dev/null
+++ b/Bindings/leds/qcom,spmi-flash-led.yaml
@@ -0,0 +1,117 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/qcom,spmi-flash-led.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Flash LED device inside Qualcomm Technologies, Inc. PMICs
+
+maintainers:
+ - Fenglin Wu <quic_fenglinw@quicinc.com>
+
+description: |
+ Flash LED controller is present inside some Qualcomm Technologies, Inc. PMICs.
+ The flash LED module can have different number of LED channels supported
+ e.g. 3 or 4. There are some different registers between them but they can
+ both support maximum current up to 1.5 A per channel and they can also support
+ ganging 2 channels together to supply maximum current up to 2 A. The current
+ will be split symmetrically on each channel and they will be enabled and
+ disabled at the same time.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,pm6150l-flash-led
+ - qcom,pm8150c-flash-led
+ - qcom,pm8150l-flash-led
+ - qcom,pm8350c-flash-led
+ - const: qcom,spmi-flash-led
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^led-[0-3]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+ description:
+ Represents the physical LED components which are connected to the
+ flash LED channels' output.
+
+ properties:
+ led-sources:
+ description:
+ The HW indices of the flash LED channels that connect to the
+ physical LED
+ allOf:
+ - minItems: 1
+ maxItems: 2
+ items:
+ enum: [1, 2, 3, 4]
+
+ led-max-microamp:
+ anyOf:
+ - minimum: 5000
+ maximum: 500000
+ multipleOf: 5000
+ - minimum: 10000
+ maximum: 1000000
+ multipleOf: 10000
+
+ flash-max-microamp:
+ anyOf:
+ - minimum: 12500
+ maximum: 1500000
+ multipleOf: 12500
+ - minimum: 25000
+ maximum: 2000000
+ multipleOf: 25000
+
+ flash-max-timeout-us:
+ minimum: 10000
+ maximum: 1280000
+ multipleOf: 10000
+
+ required:
+ - led-sources
+ - led-max-microamp
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+ spmi {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ led-controller@ee00 {
+ compatible = "qcom,pm8350c-flash-led", "qcom,spmi-flash-led";
+ reg = <0xee00>;
+
+ led-0 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_WHITE>;
+ led-sources = <1>, <4>;
+ led-max-microamp = <300000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <0>;
+ };
+
+ led-1 {
+ function = LED_FUNCTION_FLASH;
+ color = <LED_COLOR_ID_YELLOW>;
+ led-sources = <2>, <3>;
+ led-max-microamp = <300000>;
+ flash-max-microamp = <2000000>;
+ flash-max-timeout-us = <1280000>;
+ function-enumerator = <1>;
+ };
+ };
+ };
diff --git a/Bindings/leds/rohm,bd2606mvv.yaml b/Bindings/leds/rohm,bd2606mvv.yaml
new file mode 100644
index 0000000..14700a2
--- /dev/null
+++ b/Bindings/leds/rohm,bd2606mvv.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/leds/rohm,bd2606mvv.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ROHM BD2606MVV LED controller
+
+maintainers:
+ - Andreas Kemnade <andreas@kemnade.info>
+
+description:
+ The BD2606 MVV is a programmable LED controller connected via I2C that can
+ drive 6 separate lines. Each of them can be individually switched on and off,
+ but the brightness setting is shared between pairs of them.
+
+ Datasheet is available at
+ https://fscdn.rohm.com/en/products/databook/datasheet/ic/power/led_driver/bd2606mvv_1-e.pdf
+
+properties:
+ compatible:
+ const: rohm,bd2606mvv
+
+ reg:
+ maxItems: 1
+
+ "#address-cells":
+ const: 1
+
+ "#size-cells":
+ const: 0
+
+ enable-gpios:
+ maxItems: 1
+ description: GPIO pin to enable/disable the device.
+
+patternProperties:
+ "^led@[0-6]$":
+ type: object
+ $ref: common.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ reg:
+ minimum: 0
+ maximum: 6
+
+ required:
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/leds/common.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led-controller@66 {
+ compatible = "rohm,bd2606mvv";
+ reg = <0x66>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ led@0 {
+ reg = <0x0>;
+ color = <LED_COLOR_ID_RED>;
+ function = LED_FUNCTION_POWER;
+ };
+
+ led@2 {
+ reg = <0x2>;
+ color = <LED_COLOR_ID_WHITE>;
+ function = LED_FUNCTION_STATUS;
+ };
+ };
+ };
+
+...
diff --git a/Bindings/leds/ti,tca6507.yaml b/Bindings/leds/ti,tca6507.yaml
index 9ce5c0f..4b1575e 100644
--- a/Bindings/leds/ti,tca6507.yaml
+++ b/Bindings/leds/ti,tca6507.yaml
@@ -87,7 +87,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/leds/common.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml b/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
index dfd26b9..385809e 100644
--- a/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
+++ b/Bindings/mailbox/amlogic,meson-gxbb-mhu.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/amlogic,meson-gxbb-mhu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson Message-Handling-Unit Controller
diff --git a/Bindings/mailbox/apple,mailbox.yaml b/Bindings/mailbox/apple,mailbox.yaml
index 5c5c328..4c0668e 100644
--- a/Bindings/mailbox/apple,mailbox.yaml
+++ b/Bindings/mailbox/apple,mailbox.yaml
@@ -29,6 +29,7 @@
items:
- enum:
- apple,t8103-asc-mailbox
+ - apple,t8112-asc-mailbox
- apple,t6000-asc-mailbox
- const: apple,asc-mailbox-v4
@@ -39,6 +40,7 @@
items:
- enum:
- apple,t8103-m3-mailbox
+ - apple,t8112-m3-mailbox
- apple,t6000-m3-mailbox
- const: apple,m3-mailbox-v2
diff --git a/Bindings/mailbox/mediatek,gce-mailbox.yaml b/Bindings/mailbox/mediatek,gce-mailbox.yaml
index d383b2a..cef9d76 100644
--- a/Bindings/mailbox/mediatek,gce-mailbox.yaml
+++ b/Bindings/mailbox/mediatek,gce-mailbox.yaml
@@ -16,14 +16,18 @@
properties:
compatible:
- enum:
- - mediatek,mt6779-gce
- - mediatek,mt8173-gce
- - mediatek,mt8183-gce
- - mediatek,mt8186-gce
- - mediatek,mt8188-gce
- - mediatek,mt8192-gce
- - mediatek,mt8195-gce
+ oneOf:
+ - enum:
+ - mediatek,mt6779-gce
+ - mediatek,mt8173-gce
+ - mediatek,mt8183-gce
+ - mediatek,mt8186-gce
+ - mediatek,mt8188-gce
+ - mediatek,mt8192-gce
+ - mediatek,mt8195-gce
+ - items:
+ - const: mediatek,mt6795-gce
+ - const: mediatek,mt8173-gce
"#mbox-cells":
const: 2
diff --git a/Bindings/mailbox/microchip,mpfs-mailbox.yaml b/Bindings/mailbox/microchip,mpfs-mailbox.yaml
index 935937c..4044779 100644
--- a/Bindings/mailbox/microchip,mpfs-mailbox.yaml
+++ b/Bindings/mailbox/microchip,mpfs-mailbox.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/microchip,mpfs-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) mailbox controller
diff --git a/Bindings/mailbox/qcom,apcs-kpss-global.yaml b/Bindings/mailbox/qcom,apcs-kpss-global.yaml
index d888ead..32d7bbc 100644
--- a/Bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/qcom,apcs-kpss-global.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm APCS global block
@@ -19,22 +19,15 @@
- items:
- enum:
- qcom,ipq5332-apcs-apps-global
+ - qcom,ipq8074-apcs-apps-global
+ - qcom,ipq9574-apcs-apps-global
- const: qcom,ipq6018-apcs-apps-global
- items:
- enum:
- - qcom,ipq6018-apcs-apps-global
- - qcom,ipq8074-apcs-apps-global
- - qcom,msm8996-apcs-hmss-global
- - qcom,msm8998-apcs-hmss-global
- - qcom,qcm2290-apcs-hmss-global
- qcom,sc7180-apss-shared
- qcom,sc8180x-apss-shared
- - qcom,sdm660-apcs-hmss-global
- - qcom,sdm845-apss-shared
- - qcom,sm4250-apcs-hmss-global
- - qcom,sm6125-apcs-hmss-global
- - qcom,sm6115-apcs-hmss-global
- qcom,sm8150-apss-shared
+ - const: qcom,sdm845-apss-shared
- items:
- enum:
- qcom,msm8916-apcs-kpss-global
@@ -45,6 +38,18 @@
- qcom,qcs404-apcs-apps-global
- qcom,sdx55-apcs-gcc
- const: syscon
+ - enum:
+ - qcom,ipq6018-apcs-apps-global
+ - qcom,ipq8074-apcs-apps-global
+ - qcom,msm8996-apcs-hmss-global
+ - qcom,msm8998-apcs-hmss-global
+ - qcom,qcm2290-apcs-hmss-global
+ - qcom,sdm660-apcs-hmss-global
+ - qcom,sdm845-apss-shared
+ - qcom,sm4250-apcs-hmss-global
+ - qcom,sm6115-apcs-hmss-global
+ - qcom,sm6125-apcs-hmss-global
+
reg:
maxItems: 1
@@ -88,30 +93,31 @@
items:
- const: pll
- const: aux
+
- if:
properties:
compatible:
- enum:
- - qcom,sdx55-apcs-gcc
+ contains:
+ enum:
+ - qcom,sdx55-apcs-gcc
then:
properties:
clocks:
items:
+ - description: reference clock
- description: primary pll parent of the clock driver
- description: auxiliary parent
- - description: reference clock
clock-names:
items:
+ - const: ref
- const: pll
- const: aux
- - const: ref
- if:
properties:
compatible:
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- - qcom,ipq8074-apcs-apps-global
then:
properties:
clocks:
@@ -133,14 +139,11 @@
- qcom,msm8996-apcs-hmss-global
- qcom,msm8998-apcs-hmss-global
- qcom,qcm2290-apcs-hmss-global
- - qcom,sc7180-apss-shared
- - qcom,sc8180x-apss-shared
- qcom,sdm660-apcs-hmss-global
- qcom,sdm845-apss-shared
- qcom,sm4250-apcs-hmss-global
- qcom,sm6115-apcs-hmss-global
- qcom,sm6125-apcs-hmss-global
- - qcom,sm8150-apss-shared
then:
properties:
clocks: false
@@ -152,7 +155,6 @@
contains:
enum:
- qcom,ipq6018-apcs-apps-global
- - qcom,ipq8074-apcs-apps-global
then:
properties:
'#clock-cells':
diff --git a/Bindings/mailbox/sprd-mailbox.yaml b/Bindings/mailbox/sprd-mailbox.yaml
index bdfb4a8..b526f9c 100644
--- a/Bindings/mailbox/sprd-mailbox.yaml
+++ b/Bindings/mailbox/sprd-mailbox.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/sprd-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Spreadtrum mailbox controller
diff --git a/Bindings/mailbox/st,stm32-ipcc.yaml b/Bindings/mailbox/st,stm32-ipcc.yaml
index 0dfe05a..134fd22 100644
--- a/Bindings/mailbox/st,stm32-ipcc.yaml
+++ b/Bindings/mailbox/st,stm32-ipcc.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/st,stm32-ipcc.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 IPC controller
diff --git a/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml b/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
index 2193141..374ffe6 100644
--- a/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
+++ b/Bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ipi-mailbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Xilinx IPI(Inter Processor Interrupt) mailbox controller
@@ -72,6 +72,7 @@
'^mailbox@[0-9a-f]+$':
description: Internal ipi mailbox node
type: object # DT nodes are json objects
+ additionalProperties: false
properties:
xlnx,ipi-id:
description:
diff --git a/Bindings/media/allwinner,sun4i-a10-ir.yaml b/Bindings/media/allwinner,sun4i-a10-ir.yaml
index 53945c6..42dfe22 100644
--- a/Bindings/media/allwinner,sun4i-a10-ir.yaml
+++ b/Bindings/media/allwinner,sun4i-a10-ir.yaml
@@ -11,7 +11,7 @@
- Maxime Ripard <mripard@kernel.org>
allOf:
- - $ref: "rc.yaml#"
+ - $ref: rc.yaml#
properties:
compatible:
diff --git a/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml b/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
index 9d44236..a4f06bb 100644
--- a/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
+++ b/Bindings/media/allwinner,sun50i-h6-vpu-g2.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/allwinner,sun50i-h6-vpu-g2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hantro G2 VPU codec implemented on Allwinner H6 SoC
diff --git a/Bindings/media/amlogic,axg-ge2d.yaml b/Bindings/media/amlogic,axg-ge2d.yaml
index e551be5..f23fa6d 100644
--- a/Bindings/media/amlogic,axg-ge2d.yaml
+++ b/Bindings/media/amlogic,axg-ge2d.yaml
@@ -2,8 +2,8 @@
# Copyright 2020 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/amlogic,axg-ge2d.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/amlogic,axg-ge2d.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic GE2D Acceleration Unit
diff --git a/Bindings/media/amlogic,gx-vdec.yaml b/Bindings/media/amlogic,gx-vdec.yaml
index b827eda..55930f6 100644
--- a/Bindings/media/amlogic,gx-vdec.yaml
+++ b/Bindings/media/amlogic,gx-vdec.yaml
@@ -2,8 +2,8 @@
# Copyright 2019 BayLibre, SAS
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/amlogic,gx-vdec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/amlogic,gx-vdec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Video Decoder
diff --git a/Bindings/media/amlogic,meson-ir-tx.yaml b/Bindings/media/amlogic,meson-ir-tx.yaml
index 4432fea..377acce 100644
--- a/Bindings/media/amlogic,meson-ir-tx.yaml
+++ b/Bindings/media/amlogic,meson-ir-tx.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/amlogic,meson-ir-tx.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Amlogic Meson IR transmitter
diff --git a/Bindings/media/amlogic,meson6-ir.yaml b/Bindings/media/amlogic,meson6-ir.yaml
new file mode 100644
index 0000000..3f9fa92
--- /dev/null
+++ b/Bindings/media/amlogic,meson6-ir.yaml
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/amlogic,meson6-ir.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Amlogic Meson IR remote control receiver
+
+maintainers:
+ - Neil Armstrong <neil.armstrong@linaro.org>
+
+allOf:
+ - $ref: rc.yaml#
+
+properties:
+ compatible:
+ oneOf:
+ - enum:
+ - amlogic,meson6-ir
+ - amlogic,meson8b-ir
+ - amlogic,meson-gxbb-ir
+ - items:
+ - const: amlogic,meson-gx-ir
+ - const: amlogic,meson-gxbb-ir
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - interrupts
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ ir-receiver@c8100480 {
+ compatible = "amlogic,meson6-ir";
+ reg = <0xc8100480 0x20>;
+ interrupts = <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>;
+ };
diff --git a/Bindings/media/exynos-fimc-lite.txt b/Bindings/media/exynos-fimc-lite.txt
deleted file mode 100644
index 0bf6fb7..0000000
--- a/Bindings/media/exynos-fimc-lite.txt
+++ /dev/null
@@ -1,16 +0,0 @@
-Exynos4x12/Exynos5 SoC series camera host interface (FIMC-LITE)
-
-Required properties:
-
-- compatible : should be one of:
- "samsung,exynos4212-fimc-lite" for Exynos4212/4412 SoCs,
- "samsung,exynos5250-fimc-lite" for Exynos5250 compatible
- devices;
-- reg : physical base address and size of the device memory mapped
- registers;
-- interrupts : should contain FIMC-LITE interrupt;
-- clocks : FIMC LITE gate clock should be specified in this property.
-- clock-names : should contain "flite" entry.
-
-Each FIMC device should have an alias in the aliases node, in the form of
-fimc-lite<n>, where <n> is an integer specifying the IP block instance.
diff --git a/Bindings/media/exynos4-fimc-is.txt b/Bindings/media/exynos4-fimc-is.txt
deleted file mode 100644
index 32ced99..0000000
--- a/Bindings/media/exynos4-fimc-is.txt
+++ /dev/null
@@ -1,50 +0,0 @@
-Exynos4x12 SoC series Imaging Subsystem (FIMC-IS)
-
-The FIMC-IS is a subsystem for processing image signal from an image sensor.
-The Exynos4x12 SoC series FIMC-IS V1.5 comprises of a dedicated ARM Cortex-A5
-processor, ISP, DRC and FD IP blocks and peripheral devices such as UART, I2C
-and SPI bus controllers, PWM and ADC.
-
-fimc-is node
-------------
-
-Required properties:
-- compatible : should be "samsung,exynos4212-fimc-is" for Exynos4212 and
- Exynos4412 SoCs;
-- reg : physical base address and length of the registers set;
-- interrupts : must contain two FIMC-IS interrupts, in order: ISP0, ISP1;
-- clocks : list of clock specifiers, corresponding to entries in
- clock-names property;
-- clock-names : must contain "ppmuispx", "ppmuispx", "lite0", "lite1"
- "mpll", "sysreg", "isp", "drc", "fd", "mcuisp", "gicisp",
- "pwm_isp", "mcuctl_isp", "uart", "ispdiv0", "ispdiv1",
- "mcuispdiv0", "mcuispdiv1", "aclk200", "div_aclk200",
- "aclk400mcuisp", "div_aclk400mcuisp" entries,
- matching entries in the clocks property.
-pmu subnode
------------
-
-Required properties:
- - reg : must contain PMU physical base address and size of the register set.
-
-The following are the FIMC-IS peripheral device nodes and can be specified
-either standalone or as the fimc-is node child nodes.
-
-i2c-isp (ISP I2C bus controller) nodes
-------------------------------------------
-
-Required properties:
-
-- compatible : should be "samsung,exynos4212-i2c-isp" for Exynos4212 and
- Exynos4412 SoCs;
-- reg : physical base address and length of the registers set;
-- clocks : must contain gate clock specifier for this controller;
-- clock-names : must contain "i2c_isp" entry.
-
-For the above nodes it is required to specify a pinctrl state named "default",
-according to the pinctrl bindings defined in ../pinctrl/pinctrl-bindings.txt.
-
-Device tree nodes of the image sensors' controlled directly by the FIMC-IS
-firmware must be child nodes of their corresponding ISP I2C bus controller node.
-The data link of these image sensors must be specified using the common video
-interfaces bindings, defined in video-interfaces.txt.
diff --git a/Bindings/media/gpio-ir-receiver.yaml b/Bindings/media/gpio-ir-receiver.yaml
index 6107274..008c007 100644
--- a/Bindings/media/gpio-ir-receiver.yaml
+++ b/Bindings/media/gpio-ir-receiver.yaml
@@ -23,6 +23,9 @@
description: autosuspend delay time in milliseconds
$ref: /schemas/types.yaml#/definitions/uint32
+ wakeup-source:
+ description: IR receiver can wake-up the system.
+
required:
- compatible
- gpios
diff --git a/Bindings/media/i2c/aptina,mt9p031.yaml b/Bindings/media/i2c/aptina,mt9p031.yaml
index 1d6af1b..be00de2 100644
--- a/Bindings/media/i2c/aptina,mt9p031.yaml
+++ b/Bindings/media/i2c/aptina,mt9p031.yaml
@@ -82,7 +82,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/aptina,mt9v111.yaml b/Bindings/media/i2c/aptina,mt9v111.yaml
index e53b8d6..088022f 100644
--- a/Bindings/media/i2c/aptina,mt9v111.yaml
+++ b/Bindings/media/i2c/aptina,mt9v111.yaml
@@ -55,7 +55,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/chrontel,ch7322.yaml b/Bindings/media/i2c/chrontel,ch7322.yaml
index af8ada5..4e69b6a 100644
--- a/Bindings/media/i2c/chrontel,ch7322.yaml
+++ b/Bindings/media/i2c/chrontel,ch7322.yaml
@@ -1,8 +1,8 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/i2c/chrontel,ch7322.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/i2c/chrontel,ch7322.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Chrontel HDMI-CEC Controller
diff --git a/Bindings/media/i2c/dongwoon,dw9768.yaml b/Bindings/media/i2c/dongwoon,dw9768.yaml
index 82d3d18..a0855d3 100644
--- a/Bindings/media/i2c/dongwoon,dw9768.yaml
+++ b/Bindings/media/i2c/dongwoon,dw9768.yaml
@@ -38,7 +38,7 @@
dongwoon,aac-mode:
description:
Indication of AAC mode select.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
enum:
- 1 # AAC2 mode(operation time# 0.48 x Tvib)
- 2 # AAC3 mode(operation time# 0.70 x Tvib)
@@ -50,7 +50,7 @@
description:
Number of AAC Timing count that controlled by one 6-bit period of
vibration register AACT[5:0], the unit of which is 100 us.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
default: 0x20
minimum: 0x00
maximum: 0x3f
@@ -59,7 +59,7 @@
description:
Indication of VCM internal clock dividing rate select, as one multiple
factor to calculate VCM ring periodic time Tvib.
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # Dividing Rate - 2
- 1 # Dividing Rate - 1
diff --git a/Bindings/media/i2c/imx219.yaml b/Bindings/media/i2c/imx219.yaml
index 5fc9694..07d088c 100644
--- a/Bindings/media/i2c/imx219.yaml
+++ b/Bindings/media/i2c/imx219.yaml
@@ -83,7 +83,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/imx258.yaml b/Bindings/media/i2c/imx258.yaml
index cde0f73..80d2422 100644
--- a/Bindings/media/i2c/imx258.yaml
+++ b/Bindings/media/i2c/imx258.yaml
@@ -84,7 +84,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -111,7 +111,7 @@
};
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/maxim,max9286.yaml b/Bindings/media/i2c/maxim,max9286.yaml
index 0c4213a..a374472 100644
--- a/Bindings/media/i2c/maxim,max9286.yaml
+++ b/Bindings/media/i2c/maxim,max9286.yaml
@@ -86,7 +86,7 @@
is 100000 micro volts
maxim,gpio-poc:
- $ref: '/schemas/types.yaml#/definitions/uint32-array'
+ $ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 2
maxItems: 2
description: |
@@ -156,6 +156,7 @@
patternProperties:
"^i2c@[0-3]$":
type: object
+ additionalProperties: false
description: |
Child node of the i2c bus multiplexer which represents a GMSL link.
Each serializer device on the GMSL link remote end is represented with
@@ -167,6 +168,12 @@
description: The index of the GMSL channel.
maxItems: 1
+ '#address-cells':
+ const: 1
+
+ '#size-cells':
+ const: 0
+
patternProperties:
"^camera@[a-f0-9]+$":
type: object
diff --git a/Bindings/media/i2c/mipi-ccs.yaml b/Bindings/media/i2c/mipi-ccs.yaml
index edde420..f8ace8c 100644
--- a/Bindings/media/i2c/mipi-ccs.yaml
+++ b/Bindings/media/i2c/mipi-ccs.yaml
@@ -106,7 +106,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
- i2c2 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/ov2685.txt b/Bindings/media/i2c/ov2685.txt
deleted file mode 100644
index 625c4a8..0000000
--- a/Bindings/media/i2c/ov2685.txt
+++ /dev/null
@@ -1,41 +0,0 @@
-* Omnivision OV2685 MIPI CSI-2 sensor
-
-Required Properties:
-- compatible: shall be "ovti,ov2685"
-- clocks: reference to the xvclk input clock
-- clock-names: shall be "xvclk"
-- avdd-supply: Analog voltage supply, 2.8 volts
-- dovdd-supply: Digital I/O voltage supply, 1.8 volts
-- dvdd-supply: Digital core voltage supply, 1.8 volts
-- reset-gpios: Low active reset gpio
-
-The device node shall contain one 'port' child node with an
-'endpoint' subnode for its digital output video port,
-in accordance with the video interface bindings defined in
-Documentation/devicetree/bindings/media/video-interfaces.txt.
-The endpoint optional property 'data-lanes' shall be "<1>".
-
-Example:
-&i2c7 {
- ov2685: camera-sensor@3c {
- compatible = "ovti,ov2685";
- reg = <0x3c>;
- pinctrl-names = "default";
- pinctrl-0 = <&clk_24m_cam>;
-
- clocks = <&cru SCLK_TESTCLKOUT1>;
- clock-names = "xvclk";
-
- avdd-supply = <&pp2800_cam>;
- dovdd-supply = <&pp1800>;
- dvdd-supply = <&pp1800>;
- reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
-
- port {
- ucam_out: endpoint {
- remote-endpoint = <&mipi_in_ucam>;
- data-lanes = <1>;
- };
- };
- };
-};
diff --git a/Bindings/media/i2c/ov8856.yaml b/Bindings/media/i2c/ov8856.yaml
index e17288d..57f5e48 100644
--- a/Bindings/media/i2c/ov8856.yaml
+++ b/Bindings/media/i2c/ov8856.yaml
@@ -8,7 +8,7 @@
title: Omnivision OV8856 CMOS Sensor
maintainers:
- - Dongchun Zhu <dongchun.zhu@mediatek.com>
+ - Sakari Ailus <sakari.ailus@linux.intel.com>
description: |-
The Omnivision OV8856 is a high performance, 1/4-inch, 8 megapixel, CMOS
diff --git a/Bindings/media/i2c/ovti,ov02a10.yaml b/Bindings/media/i2c/ovti,ov02a10.yaml
index 54df9d7..763cebe 100644
--- a/Bindings/media/i2c/ovti,ov02a10.yaml
+++ b/Bindings/media/i2c/ovti,ov02a10.yaml
@@ -88,7 +88,7 @@
properties:
link-frequencies: true
ovti,mipi-clock-voltage:
- $ref: "/schemas/types.yaml#/definitions/uint32"
+ $ref: /schemas/types.yaml#/definitions/uint32
description:
Definition of MIPI clock voltage unit. This entry corresponds to
the link speed defined by the 'link-frequencies' property.
diff --git a/Bindings/media/i2c/ovti,ov2685.yaml b/Bindings/media/i2c/ovti,ov2685.yaml
new file mode 100644
index 0000000..e2ffe0a
--- /dev/null
+++ b/Bindings/media/i2c/ovti,ov2685.yaml
@@ -0,0 +1,102 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/ovti,ov2685.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: OmniVision OV2685 Image Sensor
+
+maintainers:
+ - Shunqian Zheng <zhengsq@rock-chips.com>
+
+properties:
+ compatible:
+ const: ovti,ov2685
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: XVCLK clock
+
+ clock-names:
+ items:
+ - const: xvclk
+
+ dvdd-supply:
+ description: Digital Domain Power Supply
+
+ avdd-supply:
+ description: Analog Domain Power Supply
+
+ dovdd-supply:
+ description: I/O Domain Power Supply
+
+ reset-gpios:
+ maxItems: 1
+ description: Reset Pin GPIO Control (active low)
+
+ port:
+ description: MIPI CSI-2 transmitter port
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ minItems: 1
+ maxItems: 2
+
+ required:
+ - data-lanes
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - dvdd-supply
+ - avdd-supply
+ - dovdd-supply
+ - port
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/rk3399-cru.h>
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ov2685: camera-sensor@3c {
+ compatible = "ovti,ov2685";
+ reg = <0x3c>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&clk_24m_cam>;
+
+ clocks = <&cru SCLK_TESTCLKOUT1>;
+ clock-names = "xvclk";
+
+ avdd-supply = <&pp2800_cam>;
+ dovdd-supply = <&pp1800>;
+ dvdd-supply = <&pp1800>;
+ reset-gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
+
+ port {
+ ucam_out: endpoint {
+ remote-endpoint = <&mipi_in_ucam>;
+ data-lanes = <1>;
+ };
+ };
+ };
+ };
+
+...
diff --git a/Bindings/media/i2c/ovti,ov5648.yaml b/Bindings/media/i2c/ovti,ov5648.yaml
index 61e4e9c..1f49767 100644
--- a/Bindings/media/i2c/ovti,ov5648.yaml
+++ b/Bindings/media/i2c/ovti,ov5648.yaml
@@ -81,7 +81,7 @@
#include <dt-bindings/clock/sun8i-v3s-ccu.h>
#include <dt-bindings/gpio/gpio.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/ovti,ov772x.yaml b/Bindings/media/i2c/ovti,ov772x.yaml
index 161e6d5..5d24edb 100644
--- a/Bindings/media/i2c/ovti,ov772x.yaml
+++ b/Bindings/media/i2c/ovti,ov772x.yaml
@@ -107,7 +107,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
ov772x: camera@21 {
diff --git a/Bindings/media/i2c/ovti,ov8865.yaml b/Bindings/media/i2c/ovti,ov8865.yaml
index 6bac326..8a70e23 100644
--- a/Bindings/media/i2c/ovti,ov8865.yaml
+++ b/Bindings/media/i2c/ovti,ov8865.yaml
@@ -82,7 +82,7 @@
#include <dt-bindings/clock/sun8i-a83t-ccu.h>
#include <dt-bindings/gpio/gpio.h>
- i2c2 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/ovti,ov9282.yaml b/Bindings/media/i2c/ovti,ov9282.yaml
index 0c4654e..79a7658 100644
--- a/Bindings/media/i2c/ovti,ov9282.yaml
+++ b/Bindings/media/i2c/ovti,ov9282.yaml
@@ -78,7 +78,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/rda,rda5807.yaml b/Bindings/media/i2c/rda,rda5807.yaml
index f50e54a..34a05df 100644
--- a/Bindings/media/i2c/rda,rda5807.yaml
+++ b/Bindings/media/i2c/rda,rda5807.yaml
@@ -50,7 +50,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/samsung,s5k5baf.yaml b/Bindings/media/i2c/samsung,s5k5baf.yaml
new file mode 100644
index 0000000..c8f2955
--- /dev/null
+++ b/Bindings/media/i2c/samsung,s5k5baf.yaml
@@ -0,0 +1,101 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/samsung,s5k5baf.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5K5BAF UXGA 1/5" 2M CMOS Image Sensor with embedded SoC ISP
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+properties:
+ compatible:
+ const: samsung,s5k5baf
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: mclk
+
+ clock-frequency:
+ default: 24000000
+ description: mclk clock frequency
+
+ rstn-gpios:
+ maxItems: 1
+ description: RSTN pin
+
+ stbyn-gpios:
+ maxItems: 1
+ description: STDBYN pin
+
+ vdda-supply:
+ description: Analog power supply 2.8V (2.6V to 3.0V)
+
+ vddio-supply:
+ description: I/O power supply 1.8V (1.65V to 1.95V) or 2.8V (2.5V to 3.1V)
+
+ vddreg-supply:
+ description:
+ Regulator input power supply 1.8V (1.7V to 1.9V) or 2.8V (2.6V to 3.0)
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ items:
+ - const: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - rstn-gpios
+ - stbyn-gpios
+ - vdda-supply
+ - vddio-supply
+ - vddreg-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@2d {
+ compatible = "samsung,s5k5baf";
+ reg = <0x2d>;
+ clocks = <&camera 0>;
+ clock-names = "mclk";
+ clock-frequency = <24000000>;
+ rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>;
+ stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>;
+ vdda-supply = <&cam_io_en_reg>;
+ vddio-supply = <&vtcam_reg>;
+ vddreg-supply = <&vt_core_15v_reg>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&csis1_ep>;
+ data-lanes = <1>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/media/i2c/samsung,s5k6a3.yaml b/Bindings/media/i2c/samsung,s5k6a3.yaml
new file mode 100644
index 0000000..7e83a94
--- /dev/null
+++ b/Bindings/media/i2c/samsung,s5k6a3.yaml
@@ -0,0 +1,98 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/i2c/samsung,s5k6a3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung S5K6A3(YX) raw image sensor
+
+maintainers:
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ S5K6A3(YX) is a raw image sensor with MIPI CSI-2 and CCP2 image data
+ interfaces and CCI (I2C compatible) control bus.
+
+properties:
+ compatible:
+ const: samsung,s5k6a3
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: extclk
+
+ clock-frequency:
+ default: 24000000
+ description: extclk clock frequency
+
+ gpios:
+ maxItems: 1
+ description: GPIO connected to the RESET pin
+
+ afvdd-supply:
+ description: AF (actuator) voltage supply
+
+ svdda-supply:
+ description: Core voltage supply
+
+ svddio-supply:
+ description: I/O voltage supply
+
+ port:
+ $ref: /schemas/graph.yaml#/$defs/port-base
+ additionalProperties: false
+
+ properties:
+ endpoint:
+ $ref: /schemas/media/video-interfaces.yaml#
+ unevaluatedProperties: false
+
+ properties:
+ data-lanes:
+ items:
+ - const: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - gpios
+ - afvdd-supply
+ - svdda-supply
+ - svddio-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/gpio/gpio.h>
+
+ i2c {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sensor@10 {
+ compatible = "samsung,s5k6a3";
+ reg = <0x10>;
+ clock-frequency = <24000000>;
+ clocks = <&camera 1>;
+ clock-names = "extclk";
+ gpios = <&gpm1 6 GPIO_ACTIVE_LOW>;
+ afvdd-supply = <&ldo19_reg>;
+ svdda-supply = <&cam_io_reg>;
+ svddio-supply = <&ldo19_reg>;
+
+ port {
+ endpoint {
+ remote-endpoint = <&csis1_ep>;
+ data-lanes = <1>;
+ };
+ };
+ };
+ };
diff --git a/Bindings/media/i2c/sony,imx214.yaml b/Bindings/media/i2c/sony,imx214.yaml
index c9760f8..e2470dd 100644
--- a/Bindings/media/i2c/sony,imx214.yaml
+++ b/Bindings/media/i2c/sony,imx214.yaml
@@ -97,7 +97,7 @@
- |
#include <dt-bindings/gpio/gpio.h>
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/sony,imx274.yaml b/Bindings/media/i2c/sony,imx274.yaml
index 4271fc3..b397a73 100644
--- a/Bindings/media/i2c/sony,imx274.yaml
+++ b/Bindings/media/i2c/sony,imx274.yaml
@@ -52,7 +52,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/sony,imx290.yaml b/Bindings/media/i2c/sony,imx290.yaml
index 21377da..a531bad 100644
--- a/Bindings/media/i2c/sony,imx290.yaml
+++ b/Bindings/media/i2c/sony,imx290.yaml
@@ -12,15 +12,26 @@
description: |-
The Sony IMX290 is a 1/2.8-Inch CMOS Solid-state image sensor with Square
- Pixel for Color Cameras. It is programmable through I2C and 4-wire
- interfaces. The sensor output is available via CMOS logic parallel SDR
- output, Low voltage LVDS DDR output and CSI-2 serial data output. The CSI-2
- bus is the default. No bindings have been defined for the other busses.
+ Pixel, available in either mono or colour variants. It is programmable
+ through I2C and 4-wire interfaces.
+
+ The sensor output is available via CMOS logic parallel SDR output, Low voltage
+ LVDS DDR output and CSI-2 serial data output. The CSI-2 bus is the default.
+ No bindings have been defined for the other busses.
+
+ imx290lqr is the full model identifier for the colour variant. "sony,imx290"
+ is treated the same as this as it was the original compatible string.
+ imx290llr is the mono version of the sensor.
properties:
compatible:
- enum:
- - sony,imx290
+ oneOf:
+ - enum:
+ - sony,imx290lqr # Colour
+ - sony,imx290llr # Monochrome
+ - sony,imx327lqr # Colour
+ - const: sony,imx290
+ deprecated: true
reg:
maxItems: 1
@@ -101,7 +112,7 @@
#size-cells = <0>;
imx290: camera-sensor@1a {
- compatible = "sony,imx290";
+ compatible = "sony,imx290lqr";
reg = <0x1a>;
pinctrl-names = "default";
diff --git a/Bindings/media/i2c/sony,imx334.yaml b/Bindings/media/i2c/sony,imx334.yaml
index f5055b9..bce57b2 100644
--- a/Bindings/media/i2c/sony,imx334.yaml
+++ b/Bindings/media/i2c/sony,imx334.yaml
@@ -65,7 +65,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,7 +82,7 @@
imx334: endpoint {
remote-endpoint = <&cam>;
data-lanes = <1 2 3 4>;
- link-frequencies = /bits/ 64 <891000000>;
+ link-frequencies = /bits/ 64 <891000000 445500000>;
};
};
};
diff --git a/Bindings/media/i2c/sony,imx335.yaml b/Bindings/media/i2c/sony,imx335.yaml
index cf2ca27..a167dcd 100644
--- a/Bindings/media/i2c/sony,imx335.yaml
+++ b/Bindings/media/i2c/sony,imx335.yaml
@@ -66,7 +66,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/i2c/sony,imx412.yaml b/Bindings/media/i2c/sony,imx412.yaml
index 60dc25f..d9b7815 100644
--- a/Bindings/media/i2c/sony,imx412.yaml
+++ b/Bindings/media/i2c/sony,imx412.yaml
@@ -77,7 +77,7 @@
examples:
- |
- i2c0 {
+ i2c {
#address-cells = <1>;
#size-cells = <0>;
diff --git a/Bindings/media/mediatek,mdp3-rdma.yaml b/Bindings/media/mediatek,mdp3-rdma.yaml
index 9cfc0c7..7032c7e 100644
--- a/Bindings/media/mediatek,mdp3-rdma.yaml
+++ b/Bindings/media/mediatek,mdp3-rdma.yaml
@@ -27,7 +27,7 @@
maxItems: 1
mediatek,gce-client-reg:
- $ref: '/schemas/types.yaml#/definitions/phandle-array'
+ $ref: /schemas/types.yaml#/definitions/phandle-array
items:
items:
- description: phandle of GCE
diff --git a/Bindings/media/mediatek,mt8195-jpegdec.yaml b/Bindings/media/mediatek,mt8195-jpegdec.yaml
index 71595c0..e5448c6 100644
--- a/Bindings/media/mediatek,mt8195-jpegdec.yaml
+++ b/Bindings/media/mediatek,mt8195-jpegdec.yaml
@@ -26,11 +26,6 @@
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
"#address-cells":
const: 2
@@ -89,7 +84,6 @@
- compatible
- power-domains
- iommus
- - dma-ranges
- ranges
additionalProperties: false
@@ -115,7 +109,6 @@
<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
- dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
diff --git a/Bindings/media/mediatek,mt8195-jpegenc.yaml b/Bindings/media/mediatek,mt8195-jpegenc.yaml
index 9599053..5961864 100644
--- a/Bindings/media/mediatek,mt8195-jpegenc.yaml
+++ b/Bindings/media/mediatek,mt8195-jpegenc.yaml
@@ -26,11 +26,6 @@
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
"#address-cells":
const: 2
@@ -89,7 +84,6 @@
- compatible
- power-domains
- iommus
- - dma-ranges
- ranges
additionalProperties: false
@@ -113,7 +107,6 @@
<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
- dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
diff --git a/Bindings/media/mediatek,vcodec-decoder.yaml b/Bindings/media/mediatek,vcodec-decoder.yaml
index aa55ca6..fad59b4 100644
--- a/Bindings/media/mediatek,vcodec-decoder.yaml
+++ b/Bindings/media/mediatek,vcodec-decoder.yaml
@@ -56,11 +56,6 @@
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
diff --git a/Bindings/media/mediatek,vcodec-encoder.yaml b/Bindings/media/mediatek,vcodec-encoder.yaml
index 0f2ea8d..a2051b3 100644
--- a/Bindings/media/mediatek,vcodec-encoder.yaml
+++ b/Bindings/media/mediatek,vcodec-encoder.yaml
@@ -49,11 +49,6 @@
List of the hardware port in respective IOMMU block for current Socs.
Refer to bindings/iommu/mediatek,iommu.yaml.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
mediatek,vpu:
$ref: /schemas/types.yaml#/definitions/phandle
description:
diff --git a/Bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
index c4f20ac..dca9b0c 100644
--- a/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
+++ b/Bindings/media/mediatek,vcodec-subdev-decoder.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Video Decode Accelerator With Multi Hardware
@@ -61,7 +61,10 @@
- mediatek,mt8195-vcodec-dec
reg:
- maxItems: 1
+ minItems: 1
+ items:
+ - description: VDEC_SYS register space
+ - description: VDEC_RACING_CTRL register space
iommus:
minItems: 1
@@ -76,11 +79,6 @@
The node of system control processor (SCP), using
the remoteproc & rpmsg framework.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
"#address-cells":
const: 2
@@ -91,17 +89,19 @@
# Required child node:
patternProperties:
- '^vcodec-lat@[0-9a-f]+$':
+ '^video-codec@[0-9a-f]+$':
type: object
properties:
compatible:
enum:
+ - mediatek,mtk-vcodec-core
- mediatek,mtk-vcodec-lat
- mediatek,mtk-vcodec-lat-soc
reg:
maxItems: 1
+ description: VDEC_MISC register space
interrupts:
maxItems: 1
@@ -114,15 +114,12 @@
Refer to bindings/iommu/mediatek,iommu.yaml.
clocks:
+ minItems: 4
maxItems: 5
clock-names:
- items:
- - const: sel
- - const: soc-vdec
- - const: soc-lat
- - const: vdec
- - const: top
+ minItems: 4
+ maxItems: 5
assigned-clocks:
maxItems: 1
@@ -145,65 +142,11 @@
additionalProperties: false
- '^vcodec-core@[0-9a-f]+$':
- type: object
-
- properties:
- compatible:
- const: mediatek,mtk-vcodec-core
-
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
- iommus:
- minItems: 1
- maxItems: 32
- description: |
- List of the hardware port in respective IOMMU block for current Socs.
- Refer to bindings/iommu/mediatek,iommu.yaml.
-
- clocks:
- maxItems: 5
-
- clock-names:
- items:
- - const: sel
- - const: soc-vdec
- - const: soc-lat
- - const: vdec
- - const: top
-
- assigned-clocks:
- maxItems: 1
-
- assigned-clock-parents:
- maxItems: 1
-
- power-domains:
- maxItems: 1
-
- required:
- - compatible
- - reg
- - interrupts
- - iommus
- - clocks
- - clock-names
- - assigned-clocks
- - assigned-clock-parents
- - power-domains
-
- additionalProperties: false
-
required:
- compatible
- reg
- iommus
- mediatek,scp
- - dma-ranges
- ranges
if:
@@ -211,12 +154,45 @@
compatible:
contains:
enum:
+ - mediatek,mtk-vcodec-core
- mediatek,mtk-vcodec-lat
then:
required:
- interrupts
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8192-vcodec-dec
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: sel
+ - const: soc-vdec
+ - const: soc-lat
+ - const: vdec
+ - const: top
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - mediatek,mt8195-vcodec-dec
+ then:
+ properties:
+ clock-names:
+ items:
+ - const: sel
+ - const: vdec
+ - const: lat
+ - const: top
+
additionalProperties: false
examples:
@@ -236,12 +212,11 @@
compatible = "mediatek,mt8192-vcodec-dec";
mediatek,scp = <&scp>;
iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
- dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0 0 0 0x16000000 0 0x40000>;
reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */
- vcodec-lat@10000 {
+ video-codec@10000 {
compatible = "mediatek,mtk-vcodec-lat";
reg = <0 0x10000 0 0x800>;
interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
@@ -264,7 +239,7 @@
power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
};
- vcodec-core@25000 {
+ video-codec@25000 {
compatible = "mediatek,mtk-vcodec-core";
reg = <0 0x25000 0 0x1000>;
interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
diff --git a/Bindings/media/mediatek-jpeg-encoder.yaml b/Bindings/media/mediatek-jpeg-encoder.yaml
index c8412e8..37800e1 100644
--- a/Bindings/media/mediatek-jpeg-encoder.yaml
+++ b/Bindings/media/mediatek-jpeg-encoder.yaml
@@ -44,11 +44,6 @@
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
Ports are according to the HW.
- dma-ranges:
- maxItems: 1
- description: |
- Describes the physical address space of IOMMU maps to memory.
-
required:
- compatible
- reg
diff --git a/Bindings/media/meson-ir.txt b/Bindings/media/meson-ir.txt
deleted file mode 100644
index efd9d29..0000000
--- a/Bindings/media/meson-ir.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-* Amlogic Meson IR remote control receiver
-
-Required properties:
- - compatible : depending on the platform this should be one of:
- - "amlogic,meson6-ir"
- - "amlogic,meson8b-ir"
- - "amlogic,meson-gxbb-ir"
- - reg : physical base address and length of the device registers
- - interrupts : a single specifier for the interrupt from the device
-
-Optional properties:
- - linux,rc-map-name: see rc.txt file in the same directory.
-
-Example:
-
- ir-receiver@c8100480 {
- compatible= "amlogic,meson6-ir";
- reg = <0xc8100480 0x20>;
- interrupts = <0 15 1>;
- };
diff --git a/Bindings/media/microchip,sama5d4-vdec.yaml b/Bindings/media/microchip,sama5d4-vdec.yaml
index 4b77103..59b805c 100644
--- a/Bindings/media/microchip,sama5d4-vdec.yaml
+++ b/Bindings/media/microchip,sama5d4-vdec.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/microchip,sama5d4-vdec.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hantro G1 VPU codec implemented on Microchip SAMA5D4 SoCs
diff --git a/Bindings/media/nxp,imx8-isi.yaml b/Bindings/media/nxp,imx8-isi.yaml
new file mode 100644
index 0000000..6038b9b
--- /dev/null
+++ b/Bindings/media/nxp,imx8-isi.yaml
@@ -0,0 +1,173 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/media/nxp,imx8-isi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: i.MX8 Image Sensing Interface
+
+maintainers:
+ - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+description: |
+ The Image Sensing Interface (ISI) combines image processing pipelines with
+ DMA engines to process and capture frames originating from a variety of
+ sources. The inputs to the ISI go through Pixel Link interfaces, and their
+ number and nature is SoC-dependent. They cover both capture interfaces (MIPI
+ CSI-2 RX, HDMI RX, ...) and display engine outputs for writeback support.
+
+properties:
+ compatible:
+ enum:
+ - fsl,imx8mn-isi
+ - fsl,imx8mp-isi
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ items:
+ - description: The AXI clock
+ - description: The APB clock
+ # TODO: Check if the per-channel ipg_proc_clk clocks need to be specified
+ # as well, in case some SoCs have the ability to control them separately.
+ # This may be the case of the i.MX8[DQ]X(P)
+
+ clock-names:
+ items:
+ - const: axi
+ - const: apb
+
+ fsl,blk-ctrl:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ A phandle referencing the block control that contains the CSIS to ISI
+ gasket.
+
+ interrupts:
+ description: Processing pipeline interrupts, one per pipeline
+ minItems: 1
+ maxItems: 2
+
+ power-domains:
+ maxItems: 1
+
+ ports:
+ $ref: /schemas/graph.yaml#/properties/ports
+ description: |
+ Ports represent the Pixel Link inputs to the ISI. Their number and
+ assignment are model-dependent. Each port shall have a single endpoint.
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+ - fsl,blk-ctrl
+ - ports
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mn-isi
+ then:
+ properties:
+ interrupts:
+ maxItems: 1
+ ports:
+ properties:
+ port@0:
+ description: MIPI CSI-2 RX
+ required:
+ - port@0
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: fsl,imx8mp-isi
+ then:
+ properties:
+ interrupts:
+ maxItems: 2
+ ports:
+ properties:
+ port@0:
+ description: MIPI CSI-2 RX 0
+ port@1:
+ description: MIPI CSI-2 RX 1
+ required:
+ - port@0
+ - port@1
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/imx8mn-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/imx8mn-power.h>
+
+ isi@32e20000 {
+ compatible = "fsl,imx8mn-isi";
+ reg = <0x32e20000 0x100>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MN_CLK_DISP_AXI_ROOT>,
+ <&clk IMX8MN_CLK_DISP_APB_ROOT>;
+ clock-names = "axi", "apb";
+ fsl,blk-ctrl = <&disp_blk_ctrl>;
+ power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ isi_in: endpoint {
+ remote-endpoint = <&mipi_csi_out>;
+ };
+ };
+ };
+ };
+
+ - |
+ #include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/interrupt-controller/irq.h>
+
+ isi@32e00000 {
+ compatible = "fsl,imx8mp-isi";
+ reg = <0x32e00000 0x4000>;
+ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_MEDIA_AXI_ROOT>,
+ <&clk IMX8MP_CLK_MEDIA_APB_ROOT>;
+ clock-names = "axi", "apb";
+ fsl,blk-ctrl = <&media_blk_ctrl>;
+ power-domains = <&mediamix_pd>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ isi_in_0: endpoint {
+ remote-endpoint = <&mipi_csi_0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ isi_in_1: endpoint {
+ remote-endpoint = <&mipi_csi_1_out>;
+ };
+ };
+ };
+ };
+...
diff --git a/Bindings/media/nxp,imx8mq-vpu.yaml b/Bindings/media/nxp,imx8mq-vpu.yaml
index 7dc13a4..3d58f02 100644
--- a/Bindings/media/nxp,imx8mq-vpu.yaml
+++ b/Bindings/media/nxp,imx8mq-vpu.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/nxp,imx8mq-vpu.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hantro G1/G2 VPU codecs implemented on i.MX8M SoCs
diff --git a/Bindings/media/qcom,msm8916-camss.yaml b/Bindings/media/qcom,msm8916-camss.yaml
index 12ec3e1..eb14999 100644
--- a/Bindings/media/qcom,msm8916-camss.yaml
+++ b/Bindings/media/qcom,msm8916-camss.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,msm8916-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CAMSS ISP
diff --git a/Bindings/media/qcom,msm8916-venus.yaml b/Bindings/media/qcom,msm8916-venus.yaml
index 2abb7d2..2350bf4 100644
--- a/Bindings/media/qcom,msm8916-venus.yaml
+++ b/Bindings/media/qcom,msm8916-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,msm8916-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm MSM8916 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,msm8916-venus
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
maxItems: 1
@@ -39,9 +35,6 @@
iommus:
maxItems: 1
- memory-region:
- maxItems: 1
-
video-decoder:
type: object
@@ -66,57 +59,36 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- - clocks
- - clock-names
- iommus
- - memory-region
- video-decoder
- video-encoder
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,gcc-msm8916.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,gcc-msm8916.h>
- video-codec@1d00000 {
- compatible = "qcom,msm8916-venus";
- reg = <0x01d00000 0xff000>;
- interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
- <&gcc GCC_VENUS0_AHB_CLK>,
- <&gcc GCC_VENUS0_AXI_CLK>;
- clock-names = "core", "iface", "bus";
- power-domains = <&gcc VENUS_GDSC>;
- iommus = <&apps_iommu 5>;
- memory-region = <&venus_mem>;
+ video-codec@1d00000 {
+ compatible = "qcom,msm8916-venus";
+ reg = <0x01d00000 0xff000>;
+ interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
+ <&gcc GCC_VENUS0_AHB_CLK>,
+ <&gcc GCC_VENUS0_AXI_CLK>;
+ clock-names = "core", "iface", "bus";
+ power-domains = <&gcc VENUS_GDSC>;
+ iommus = <&apps_iommu 5>;
+ memory-region = <&venus_mem>;
- video-decoder {
- compatible = "venus-decoder";
- };
-
- video-encoder {
- compatible = "venus-encoder";
- };
+ video-decoder {
+ compatible = "venus-decoder";
};
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+ };
diff --git a/Bindings/media/qcom,msm8996-camss.yaml b/Bindings/media/qcom,msm8996-camss.yaml
index 6aeb3d6..8a10aa1 100644
--- a/Bindings/media/qcom,msm8996-camss.yaml
+++ b/Bindings/media/qcom,msm8996-camss.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,msm8996-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CAMSS ISP
diff --git a/Bindings/media/qcom,msm8996-venus.yaml b/Bindings/media/qcom,msm8996-venus.yaml
index 29d0cb6..3a4d817 100644
--- a/Bindings/media/qcom,msm8996-venus.yaml
+++ b/Bindings/media/qcom,msm8996-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,msm8996-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm MSM8996 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,msm8996-venus
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
maxItems: 1
@@ -37,12 +33,17 @@
- const: bus
- const: mbus
+ interconnects:
+ maxItems: 2
+
+ interconnect-names:
+ items:
+ - const: video-mem
+ - const: cpu-cfg
+
iommus:
maxItems: 20
- memory-region:
- maxItems: 1
-
video-decoder:
type: object
@@ -93,83 +94,62 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- - clocks
- - clock-names
- iommus
- - memory-region
- video-decoder
- video-encoder
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
- video-codec@c00000 {
- compatible = "qcom,msm8996-venus";
- reg = <0x00c00000 0xff000>;
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&mmcc VIDEO_CORE_CLK>,
- <&mmcc VIDEO_AHB_CLK>,
- <&mmcc VIDEO_AXI_CLK>,
- <&mmcc VIDEO_MAXI_CLK>;
- clock-names = "core", "iface", "bus", "mbus";
- power-domains = <&mmcc VENUS_GDSC>;
- iommus = <&venus_smmu 0x00>,
- <&venus_smmu 0x01>,
- <&venus_smmu 0x0a>,
- <&venus_smmu 0x07>,
- <&venus_smmu 0x0e>,
- <&venus_smmu 0x0f>,
- <&venus_smmu 0x08>,
- <&venus_smmu 0x09>,
- <&venus_smmu 0x0b>,
- <&venus_smmu 0x0c>,
- <&venus_smmu 0x0d>,
- <&venus_smmu 0x10>,
- <&venus_smmu 0x11>,
- <&venus_smmu 0x21>,
- <&venus_smmu 0x28>,
- <&venus_smmu 0x29>,
- <&venus_smmu 0x2b>,
- <&venus_smmu 0x2c>,
- <&venus_smmu 0x2d>,
- <&venus_smmu 0x31>;
- memory-region = <&venus_mem>;
+ video-codec@c00000 {
+ compatible = "qcom,msm8996-venus";
+ reg = <0x00c00000 0xff000>;
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc VIDEO_MAXI_CLK>;
+ clock-names = "core", "iface", "bus", "mbus";
+ power-domains = <&mmcc VENUS_GDSC>;
+ iommus = <&venus_smmu 0x00>,
+ <&venus_smmu 0x01>,
+ <&venus_smmu 0x0a>,
+ <&venus_smmu 0x07>,
+ <&venus_smmu 0x0e>,
+ <&venus_smmu 0x0f>,
+ <&venus_smmu 0x08>,
+ <&venus_smmu 0x09>,
+ <&venus_smmu 0x0b>,
+ <&venus_smmu 0x0c>,
+ <&venus_smmu 0x0d>,
+ <&venus_smmu 0x10>,
+ <&venus_smmu 0x11>,
+ <&venus_smmu 0x21>,
+ <&venus_smmu 0x28>,
+ <&venus_smmu 0x29>,
+ <&venus_smmu 0x2b>,
+ <&venus_smmu 0x2c>,
+ <&venus_smmu 0x2d>,
+ <&venus_smmu 0x31>;
+ memory-region = <&venus_mem>;
- video-decoder {
- compatible = "venus-decoder";
- clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
- clock-names = "core";
- power-domains = <&mmcc VENUS_CORE0_GDSC>;
- };
-
- video-encoder {
- compatible = "venus-encoder";
- clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
- clock-names = "core";
- power-domains = <&mmcc VENUS_CORE1_GDSC>;
- };
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
};
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
+ clock-names = "core";
+ power-domains = <&mmcc VENUS_CORE1_GDSC>;
+ };
+ };
diff --git a/Bindings/media/qcom,sc7180-venus.yaml b/Bindings/media/qcom,sc7180-venus.yaml
index 42ee3f0..5cec1d0 100644
--- a/Bindings/media/qcom,sc7180-venus.yaml
+++ b/Bindings/media/qcom,sc7180-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sc7180-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm SC7180 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,sc7180-venus
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
minItems: 2
maxItems: 3
@@ -60,6 +56,10 @@
- const: video-mem
- const: cpu-cfg
+ operating-points-v2: true
+ opp-table:
+ type: object
+
video-decoder:
type: object
@@ -84,63 +84,42 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- power-domain-names
- - clocks
- - clock-names
- iommus
- - memory-region
- video-decoder
- video-encoder
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,videocc-sc7180.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,videocc-sc7180.h>
- venus: video-codec@aa00000 {
- compatible = "qcom,sc7180-venus";
- reg = <0x0aa00000 0xff000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&videocc VENUS_GDSC>,
- <&videocc VCODEC0_GDSC>;
- power-domain-names = "venus", "vcodec0";
- clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
- <&videocc VIDEO_CC_VENUS_AHB_CLK>,
- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
- <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
- clock-names = "core", "iface", "bus",
- "vcodec0_core", "vcodec0_bus";
- iommus = <&apps_smmu 0x0c00 0x60>;
- memory-region = <&venus_mem>;
+ venus: video-codec@aa00000 {
+ compatible = "qcom,sc7180-venus";
+ reg = <0x0aa00000 0xff000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&videocc VENUS_GDSC>,
+ <&videocc VCODEC0_GDSC>;
+ power-domain-names = "venus", "vcodec0";
+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+ clock-names = "core", "iface", "bus",
+ "vcodec0_core", "vcodec0_bus";
+ iommus = <&apps_smmu 0x0c00 0x60>;
+ memory-region = <&venus_mem>;
- video-decoder {
- compatible = "venus-decoder";
- };
-
- video-encoder {
- compatible = "venus-encoder";
- };
+ video-decoder {
+ compatible = "venus-decoder";
};
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+ };
diff --git a/Bindings/media/qcom,sc7280-venus.yaml b/Bindings/media/qcom,sc7280-venus.yaml
index cf361dd..8f9b643 100644
--- a/Bindings/media/qcom,sc7280-venus.yaml
+++ b/Bindings/media/qcom,sc7280-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sc7280-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm SC7280 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus Iris2 IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,sc7280-venus
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
minItems: 2
maxItems: 3
@@ -49,9 +45,6 @@
iommus:
maxItems: 2
- memory-region:
- maxItems: 1
-
interconnects:
maxItems: 2
@@ -60,6 +53,10 @@
- const: cpu-cfg
- const: video-mem
+ operating-points-v2: true
+ opp-table:
+ type: object
+
video-decoder:
type: object
@@ -84,79 +81,58 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- power-domain-names
- - clocks
- - clock-names
- iommus
- - memory-region
- video-decoder
- video-encoder
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,videocc-sc7280.h>
- #include <dt-bindings/interconnect/qcom,sc7280.h>
- #include <dt-bindings/power/qcom-rpmpd.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,videocc-sc7280.h>
+ #include <dt-bindings/interconnect/qcom,sc7280.h>
+ #include <dt-bindings/power/qcom-rpmpd.h>
- venus: video-codec@aa00000 {
- compatible = "qcom,sc7280-venus";
- reg = <0x0aa00000 0xd0600>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ venus: video-codec@aa00000 {
+ compatible = "qcom,sc7280-venus";
+ reg = <0x0aa00000 0xd0600>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
- <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
- <&videocc VIDEO_CC_VENUS_AHB_CLK>,
- <&videocc VIDEO_CC_MVS0_CORE_CLK>,
- <&videocc VIDEO_CC_MVS0_AXI_CLK>;
- clock-names = "core", "bus", "iface",
- "vcodec_core", "vcodec_bus";
+ clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>,
+ <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_MVS0_CORE_CLK>,
+ <&videocc VIDEO_CC_MVS0_AXI_CLK>;
+ clock-names = "core", "bus", "iface",
+ "vcodec_core", "vcodec_bus";
- power-domains = <&videocc MVSC_GDSC>,
- <&videocc MVS0_GDSC>,
- <&rpmhpd SC7280_CX>;
- power-domain-names = "venus", "vcodec0", "cx";
+ power-domains = <&videocc MVSC_GDSC>,
+ <&videocc MVS0_GDSC>,
+ <&rpmhpd SC7280_CX>;
+ power-domain-names = "venus", "vcodec0", "cx";
- interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
- <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
- interconnect-names = "cpu-cfg", "video-mem";
+ interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>,
+ <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>;
+ interconnect-names = "cpu-cfg", "video-mem";
- iommus = <&apps_smmu 0x2180 0x20>,
- <&apps_smmu 0x2184 0x20>;
+ iommus = <&apps_smmu 0x2180 0x20>,
+ <&apps_smmu 0x2184 0x20>;
- memory-region = <&video_mem>;
+ memory-region = <&video_mem>;
- video-decoder {
- compatible = "venus-decoder";
- };
-
- video-encoder {
- compatible = "venus-encoder";
- };
-
- video-firmware {
- iommus = <&apps_smmu 0x21a2 0x0>;
- };
+ video-decoder {
+ compatible = "venus-decoder";
};
+
+ video-encoder {
+ compatible = "venus-encoder";
+ };
+
+ video-firmware {
+ iommus = <&apps_smmu 0x21a2 0x0>;
+ };
+ };
diff --git a/Bindings/media/qcom,sdm660-camss.yaml b/Bindings/media/qcom,sdm660-camss.yaml
index b28c8e1..0a109e1 100644
--- a/Bindings/media/qcom,sdm660-camss.yaml
+++ b/Bindings/media/qcom,sdm660-camss.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sdm660-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CAMSS ISP
diff --git a/Bindings/media/qcom,sdm660-venus.yaml b/Bindings/media/qcom,sdm660-venus.yaml
index 45e3f58..a51835b 100644
--- a/Bindings/media/qcom,sdm660-venus.yaml
+++ b/Bindings/media/qcom,sdm660-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sdm660-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm SDM660 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -15,13 +14,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,sdm660-venus
- reg:
- maxItems: 1
-
clocks:
maxItems: 4
@@ -40,15 +39,9 @@
- const: cpu-cfg
- const: video-mem
- interrupts:
- maxItems: 1
-
iommus:
maxItems: 20
- memory-region:
- maxItems: 1
-
power-domains:
maxItems: 1
@@ -102,86 +95,65 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - clocks
- - clock-names
- - interrupts
- iommus
- - memory-region
- - power-domains
- video-decoder
- video-encoder
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,mmcc-sdm660.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
- video-codec@cc00000 {
- compatible = "qcom,sdm660-venus";
- reg = <0x0cc00000 0xff000>;
- clocks = <&mmcc VIDEO_CORE_CLK>,
- <&mmcc VIDEO_AHB_CLK>,
- <&mmcc VIDEO_AXI_CLK>,
- <&mmcc THROTTLE_VIDEO_AXI_CLK>;
- clock-names = "core", "iface", "bus", "bus_throttle";
- interconnects = <&gnoc 0 &mnoc 13>,
- <&mnoc 4 &bimc 5>;
- interconnect-names = "cpu-cfg", "video-mem";
- interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
- iommus = <&mmss_smmu 0x400>,
- <&mmss_smmu 0x401>,
- <&mmss_smmu 0x40a>,
- <&mmss_smmu 0x407>,
- <&mmss_smmu 0x40e>,
- <&mmss_smmu 0x40f>,
- <&mmss_smmu 0x408>,
- <&mmss_smmu 0x409>,
- <&mmss_smmu 0x40b>,
- <&mmss_smmu 0x40c>,
- <&mmss_smmu 0x40d>,
- <&mmss_smmu 0x410>,
- <&mmss_smmu 0x421>,
- <&mmss_smmu 0x428>,
- <&mmss_smmu 0x429>,
- <&mmss_smmu 0x42b>,
- <&mmss_smmu 0x42c>,
- <&mmss_smmu 0x42d>,
- <&mmss_smmu 0x411>,
- <&mmss_smmu 0x431>;
- memory-region = <&venus_region>;
- power-domains = <&mmcc VENUS_GDSC>;
+ video-codec@cc00000 {
+ compatible = "qcom,sdm660-venus";
+ reg = <0x0cc00000 0xff000>;
+ clocks = <&mmcc VIDEO_CORE_CLK>,
+ <&mmcc VIDEO_AHB_CLK>,
+ <&mmcc VIDEO_AXI_CLK>,
+ <&mmcc THROTTLE_VIDEO_AXI_CLK>;
+ clock-names = "core", "iface", "bus", "bus_throttle";
+ interconnects = <&gnoc 0 &mnoc 13>,
+ <&mnoc 4 &bimc 5>;
+ interconnect-names = "cpu-cfg", "video-mem";
+ interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&mmss_smmu 0x400>,
+ <&mmss_smmu 0x401>,
+ <&mmss_smmu 0x40a>,
+ <&mmss_smmu 0x407>,
+ <&mmss_smmu 0x40e>,
+ <&mmss_smmu 0x40f>,
+ <&mmss_smmu 0x408>,
+ <&mmss_smmu 0x409>,
+ <&mmss_smmu 0x40b>,
+ <&mmss_smmu 0x40c>,
+ <&mmss_smmu 0x40d>,
+ <&mmss_smmu 0x410>,
+ <&mmss_smmu 0x421>,
+ <&mmss_smmu 0x428>,
+ <&mmss_smmu 0x429>,
+ <&mmss_smmu 0x42b>,
+ <&mmss_smmu 0x42c>,
+ <&mmss_smmu 0x42d>,
+ <&mmss_smmu 0x411>,
+ <&mmss_smmu 0x431>;
+ memory-region = <&venus_region>;
+ power-domains = <&mmcc VENUS_GDSC>;
- video-decoder {
- compatible = "venus-decoder";
- clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
- clock-names = "vcodec0_core";
- power-domains = <&mmcc VENUS_CORE0_GDSC>;
- };
-
- video-encoder {
- compatible = "venus-encoder";
- clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
- clock-names = "vcodec0_core";
- power-domains = <&mmcc VENUS_CORE0_GDSC>;
- };
+ video-decoder {
+ compatible = "venus-decoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "vcodec0_core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
};
+
+ video-encoder {
+ compatible = "venus-encoder";
+ clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
+ clock-names = "vcodec0_core";
+ power-domains = <&mmcc VENUS_CORE0_GDSC>;
+ };
+ };
diff --git a/Bindings/media/qcom,sdm845-camss.yaml b/Bindings/media/qcom,sdm845-camss.yaml
index f9a0038..1530ad0 100644
--- a/Bindings/media/qcom,sdm845-camss.yaml
+++ b/Bindings/media/qcom,sdm845-camss.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sdm845-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CAMSS ISP
diff --git a/Bindings/media/qcom,sdm845-venus-v2.yaml b/Bindings/media/qcom,sdm845-venus-v2.yaml
index 8edc8a2..d5f8097 100644
--- a/Bindings/media/qcom,sdm845-venus-v2.yaml
+++ b/Bindings/media/qcom,sdm845-venus-v2.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sdm845-venus-v2.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm SDM845 Venus v2 video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,sdm845-venus-v2
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
minItems: 3
maxItems: 4
@@ -52,8 +48,9 @@
iommus:
maxItems: 2
- memory-region:
- maxItems: 1
+ operating-points-v2: true
+ opp-table:
+ type: object
video-core0:
type: object
@@ -79,68 +76,47 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- power-domain-names
- - clocks
- - clock-names
- iommus
- - memory-region
- video-core0
- video-core1
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,videocc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,videocc-sdm845.h>
- video-codec@aa00000 {
- compatible = "qcom,sdm845-venus-v2";
- reg = <0x0aa00000 0xff000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
- <&videocc VIDEO_CC_VENUS_AHB_CLK>,
- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
- <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
- <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
- <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
- clock-names = "core", "iface", "bus",
- "vcodec0_core", "vcodec0_bus",
- "vcodec1_core", "vcodec1_bus";
- power-domains = <&videocc VENUS_GDSC>,
- <&videocc VCODEC0_GDSC>,
- <&videocc VCODEC1_GDSC>;
- power-domain-names = "venus", "vcodec0", "vcodec1";
- iommus = <&apps_smmu 0x10a0 0x8>,
- <&apps_smmu 0x10b0 0x0>;
- memory-region = <&venus_mem>;
+ video-codec@aa00000 {
+ compatible = "qcom,sdm845-venus-v2";
+ reg = <0x0aa00000 0xff000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>,
+ <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
+ clock-names = "core", "iface", "bus",
+ "vcodec0_core", "vcodec0_bus",
+ "vcodec1_core", "vcodec1_bus";
+ power-domains = <&videocc VENUS_GDSC>,
+ <&videocc VCODEC0_GDSC>,
+ <&videocc VCODEC1_GDSC>;
+ power-domain-names = "venus", "vcodec0", "vcodec1";
+ iommus = <&apps_smmu 0x10a0 0x8>,
+ <&apps_smmu 0x10b0 0x0>;
+ memory-region = <&venus_mem>;
- video-core0 {
- compatible = "venus-decoder";
- };
-
- video-core1 {
- compatible = "venus-encoder";
- };
+ video-core0 {
+ compatible = "venus-decoder";
};
+
+ video-core1 {
+ compatible = "venus-encoder";
+ };
+ };
diff --git a/Bindings/media/qcom,sdm845-venus.yaml b/Bindings/media/qcom,sdm845-venus.yaml
index 57d5033..eabc095 100644
--- a/Bindings/media/qcom,sdm845-venus.yaml
+++ b/Bindings/media/qcom,sdm845-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sdm845-venus.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
-title: Qualcomm Venus video encode and decode accelerators
+title: Qualcomm SDM845 Venus video encode and decode accelerators
maintainers:
- Stanimir Varbanov <stanimir.varbanov@linaro.org>
@@ -14,16 +13,13 @@
The Venus IP is a video encode and decode accelerator present
on Qualcomm platforms
+allOf:
+ - $ref: qcom,venus-common.yaml#
+
properties:
compatible:
const: qcom,sdm845-venus
- reg:
- maxItems: 1
-
- interrupts:
- maxItems: 1
-
power-domains:
maxItems: 1
@@ -39,9 +35,6 @@
iommus:
maxItems: 2
- memory-region:
- maxItems: 1
-
video-core0:
type: object
@@ -94,66 +87,45 @@
additionalProperties: false
- video-firmware:
- type: object
- additionalProperties: false
-
- description: |
- Firmware subnode is needed when the platform does not
- have TrustZone.
-
- properties:
- iommus:
- maxItems: 1
-
- required:
- - iommus
-
required:
- compatible
- - reg
- - interrupts
- - power-domains
- - clocks
- - clock-names
- iommus
- - memory-region
- video-core0
- video-core1
-additionalProperties: false
+unevaluatedProperties: false
examples:
- |
- #include <dt-bindings/interrupt-controller/arm-gic.h>
- #include <dt-bindings/clock/qcom,videocc-sdm845.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,videocc-sdm845.h>
- video-codec@aa00000 {
- compatible = "qcom,sdm845-venus";
- reg = <0x0aa00000 0xff000>;
- interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
- <&videocc VIDEO_CC_VENUS_AHB_CLK>,
- <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
- clock-names = "core", "iface", "bus";
- power-domains = <&videocc VENUS_GDSC>;
- iommus = <&apps_smmu 0x10a0 0x8>,
- <&apps_smmu 0x10b0 0x0>;
- memory-region = <&venus_mem>;
+ video-codec@aa00000 {
+ compatible = "qcom,sdm845-venus";
+ reg = <0x0aa00000 0xff000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
+ <&videocc VIDEO_CC_VENUS_AHB_CLK>,
+ <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>;
+ clock-names = "core", "iface", "bus";
+ power-domains = <&videocc VENUS_GDSC>;
+ iommus = <&apps_smmu 0x10a0 0x8>,
+ <&apps_smmu 0x10b0 0x0>;
+ memory-region = <&venus_mem>;
- video-core0 {
- compatible = "venus-decoder";
- clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
- <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
- clock-names = "core", "bus";
- power-domains = <&videocc VCODEC0_GDSC>;
- };
-
- video-core1 {
- compatible = "venus-encoder";
- clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
- <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
- clock-names = "core", "bus";
- power-domains = <&videocc VCODEC1_GDSC>;
- };
+ video-core0 {
+ compatible = "venus-decoder";
+ clocks = <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
+ clock-names = "core", "bus";
+ power-domains = <&videocc VCODEC0_GDSC>;
};
+
+ video-core1 {
+ compatible = "venus-encoder";
+ clocks = <&videocc VIDEO_CC_VCODEC1_CORE_CLK>,
+ <&videocc VIDEO_CC_VCODEC1_AXI_CLK>;
+ clock-names = "core", "bus";
+ power-domains = <&videocc VCODEC1_GDSC>;
+ };
+ };
diff --git a/Bindings/media/qcom,sm8250-camss.yaml b/Bindings/media/qcom,sm8250-camss.yaml
index 07a2af1..fa5073c 100644
--- a/Bindings/media/qcom,sm8250-camss.yaml
+++ b/Bindings/media/qcom,sm8250-camss.yaml
@@ -2,8 +2,8 @@
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sm8250-camss.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm CAMSS ISP
diff --git a/Bindings/media/qcom,sm8250-venus.yaml b/Bindings/media/qcom,sm8250-venus.yaml
index 4b7a125..7915dcd 100644
--- a/Bindings/media/qcom,sm8250-venus.yaml
+++ b/Bindings/media/qcom,sm8250-venus.yaml
@@ -1,11 +1,10 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
-
%YAML 1.2
---
-$id: "http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#"
-$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+$id: http://devicetree.org/schemas/media/qcom,sm8250-venus.yaml#
+$schema: http://devicetree.
