fix up the bypass options for main/peripheral pll
diff --git a/drivers/clk/socfpga/clk-agilex.c b/drivers/clk/socfpga/clk-agilex.c
index 92a6d74..7eea5ca 100644
--- a/drivers/clk/socfpga/clk-agilex.c
+++ b/drivers/clk/socfpga/clk-agilex.c
@@ -186,6 +186,20 @@
.name = "boot_clk", },
};
+static const struct clk_parent_data bypass_mux0[] = {
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+};
+
+static const struct clk_parent_data bypass_mux1[] = {
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+};
+
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock agilex_pll_clks[] = {
{ AGILEX_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
@@ -220,29 +234,29 @@
static const struct stratix10_perip_cnt_clock agilex_main_perip_cnt_clks[] = {
{ AGILEX_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
- 0, 0x3C, 0, 0, 0},
+ 0, 0x3C, 0, 0, 0, 0},
{ AGILEX_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
- 0, 0x40, 0, 0, 1},
+ 0, 0x40, 0, 0, 1, 0},
{ AGILEX_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
- 0, 4, 0, 0},
+ 0, 4, 0, 0, 0},
{ AGILEX_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
- 0, 0, 0, 0x30, 1},
+ 0, 0, 0, 0x30, 1, 0},
{ AGILEX_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
- 0, 0xD4, 0, 0x88, 0},
+ 0, 0xD4, 0, 0x88, 0, bypass_mux1},
{ AGILEX_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
- 0, 0xD8, 0, 0x88, 1},
+ 0, 0xD8, 0, 0x88, 1, bypass_mux1},
{ AGILEX_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
- ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2},
+ ARRAY_SIZE(emac_ptp_free_mux), 0, 0xDC, 0, 0x88, 2, bypass_mux0},
{ AGILEX_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
- ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3},
+ ARRAY_SIZE(gpio_db_free_mux), 0, 0xE0, 0, 0x88, 3, bypass_mux0},
{ AGILEX_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
- ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4},
+ ARRAY_SIZE(sdmmc_free_mux), 0, 0xE4, 0, 0x88, 4, bypass_mux0},
{ AGILEX_S2F_USER0_FREE_CLK, "s2f_user0_free_clk", NULL, s2f_usr0_free_mux,
- ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0},
+ ARRAY_SIZE(s2f_usr0_free_mux), 0, 0xE8, 0, 0, 0, bypass_mux0},
{ AGILEX_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
- ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5},
+ ARRAY_SIZE(s2f_usr1_free_mux), 0, 0xEC, 0, 0x88, 5, bypass_mux0},
{ AGILEX_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
- ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6},
+ ARRAY_SIZE(psi_ref_free_mux), 0, 0xF0, 0, 0x88, 6, bypass_mux0},
};
static const struct stratix10_gate_clock agilex_gate_clks[] = {
diff --git a/drivers/clk/socfpga/clk-s10.c b/drivers/clk/socfpga/clk-s10.c
index f0bd771..b3c54f6 100644
--- a/drivers/clk/socfpga/clk-s10.c
+++ b/drivers/clk/socfpga/clk-s10.c
@@ -144,6 +144,20 @@
.name = "f2s-free-clk", },
};
+static const struct clk_parent_data bypass_mux0[] = {
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+};
+
+static const struct clk_parent_data bypass_mux1[] = {
+ { .fw_name = "peri_pll_c3",
+ .name = "peri_pll_c3", },
+ { .fw_name = "main_pll_c3",
+ .name = "main_pll_c3", },
+};
+
/* clocks in AO (always on) controller */
static const struct stratix10_pll_clock s10_pll_clks[] = {
{ STRATIX10_BOOT_CLK, "boot_clk", boot_mux, ARRAY_SIZE(boot_mux), 0,
@@ -165,59 +179,59 @@
static const struct stratix10_perip_cnt_clock s10_main_perip_cnt_clks[] = {
{ STRATIX10_MPU_FREE_CLK, "mpu_free_clk", NULL, mpu_free_mux, ARRAY_SIZE(mpu_free_mux),
- 0, 0x48, 0, 0, 0},
+ 0, 0x48, 0, 0, 0, 0},
{ STRATIX10_NOC_FREE_CLK, "noc_free_clk", NULL, noc_free_mux, ARRAY_SIZE(noc_free_mux),
- 0, 0x4C, 0, 0, 0},
+ 0, 0x4C, 0, 0, 0, 0},
{ STRATIX10_MAIN_EMACA_CLK, "main_emaca_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x50, 0, 0, 0},
+ 0x50, 0, 0, 0, 0},
{ STRATIX10_MAIN_EMACB_CLK, "main_emacb_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x54, 0, 0, 0},
+ 0x54, 0, 0, 0, 0},
{ STRATIX10_MAIN_EMAC_PTP_CLK, "main_emac_ptp_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x58, 0, 0, 0},
+ 0x58, 0, 0, 0, 0},
{ STRATIX10_MAIN_GPIO_DB_CLK, "main_gpio_db_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x5C, 0, 0, 0},
+ 0x5C, 0, 0, 0, 0},
{ STRATIX10_MAIN_SDMMC_CLK, "main_sdmmc_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x60, 0, 0, 0},
+ 0x60, 0, 0, 0, 0},
{ STRATIX10_MAIN_S2F_USR0_CLK, "main_s2f_usr0_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0x64, 0, 0, 0},
+ 0, 0x64, 0, 0, 0, 0},
{ STRATIX10_MAIN_S2F_USR1_CLK, "main_s2f_usr1_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x68, 0, 0, 0},
+ 0x68, 0, 0, 0, 0},
{ STRATIX10_MAIN_PSI_REF_CLK, "main_psi_ref_clk", "main_noc_base_clk", NULL, 1, 0,
- 0x6C, 0, 0, 0},
+ 0x6C, 0, 0, 0, 0},
{ STRATIX10_PERI_EMACA_CLK, "peri_emaca_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xBC, 0, 0, 0},
+ 0, 0xBC, 0, 0, 0, 0},
{ STRATIX10_PERI_EMACB_CLK, "peri_emacb_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xC0, 0, 0, 0},
+ 0, 0xC0, 0, 0, 0, 0},
{ STRATIX10_PERI_EMAC_PTP_CLK, "peri_emac_ptp_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xC4, 0, 0, 0},
+ 0, 0xC4, 0, 0, 0, 0},
{ STRATIX10_PERI_GPIO_DB_CLK, "peri_gpio_db_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xC8, 0, 0, 0},
+ 0, 0xC8, 0, 0, 0, 0},
{ STRATIX10_PERI_SDMMC_CLK, "peri_sdmmc_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xCC, 0, 0, 0},
+ 0, 0xCC, 0, 0, 0, 0},
{ STRATIX10_PERI_S2F_USR0_CLK, "peri_s2f_usr0_clk", "peri_noc_base_clk", NULL, 1, 0,
- 0xD0, 0, 0, 0},
+ 0xD0, 0, 0, 0, 0},
{ STRATIX10_PERI_S2F_USR1_CLK, "peri_s2f_usr1_clk", NULL, cntr_mux, ARRAY_SIZE(cntr_mux),
- 0, 0xD4, 0, 0, 0},
+ 0, 0xD4, 0, 0, 0, 0},
{ STRATIX10_PERI_PSI_REF_CLK, "peri_psi_ref_clk", "peri_noc_base_clk", NULL, 1, 0,
- 0xD8, 0, 0, 0},
+ 0xD8, 0, 0, 0, 0},
{ STRATIX10_L4_SYS_FREE_CLK, "l4_sys_free_clk", "noc_free_clk", NULL, 1, 0,
- 0, 4, 0, 0},
+ 0, 4, 0, 0, 0, 0},
{ STRATIX10_NOC_CLK, "noc_clk", NULL, noc_mux, ARRAY_SIZE(noc_mux),
- 0, 0, 0, 0x3C, 1},
+ 0, 0, 0, 0x3C, 1, 0},
{ STRATIX10_EMAC_A_FREE_CLK, "emaca_free_clk", NULL, emaca_free_mux, ARRAY_SIZE(emaca_free_mux),
- 0, 0, 2, 0xB0, 0},
+ 0, 0, 2, 0xB0, 0, bypass_mux1},
{ STRATIX10_EMAC_B_FREE_CLK, "emacb_free_clk", NULL, emacb_free_mux, ARRAY_SIZE(emacb_free_mux),
- 0, 0, 2, 0xB0, 1},
+ 0, 0, 2, 0xB0, 1, bypass_mux1},
{ STRATIX10_EMAC_PTP_FREE_CLK, "emac_ptp_free_clk", NULL, emac_ptp_free_mux,
- ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2},
+ ARRAY_SIZE(emac_ptp_free_mux), 0, 0, 2, 0xB0, 2, bypass_mux0},
{ STRATIX10_GPIO_DB_FREE_CLK, "gpio_db_free_clk", NULL, gpio_db_free_mux,
- ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3},
+ ARRAY_SIZE(gpio_db_free_mux), 0, 0, 0, 0xB0, 3, bypass_mux0},
{ STRATIX10_SDMMC_FREE_CLK, "sdmmc_free_clk", NULL, sdmmc_free_mux,
- ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4},
+ ARRAY_SIZE(sdmmc_free_mux), 0, 0, 0, 0xB0, 4, bypass_mux0},
{ STRATIX10_S2F_USER1_FREE_CLK, "s2f_user1_free_clk", NULL, s2f_usr1_free_mux,
- ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5},
+ ARRAY_SIZE(s2f_usr1_free_mux), 0, 0, 0, 0xB0, 5, bypass_mux0},
{ STRATIX10_PSI_REF_FREE_CLK, "psi_ref_free_clk", NULL, psi_ref_free_mux,
- ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6},
+ ARRAY_SIZE(psi_ref_free_mux), 0, 0, 0, 0xB0, 6, bypass_mux0},
};
static const struct stratix10_gate_clock s10_gate_clks[] = {
diff --git a/drivers/clk/socfpga/stratix10-clk.h b/drivers/clk/socfpga/stratix10-clk.h
index 61eaf3a..d081a38 100644
--- a/drivers/clk/socfpga/stratix10-clk.h
+++ b/drivers/clk/socfpga/stratix10-clk.h
@@ -52,6 +52,7 @@
u8 fixed_divider;
unsigned long bypass_reg;
unsigned long bypass_shift;
+ const struct clk_parent_data *bypass_mux;
};
struct stratix10_gate_clock {
