SoCFPGA Agilex fix for v5.12
- Fix PHY interface register offset for GMACs
arm64: dts: agilex: fix phy interface bit shift for gmac1 and gmac2

The shift for the phy_intf_sel bit in the system manager for gmac1 and
gmac2 should be 0.

Fixes: 2f804ba7aa9ee ("arm64: dts: agilex: Add SysMgr to Ethernet nodes")
Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
1 file changed