| tag | 532affff4c20ca795e51cab97a46327779136999 | |
|---|---|---|
| tagger | Dinh Nguyen <dinguyen@kernel.org> | Thu Mar 10 13:40:39 2022 -0600 |
| object | ef82c9be844f6b249a69d8fa190d4d686121d55c |
SoCFPGA dts updates for v5.18, part 2 - More dt-bindings cleanup, this time, USB DWC2 properties - Add SDR EDAC dts entry for the N5X platform
| commit | ef82c9be844f6b249a69d8fa190d4d686121d55c | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@kernel.org> | Thu Feb 24 10:29:56 2022 -0600 |
| committer | Dinh Nguyen <dinguyen@kernel.org> | Tue Mar 01 09:43:15 2022 -0600 |
| tree | 19c69c5404dbed6eae1c19f194a68a38b66670cd | |
| parent | 4b557e171ae7b5c5b69f7a5eee553714f7c52435 [diff] |
arm64: dts: n5x: add sdr edac support The N5X platform has the Synopsys DDR controller the includes an EDAC controller. Add the entry for the controller in the DTS file instead of the base Agilex DTSI because the base Agilex does not have the controller. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>