| tag | 06d23c4140663afdad2d8ed5923301d40ba82853 | |
|---|---|---|
| tagger | Dinh Nguyen <dinguyen@kernel.org> | Fri Jul 31 11:15:40 2020 -0500 |
| object | dc2f6ce76fe2a4d34b40d79591b6a4706d4ba7f7 |
arm: dts: socfpga: fix for v5.8 - Fix incorrect timer3 reg entry for Arria10
| commit | dc2f6ce76fe2a4d34b40d79591b6a4706d4ba7f7 | [log] [tgz] |
|---|---|---|
| author | Dinh Nguyen <dinguyen@kernel.org> | Fri Jul 31 10:26:40 2020 -0500 |
| committer | Dinh Nguyen <dinguyen@kernel.org> | Fri Jul 31 11:06:16 2020 -0500 |
| tree | 5bd380ec3b0fa41bf7a1e06661b8bd9b44e1d0da | |
| parent | 681a5c71fb829fc2193e3bb524af41525477f5c3 [diff] |
ARM: dts: socfpga: fix register entry for timer3 on Arria10
Fixes the register address for the timer3 entry on Arria10.
Fixes: 475dc86d08de4 ("arm: dts: socfpga: Add a base DTSI for Altera's Arria10 SOC")
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>