tree 3f5e3ef430df334cde4db1f1923f810b651381d0
parent 0af2f6be1b4281385b618cb86ad946eded089ac8
author Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> 1744710817 +0000
committer Georgi Djakov <djakov@kernel.org> 1744715610 +0300

dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
The L3 instance on the SA8775P SoC is similar to those on SoCs
like SM8250 and SC7280. These SoCs use the PERF register instead
of L3_REG for programming the performance level, which is managed
in the data associated with the target-specific compatibles.
Since the hardware remains the same across all EPSS-supporting SoCs,
the generic compatible is retained for all SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>