| From 4fa7e89f7563e5a33ec36b57f26b36ecbbe2209d Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Tue, 28 Feb 2017 17:31:59 +0100 |
| Subject: [PATCH 152/286] clk: renesas: r8a7795: Correct parent clock and sort |
| order for Audio DMACs |
| |
| The parent clock of the Audio DMACs is the "ZS" AXI bus clock, which |
| maps to S3D1 on R-Car H3 ES1.x. |
| All module clocks must be sorted by clock ID. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> |
| (cherry picked from commit a843ed3f6c3e856f9091b042c6b4ed34c02a3187) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7795-cpg-mssr.c | 4 ++-- |
| 1 file changed, 2 insertions(+), 2 deletions(-) |
| |
| --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| @@ -142,8 +142,8 @@ static const struct mssr_mod_clk r8a7795 |
| DEF_MOD("rwdt0", 402, R8A7795_CLK_R), |
| DEF_MOD("intc-ex", 407, R8A7795_CLK_CP), |
| DEF_MOD("intc-ap", 408, R8A7795_CLK_S3D1), |
| - DEF_MOD("audmac0", 502, R8A7795_CLK_S3D4), |
| - DEF_MOD("audmac1", 501, R8A7795_CLK_S3D4), |
| + DEF_MOD("audmac1", 501, R8A7795_CLK_S3D1), |
| + DEF_MOD("audmac0", 502, R8A7795_CLK_S3D1), |
| DEF_MOD("drif7", 508, R8A7795_CLK_S3D2), |
| DEF_MOD("drif6", 509, R8A7795_CLK_S3D2), |
| DEF_MOD("drif5", 510, R8A7795_CLK_S3D2), |
