| From a631740d6e09004d2fdf0e1a69e0f5fbaeab9e6a Mon Sep 17 00:00:00 2001 |
| From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Date: Thu, 2 Feb 2017 18:10:14 +0100 |
| Subject: [PATCH 228/255] serial: sh-sci: add FIFO trigger bits |
| |
| Defines the bits controlling FIFO thresholds, adds the additional |
| HSCIF registers to the register map. |
| |
| Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| (cherry picked from commit 54e14ae2f3e82b327853e40afa9382a984a56742) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/tty/serial/sh-sci.c | 2 ++ |
| drivers/tty/serial/sh-sci.h | 6 ++++++ |
| 2 files changed, 8 insertions(+) |
| |
| --- a/drivers/tty/serial/sh-sci.c |
| +++ b/drivers/tty/serial/sh-sci.c |
| @@ -373,6 +373,8 @@ static const struct sci_port_params sci_ |
| [HSSRR] = { 0x40, 16 }, |
| [SCDL] = { 0x30, 16 }, |
| [SCCKS] = { 0x34, 16 }, |
| + [HSRTRGR] = { 0x54, 16 }, |
| + [HSTTRGR] = { 0x58, 16 }, |
| }, |
| .fifosize = 128, |
| .overrun_reg = SCLSR, |
| --- a/drivers/tty/serial/sh-sci.h |
| +++ b/drivers/tty/serial/sh-sci.h |
| @@ -29,6 +29,8 @@ enum { |
| SCPDR, /* Serial Port Data Register */ |
| SCDL, /* BRG Frequency Division Register */ |
| SCCKS, /* BRG Clock Select Register */ |
| + HSRTRGR, /* Rx FIFO Data Count Trigger Register */ |
| + HSTTRGR, /* Tx FIFO Data Count Trigger Register */ |
| |
| SCIx_NR_REGS, |
| }; |
| @@ -99,6 +101,10 @@ enum { |
| #define SCIF_BREAK_CLEAR (u32)(~(SCIF_PER | SCIF_FER | SCIF_BRK)) |
| |
| /* SCFCR (FIFO Control Register) */ |
| +#define SCFCR_RTRG1 BIT(7) /* Receive FIFO Data Count Trigger */ |
| +#define SCFCR_RTRG0 BIT(6) |
| +#define SCFCR_TTRG1 BIT(5) /* Transmit FIFO Data Count Trigger */ |
| +#define SCFCR_TTRG0 BIT(4) |
| #define SCFCR_MCE BIT(3) /* Modem Control Enable */ |
| #define SCFCR_TFRST BIT(2) /* Transmit FIFO Data Register Reset */ |
| #define SCFCR_RFRST BIT(1) /* Receive FIFO Data Register Reset */ |
