| From 78057d7b664fb1d2f584807f5511dca73e595df9 Mon Sep 17 00:00:00 2001 |
| From: Magnus Damm <damm@opensource.se> |
| Date: Thu, 18 Aug 2011 04:32:08 +0000 |
| Subject: ARM: mach-shmobile: sh73a0 PFC pull-up support for SDHI0+2 |
| |
| Extend the existing sh73a0 PFC code with pull-ups for |
| SDHI0 and SDHI2. Without this patch only SDHI1 has |
| pull-up support on sh73a0. Needed by boards that make |
| use of the internal pull-up resistor support built in |
| the SoC. |
| |
| Signed-off-by: Magnus Damm <damm@opensource.se> |
| Signed-off-by: Paul Mundt <lethal@linux-sh.org> |
| (cherry picked from commit 09dafe9e4e266c7868454a532c9ca762aa5c40a5) |
| |
| Signed-off-by: Simon Horman <horms@verge.net.au> |
| --- |
| arch/arm/mach-shmobile/include/mach/sh73a0.h | 13 +++++ |
| arch/arm/mach-shmobile/pfc-sh73a0.c | 77 ++++++++++++++++++++++------ |
| 2 files changed, 75 insertions(+), 15 deletions(-) |
| |
| diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h |
| index 216c3d6..b385e97 100644 |
| --- a/arch/arm/mach-shmobile/include/mach/sh73a0.h |
| +++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h |
| @@ -451,11 +451,23 @@ enum { |
| GPIO_FN_KEYIN5_PU, |
| GPIO_FN_KEYIN6_PU, |
| GPIO_FN_KEYIN7_PU, |
| + GPIO_FN_SDHICD0_PU, |
| + GPIO_FN_SDHID0_0_PU, |
| + GPIO_FN_SDHID0_1_PU, |
| + GPIO_FN_SDHID0_2_PU, |
| + GPIO_FN_SDHID0_3_PU, |
| + GPIO_FN_SDHICMD0_PU, |
| + GPIO_FN_SDHIWP0_PU, |
| GPIO_FN_SDHID1_0_PU, |
| GPIO_FN_SDHID1_1_PU, |
| GPIO_FN_SDHID1_2_PU, |
| GPIO_FN_SDHID1_3_PU, |
| GPIO_FN_SDHICMD1_PU, |
| + GPIO_FN_SDHID2_0_PU, |
| + GPIO_FN_SDHID2_1_PU, |
| + GPIO_FN_SDHID2_2_PU, |
| + GPIO_FN_SDHID2_3_PU, |
| + GPIO_FN_SDHICMD2_PU, |
| GPIO_FN_MMCCMD0_PU, |
| GPIO_FN_MMCCMD1_PU, |
| GPIO_FN_FSIACK_PU, |
| @@ -463,6 +475,7 @@ enum { |
| GPIO_FN_FSIAIBT_PU, |
| GPIO_FN_FSIAISLD_PU, |
| }; |
| + |
| /* DMA slave IDs */ |
| enum { |
| SHDMA_SLAVE_INVALID, |
| diff --git a/arch/arm/mach-shmobile/pfc-sh73a0.c b/arch/arm/mach-shmobile/pfc-sh73a0.c |
| index d8915c6..599016e 100644 |
| --- a/arch/arm/mach-shmobile/pfc-sh73a0.c |
| +++ b/arch/arm/mach-shmobile/pfc-sh73a0.c |
| @@ -476,13 +476,26 @@ enum { |
| KEYIN5_PU_MARK, |
| KEYIN6_PU_MARK, |
| KEYIN7_PU_MARK, |
| + SDHICD0_PU_MARK, |
| + SDHID0_0_PU_MARK, |
| + SDHID0_1_PU_MARK, |
| + SDHID0_2_PU_MARK, |
| + SDHID0_3_PU_MARK, |
| + SDHICMD0_PU_MARK, |
| + SDHIWP0_PU_MARK, |
| SDHID1_0_PU_MARK, |
| SDHID1_1_PU_MARK, |
| SDHID1_2_PU_MARK, |
| SDHID1_3_PU_MARK, |
| SDHICMD1_PU_MARK, |
| + SDHID2_0_PU_MARK, |
| + SDHID2_1_PU_MARK, |
| + SDHID2_2_PU_MARK, |
| + SDHID2_3_PU_MARK, |
| + SDHICMD2_PU_MARK, |
| MMCCMD0_PU_MARK, |
| MMCCMD1_PU_MARK, |
| + FSIBISLD_PU_MARK, |
| FSIACK_PU_MARK, |
| FSIAILR_PU_MARK, |
| FSIAIBT_PU_MARK, |
| @@ -1336,19 +1349,28 @@ static pinmux_enum_t pinmux_data[] = { |
| PINMUX_DATA(TS_SCK4_MARK, PORT268_FN3), |
| PINMUX_DATA(SDHICMD2_MARK, PORT269_FN1), |
| PINMUX_DATA(MMCCLK0_MARK, PORT270_FN1, MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, MSEL4CR_MSEL15_0), \ |
| + PINMUX_DATA(MMCD0_0_MARK, PORT271_FN1, PORT271_IN_PU, |
| + MSEL4CR_MSEL15_0), |
| + PINMUX_DATA(MMCD0_1_MARK, PORT272_FN1, PORT272_IN_PU, |
| + MSEL4CR_MSEL15_0), |
| + PINMUX_DATA(MMCD0_2_MARK, PORT273_FN1, PORT273_IN_PU, |
| + MSEL4CR_MSEL15_0), |
| + PINMUX_DATA(MMCD0_3_MARK, PORT274_FN1, PORT274_IN_PU, |
| + MSEL4CR_MSEL15_0), |
| + PINMUX_DATA(MMCD0_4_MARK, PORT275_FN1, PORT275_IN_PU, |
| + MSEL4CR_MSEL15_0), \ |
| PINMUX_DATA(TS_SPSYNC5_MARK, PORT275_FN3), |
| - PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, MSEL4CR_MSEL15_0), \ |
| + PINMUX_DATA(MMCD0_5_MARK, PORT276_FN1, PORT276_IN_PU, |
| + MSEL4CR_MSEL15_0), \ |
| PINMUX_DATA(TS_SDAT5_MARK, PORT276_FN3), |
| - PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, MSEL4CR_MSEL15_0), \ |
| + PINMUX_DATA(MMCD0_6_MARK, PORT277_FN1, PORT277_IN_PU, |
| + MSEL4CR_MSEL15_0), \ |
| PINMUX_DATA(TS_SDEN5_MARK, PORT277_FN3), |
| - PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, MSEL4CR_MSEL15_0), \ |
| + PINMUX_DATA(MMCD0_7_MARK, PORT278_FN1, PORT278_IN_PU, |
| + MSEL4CR_MSEL15_0), \ |
| PINMUX_DATA(TS_SCK5_MARK, PORT278_FN3), |
| - PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, MSEL4CR_MSEL15_0), |
| + PINMUX_DATA(MMCCMD0_MARK, PORT279_FN1, PORT279_IN_PU, |
| + MSEL4CR_MSEL15_0), |
| PINMUX_DATA(RESETOUTS__MARK, PORT281_FN1), \ |
| PINMUX_DATA(EXTAL2OUT_MARK, PORT281_FN2), |
| PINMUX_DATA(MCP_WAIT__MCP_FRB_MARK, PORT288_FN1), |
| @@ -1465,16 +1487,29 @@ static pinmux_enum_t pinmux_data[] = { |
| PINMUX_DATA(KEYIN6_PU_MARK, PORT72_FN2, PORT72_IN_PU), |
| PINMUX_DATA(KEYIN7_PU_MARK, PORT73_FN2, PORT73_IN_PU), |
| |
| - PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_IN_PU, PORT259_FN1), |
| - PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_IN_PU, PORT260_FN1), |
| - PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_IN_PU, PORT261_FN1), |
| - PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_IN_PU, PORT262_FN1), |
| - PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_IN_PU, PORT263_FN1), |
| + PINMUX_DATA(SDHICD0_PU_MARK, PORT251_FN1, PORT251_IN_PU), |
| + PINMUX_DATA(SDHID0_0_PU_MARK, PORT252_FN1, PORT252_IN_PU), |
| + PINMUX_DATA(SDHID0_1_PU_MARK, PORT253_FN1, PORT253_IN_PU), |
| + PINMUX_DATA(SDHID0_2_PU_MARK, PORT254_FN1, PORT254_IN_PU), |
| + PINMUX_DATA(SDHID0_3_PU_MARK, PORT255_FN1, PORT255_IN_PU), |
| + PINMUX_DATA(SDHICMD0_PU_MARK, PORT256_FN1, PORT256_IN_PU), |
| + PINMUX_DATA(SDHIWP0_PU_MARK, PORT257_FN1, PORT256_IN_PU), |
| + PINMUX_DATA(SDHID1_0_PU_MARK, PORT259_FN1, PORT259_IN_PU), |
| + PINMUX_DATA(SDHID1_1_PU_MARK, PORT260_FN1, PORT260_IN_PU), |
| + PINMUX_DATA(SDHID1_2_PU_MARK, PORT261_FN1, PORT261_IN_PU), |
| + PINMUX_DATA(SDHID1_3_PU_MARK, PORT262_FN1, PORT262_IN_PU), |
| + PINMUX_DATA(SDHICMD1_PU_MARK, PORT263_FN1, PORT263_IN_PU), |
| + PINMUX_DATA(SDHID2_0_PU_MARK, PORT265_FN1, PORT265_IN_PU), |
| + PINMUX_DATA(SDHID2_1_PU_MARK, PORT266_FN1, PORT266_IN_PU), |
| + PINMUX_DATA(SDHID2_2_PU_MARK, PORT267_FN1, PORT267_IN_PU), |
| + PINMUX_DATA(SDHID2_3_PU_MARK, PORT268_FN1, PORT268_IN_PU), |
| + PINMUX_DATA(SDHICMD2_PU_MARK, PORT269_FN1, PORT269_IN_PU), |
| |
| PINMUX_DATA(MMCCMD0_PU_MARK, PORT279_FN1, PORT279_IN_PU, |
| MSEL4CR_MSEL15_0), |
| - PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT279_IN_PU, |
| + PINMUX_DATA(MMCCMD1_PU_MARK, PORT297_FN2, PORT297_IN_PU, |
| MSEL4CR_MSEL15_1), |
| + PINMUX_DATA(FSIBISLD_PU_MARK, PORT39_FN1, PORT39_IN_PU), |
| PINMUX_DATA(FSIACK_PU_MARK, PORT49_FN1, PORT49_IN_PU), |
| PINMUX_DATA(FSIAILR_PU_MARK, PORT50_FN5, PORT50_IN_PU), |
| PINMUX_DATA(FSIAIBT_PU_MARK, PORT51_FN5, PORT51_IN_PU), |
| @@ -2126,11 +2161,23 @@ static struct pinmux_gpio pinmux_gpios[] = { |
| GPIO_FN(KEYIN5_PU), |
| GPIO_FN(KEYIN6_PU), |
| GPIO_FN(KEYIN7_PU), |
| + GPIO_FN(SDHICD0_PU), |
| + GPIO_FN(SDHID0_0_PU), |
| + GPIO_FN(SDHID0_1_PU), |
| + GPIO_FN(SDHID0_2_PU), |
| + GPIO_FN(SDHID0_3_PU), |
| + GPIO_FN(SDHICMD0_PU), |
| + GPIO_FN(SDHIWP0_PU), |
| GPIO_FN(SDHID1_0_PU), |
| GPIO_FN(SDHID1_1_PU), |
| GPIO_FN(SDHID1_2_PU), |
| GPIO_FN(SDHID1_3_PU), |
| GPIO_FN(SDHICMD1_PU), |
| + GPIO_FN(SDHID2_0_PU), |
| + GPIO_FN(SDHID2_1_PU), |
| + GPIO_FN(SDHID2_2_PU), |
| + GPIO_FN(SDHID2_3_PU), |
| + GPIO_FN(SDHICMD2_PU), |
| GPIO_FN(MMCCMD0_PU), |
| GPIO_FN(MMCCMD1_PU), |
| GPIO_FN(FSIACK_PU), |
| -- |
| 1.7.10.2.565.gbd578b5 |
| |