| From ad5326e9d9fb1e5818c5b4f9da3d8306d6b2b21b Mon Sep 17 00:00:00 2001 |
| From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Date: Wed, 7 Dec 2016 17:44:47 +0100 |
| Subject: [PATCH 015/286] arm64: dts: r8a7796 dtsi: Add all HSCIF nodes |
| |
| Add the device nodes for all HSCIF serial ports, incl. clocks, and |
| power domain. |
| |
| Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| [simon: express register size in hex; refer to power domain in changelog] |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| |
| (cherry picked from commit 68cd161072605c276d4e6c8cd06fbe7b00a0f680) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7796.dtsi | 70 +++++++++++++++++++++++++++++++ |
| 1 file changed, 70 insertions(+) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| +++ b/arch/arm64/boot/dts/renesas/r8a7796.dtsi |
| @@ -489,6 +489,76 @@ |
| status = "disabled"; |
| }; |
| |
| + hscif0: serial@e6540000 { |
| + compatible = "renesas,hscif-r8a7796", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6540000 0 0x60>; |
| + interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 520>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif1: serial@e6550000 { |
| + compatible = "renesas,hscif-r8a7796", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6550000 0 0x60>; |
| + interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 519>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif2: serial@e6560000 { |
| + compatible = "renesas,hscif-r8a7796", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe6560000 0 0x60>; |
| + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 518>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif3: serial@e66a0000 { |
| + compatible = "renesas,hscif-r8a7796", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe66a0000 0 0x60>; |
| + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 517>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| + hscif4: serial@e66b0000 { |
| + compatible = "renesas,hscif-r8a7796", |
| + "renesas,rcar-gen3-hscif", |
| + "renesas,hscif"; |
| + reg = <0 0xe66b0000 0 0x60>; |
| + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 516>, |
| + <&cpg CPG_CORE R8A7796_CLK_S3D1>, |
| + <&scif_clk>; |
| + clock-names = "fck", "brg_int", "scif_clk"; |
| + power-domains = <&sysc R8A7796_PD_ALWAYS_ON>; |
| + status = "disabled"; |
| + }; |
| + |
| scif2: serial@e6e88000 { |
| compatible = "renesas,scif-r8a7796", |
| "renesas,rcar-gen3-scif", "renesas,scif"; |
