| From 9389e8db60a5b7a71546c61d167256be9d5b9b9d Mon Sep 17 00:00:00 2001 |
| From: Koji Matsuoka <koji.matsuoka.xm@renesas.com> |
| Date: Mon, 18 Apr 2016 16:31:30 +0900 |
| Subject: [PATCH 053/299] drm: rcar-du: Fix display timing controller parameter |
| |
| There is a bug in the setting of the DES (Display Enable Signal) |
| register. This current setting occurs 1 dot left shift. The DES |
| register should be set minus one value about the specifying value |
| with H/W specification. This patch corrects it. |
| |
| Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com> |
| Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> |
| (cherry picked from commit 9cdced8a39c04cf798ddb2a27cb5952f7d39f633) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/gpu/drm/rcar-du/rcar_du_crtc.c | 2 +- |
| 1 file changed, 1 insertion(+), 1 deletion(-) |
| |
| --- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.c |
| +++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.c |
| @@ -172,7 +172,7 @@ static void rcar_du_crtc_set_display_tim |
| mode->crtc_vsync_start - 1); |
| rcar_du_crtc_write(rcrtc, VCR, mode->crtc_vtotal - 1); |
| |
| - rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start); |
| + rcar_du_crtc_write(rcrtc, DESR, mode->htotal - mode->hsync_start - 1); |
| rcar_du_crtc_write(rcrtc, DEWR, mode->hdisplay); |
| } |
| |
