| From 30918d73bb8dbf1074a380a9d2db2913238420e6 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 6 Mar 2017 17:40:41 +0100 |
| Subject: [PATCH 060/286] ARM: dts: r8a7792: Remove unit-address and reg from |
| integrated cache |
| |
| The Cortex-A15 cache controller is an integrated controller, and thus |
| the device node representing it should not have a unit-addresses or reg |
| property. |
| |
| Fixes: 7c4163aae3d8e5b9 ("ARM: dts: r8a7792: initial SoC device tree") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit a0504f0880c11da301dc2b5a5135bd02376e367e) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7792.dtsi | 3 +-- |
| 1 file changed, 1 insertion(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7792.dtsi |
| +++ b/arch/arm/boot/dts/r8a7792.dtsi |
| @@ -60,9 +60,8 @@ |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| - L2_CA15: cache-controller@0 { |
| + L2_CA15: cache-controller-0 { |
| compatible = "cache"; |
| - reg = <0>; |
| cache-unified; |
| cache-level = <2>; |
| power-domains = <&sysc R8A7792_PD_CA15_SCU>; |
