| From 83fae191e06ed9623195939adbe40a2cde6fd9cb Mon Sep 17 00:00:00 2001 |
| From: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> |
| Date: Thu, 13 Oct 2016 10:29:14 +0100 |
| Subject: [PATCH 094/299] pinctrl: sh-pfc: r8a7796: Add DRIF support |
| |
| This patch adds DRIF[0-3] pinmux support for r8a7796 SoC. |
| |
| Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit fb0828316bf655d26c74321240bbf83b2a1d89ad) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 291 +++++++++++++++++++++++++++++++++++ |
| 1 file changed, 291 insertions(+) |
| |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c |
| @@ -1490,6 +1490,221 @@ static const struct sh_pfc_pin pinmux_pi |
| PINMUX_GPIO_GP_ALL(), |
| }; |
| |
| +/* - DRIF0 --------------------------------------------------------------- */ |
| +static const unsigned int drif0_ctrl_a_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), |
| +}; |
| +static const unsigned int drif0_ctrl_a_mux[] = { |
| + RIF0_CLK_A_MARK, RIF0_SYNC_A_MARK, |
| +}; |
| +static const unsigned int drif0_data0_a_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 10), |
| +}; |
| +static const unsigned int drif0_data0_a_mux[] = { |
| + RIF0_D0_A_MARK, |
| +}; |
| +static const unsigned int drif0_data1_a_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 7), |
| +}; |
| +static const unsigned int drif0_data1_a_mux[] = { |
| + RIF0_D1_A_MARK, |
| +}; |
| +static const unsigned int drif0_ctrl_b_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4), |
| +}; |
| +static const unsigned int drif0_ctrl_b_mux[] = { |
| + RIF0_CLK_B_MARK, RIF0_SYNC_B_MARK, |
| +}; |
| +static const unsigned int drif0_data0_b_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(5, 1), |
| +}; |
| +static const unsigned int drif0_data0_b_mux[] = { |
| + RIF0_D0_B_MARK, |
| +}; |
| +static const unsigned int drif0_data1_b_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(5, 2), |
| +}; |
| +static const unsigned int drif0_data1_b_mux[] = { |
| + RIF0_D1_B_MARK, |
| +}; |
| +static const unsigned int drif0_ctrl_c_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 15), |
| +}; |
| +static const unsigned int drif0_ctrl_c_mux[] = { |
| + RIF0_CLK_C_MARK, RIF0_SYNC_C_MARK, |
| +}; |
| +static const unsigned int drif0_data0_c_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(5, 13), |
| +}; |
| +static const unsigned int drif0_data0_c_mux[] = { |
| + RIF0_D0_C_MARK, |
| +}; |
| +static const unsigned int drif0_data1_c_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(5, 14), |
| +}; |
| +static const unsigned int drif0_data1_c_mux[] = { |
| + RIF0_D1_C_MARK, |
| +}; |
| +/* - DRIF1 --------------------------------------------------------------- */ |
| +static const unsigned int drif1_ctrl_a_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), |
| +}; |
| +static const unsigned int drif1_ctrl_a_mux[] = { |
| + RIF1_CLK_A_MARK, RIF1_SYNC_A_MARK, |
| +}; |
| +static const unsigned int drif1_data0_a_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 19), |
| +}; |
| +static const unsigned int drif1_data0_a_mux[] = { |
| + RIF1_D0_A_MARK, |
| +}; |
| +static const unsigned int drif1_data1_a_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 20), |
| +}; |
| +static const unsigned int drif1_data1_a_mux[] = { |
| + RIF1_D1_A_MARK, |
| +}; |
| +static const unsigned int drif1_ctrl_b_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 3), |
| +}; |
| +static const unsigned int drif1_ctrl_b_mux[] = { |
| + RIF1_CLK_B_MARK, RIF1_SYNC_B_MARK, |
| +}; |
| +static const unsigned int drif1_data0_b_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(5, 7), |
| +}; |
| +static const unsigned int drif1_data0_b_mux[] = { |
| + RIF1_D0_B_MARK, |
| +}; |
| +static const unsigned int drif1_data1_b_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(5, 8), |
| +}; |
| +static const unsigned int drif1_data1_b_mux[] = { |
| + RIF1_D1_B_MARK, |
| +}; |
| +static const unsigned int drif1_ctrl_c_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 11), |
| +}; |
| +static const unsigned int drif1_ctrl_c_mux[] = { |
| + RIF1_CLK_C_MARK, RIF1_SYNC_C_MARK, |
| +}; |
| +static const unsigned int drif1_data0_c_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(5, 6), |
| +}; |
| +static const unsigned int drif1_data0_c_mux[] = { |
| + RIF1_D0_C_MARK, |
| +}; |
| +static const unsigned int drif1_data1_c_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(5, 10), |
| +}; |
| +static const unsigned int drif1_data1_c_mux[] = { |
| + RIF1_D1_C_MARK, |
| +}; |
| +/* - DRIF2 --------------------------------------------------------------- */ |
| +static const unsigned int drif2_ctrl_a_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9), |
| +}; |
| +static const unsigned int drif2_ctrl_a_mux[] = { |
| + RIF2_CLK_A_MARK, RIF2_SYNC_A_MARK, |
| +}; |
| +static const unsigned int drif2_data0_a_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 7), |
| +}; |
| +static const unsigned int drif2_data0_a_mux[] = { |
| + RIF2_D0_A_MARK, |
| +}; |
| +static const unsigned int drif2_data1_a_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 10), |
| +}; |
| +static const unsigned int drif2_data1_a_mux[] = { |
| + RIF2_D1_A_MARK, |
| +}; |
| +static const unsigned int drif2_ctrl_b_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27), |
| +}; |
| +static const unsigned int drif2_ctrl_b_mux[] = { |
| + RIF2_CLK_B_MARK, RIF2_SYNC_B_MARK, |
| +}; |
| +static const unsigned int drif2_data0_b_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 30), |
| +}; |
| +static const unsigned int drif2_data0_b_mux[] = { |
| + RIF2_D0_B_MARK, |
| +}; |
| +static const unsigned int drif2_data1_b_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 31), |
| +}; |
| +static const unsigned int drif2_data1_b_mux[] = { |
| + RIF2_D1_B_MARK, |
| +}; |
| +/* - DRIF3 --------------------------------------------------------------- */ |
| +static const unsigned int drif3_ctrl_a_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18), |
| +}; |
| +static const unsigned int drif3_ctrl_a_mux[] = { |
| + RIF3_CLK_A_MARK, RIF3_SYNC_A_MARK, |
| +}; |
| +static const unsigned int drif3_data0_a_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 19), |
| +}; |
| +static const unsigned int drif3_data0_a_mux[] = { |
| + RIF3_D0_A_MARK, |
| +}; |
| +static const unsigned int drif3_data1_a_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 20), |
| +}; |
| +static const unsigned int drif3_data1_a_mux[] = { |
| + RIF3_D1_A_MARK, |
| +}; |
| +static const unsigned int drif3_ctrl_b_pins[] = { |
| + /* CLK, SYNC */ |
| + RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25), |
| +}; |
| +static const unsigned int drif3_ctrl_b_mux[] = { |
| + RIF3_CLK_B_MARK, RIF3_SYNC_B_MARK, |
| +}; |
| +static const unsigned int drif3_data0_b_pins[] = { |
| + /* D0 */ |
| + RCAR_GP_PIN(6, 28), |
| +}; |
| +static const unsigned int drif3_data0_b_mux[] = { |
| + RIF3_D0_B_MARK, |
| +}; |
| +static const unsigned int drif3_data1_b_pins[] = { |
| + /* D1 */ |
| + RCAR_GP_PIN(6, 29), |
| +}; |
| +static const unsigned int drif3_data1_b_mux[] = { |
| + RIF3_D1_B_MARK, |
| +}; |
| + |
| /* - I2C -------------------------------------------------------------------- */ |
| static const unsigned int i2c1_a_pins[] = { |
| /* SDA, SCL */ |
| @@ -1963,6 +2178,36 @@ static const unsigned int sdhi3_ds_mux[] |
| }; |
| |
| static const struct sh_pfc_pin_group pinmux_groups[] = { |
| + SH_PFC_PIN_GROUP(drif0_ctrl_a), |
| + SH_PFC_PIN_GROUP(drif0_data0_a), |
| + SH_PFC_PIN_GROUP(drif0_data1_a), |
| + SH_PFC_PIN_GROUP(drif0_ctrl_b), |
| + SH_PFC_PIN_GROUP(drif0_data0_b), |
| + SH_PFC_PIN_GROUP(drif0_data1_b), |
| + SH_PFC_PIN_GROUP(drif0_ctrl_c), |
| + SH_PFC_PIN_GROUP(drif0_data0_c), |
| + SH_PFC_PIN_GROUP(drif0_data1_c), |
| + SH_PFC_PIN_GROUP(drif1_ctrl_a), |
| + SH_PFC_PIN_GROUP(drif1_data0_a), |
| + SH_PFC_PIN_GROUP(drif1_data1_a), |
| + SH_PFC_PIN_GROUP(drif1_ctrl_b), |
| + SH_PFC_PIN_GROUP(drif1_data0_b), |
| + SH_PFC_PIN_GROUP(drif1_data1_b), |
| + SH_PFC_PIN_GROUP(drif1_ctrl_c), |
| + SH_PFC_PIN_GROUP(drif1_data0_c), |
| + SH_PFC_PIN_GROUP(drif1_data1_c), |
| + SH_PFC_PIN_GROUP(drif2_ctrl_a), |
| + SH_PFC_PIN_GROUP(drif2_data0_a), |
| + SH_PFC_PIN_GROUP(drif2_data1_a), |
| + SH_PFC_PIN_GROUP(drif2_ctrl_b), |
| + SH_PFC_PIN_GROUP(drif2_data0_b), |
| + SH_PFC_PIN_GROUP(drif2_data1_b), |
| + SH_PFC_PIN_GROUP(drif3_ctrl_a), |
| + SH_PFC_PIN_GROUP(drif3_data0_a), |
| + SH_PFC_PIN_GROUP(drif3_data1_a), |
| + SH_PFC_PIN_GROUP(drif3_ctrl_b), |
| + SH_PFC_PIN_GROUP(drif3_data0_b), |
| + SH_PFC_PIN_GROUP(drif3_data1_b), |
| SH_PFC_PIN_GROUP(i2c1_a), |
| SH_PFC_PIN_GROUP(i2c1_b), |
| SH_PFC_PIN_GROUP(i2c2_a), |
| @@ -2027,6 +2272,48 @@ static const struct sh_pfc_pin_group pin |
| SH_PFC_PIN_GROUP(sdhi3_ds), |
| }; |
| |
| +static const char * const drif0_groups[] = { |
| + "drif0_ctrl_a", |
| + "drif0_data0_a", |
| + "drif0_data1_a", |
| + "drif0_ctrl_b", |
| + "drif0_data0_b", |
| + "drif0_data1_b", |
| + "drif0_ctrl_c", |
| + "drif0_data0_c", |
| + "drif0_data1_c", |
| +}; |
| + |
| +static const char * const drif1_groups[] = { |
| + "drif1_ctrl_a", |
| + "drif1_data0_a", |
| + "drif1_data1_a", |
| + "drif1_ctrl_b", |
| + "drif1_data0_b", |
| + "drif1_data1_b", |
| + "drif1_ctrl_c", |
| + "drif1_data0_c", |
| + "drif1_data1_c", |
| +}; |
| + |
| +static const char * const drif2_groups[] = { |
| + "drif2_ctrl_a", |
| + "drif2_data0_a", |
| + "drif2_data1_a", |
| + "drif2_ctrl_b", |
| + "drif2_data0_b", |
| + "drif2_data1_b", |
| +}; |
| + |
| +static const char * const drif3_groups[] = { |
| + "drif3_ctrl_a", |
| + "drif3_data0_a", |
| + "drif3_data1_a", |
| + "drif3_ctrl_b", |
| + "drif3_data0_b", |
| + "drif3_data1_b", |
| +}; |
| + |
| static const char * const i2c1_groups[] = { |
| "i2c1_a", |
| "i2c1_b", |
| @@ -2132,6 +2419,10 @@ static const char * const sdhi3_groups[] |
| }; |
| |
| static const struct sh_pfc_function pinmux_functions[] = { |
| + SH_PFC_FUNCTION(drif0), |
| + SH_PFC_FUNCTION(drif1), |
| + SH_PFC_FUNCTION(drif2), |
| + SH_PFC_FUNCTION(drif3), |
| SH_PFC_FUNCTION(i2c1), |
| SH_PFC_FUNCTION(i2c2), |
| SH_PFC_FUNCTION(i2c6), |