| From d80b1edc3d1787a07007fb2842be0462504dad22 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Fri, 10 Mar 2017 11:36:33 +0100 |
| Subject: [PATCH 157/286] clk: renesas: rcar-gen3-cpg: Pass mode pins to |
| rcar_gen3_cpg_init() |
| |
| Pass the mode pin states from the SoC-specific CPG/MSSR driver to the |
| R-Car Gen3 CPG driver core, as their state will be needed to make some |
| core clock configuration decisions. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit 5f3a432a44b135db002d22446827cfa061fc0bfb) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/clk/renesas/r8a7795-cpg-mssr.c | 2 +- |
| drivers/clk/renesas/r8a7796-cpg-mssr.c | 2 +- |
| drivers/clk/renesas/rcar-gen3-cpg.c | 4 +++- |
| drivers/clk/renesas/rcar-gen3-cpg.h | 2 +- |
| 4 files changed, 6 insertions(+), 4 deletions(-) |
| |
| --- a/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c |
| @@ -330,7 +330,7 @@ static int __init r8a7795_cpg_mssr_init( |
| return -EINVAL; |
| } |
| |
| - return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); |
| + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); |
| } |
| |
| const struct cpg_mssr_info r8a7795_cpg_mssr_info __initconst = { |
| --- a/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| +++ b/drivers/clk/renesas/r8a7796-cpg-mssr.c |
| @@ -273,7 +273,7 @@ static int __init r8a7796_cpg_mssr_init( |
| return -EINVAL; |
| } |
| |
| - return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR); |
| + return rcar_gen3_cpg_init(cpg_pll_config, CLK_EXTALR, cpg_mode); |
| } |
| |
| const struct cpg_mssr_info r8a7796_cpg_mssr_info __initconst = { |
| --- a/drivers/clk/renesas/rcar-gen3-cpg.c |
| +++ b/drivers/clk/renesas/rcar-gen3-cpg.c |
| @@ -247,6 +247,7 @@ static struct clk * __init cpg_sd_clk_re |
| |
| static const struct rcar_gen3_cpg_pll_config *cpg_pll_config __initdata; |
| static unsigned int cpg_clk_extalr __initdata; |
| +static u32 cpg_mode __initdata; |
| |
| struct clk * __init rcar_gen3_cpg_clk_register(struct device *dev, |
| const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
| @@ -334,9 +335,10 @@ struct clk * __init rcar_gen3_cpg_clk_re |
| } |
| |
| int __init rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, |
| - unsigned int clk_extalr) |
| + unsigned int clk_extalr, u32 mode) |
| { |
| cpg_pll_config = config; |
| cpg_clk_extalr = clk_extalr; |
| + cpg_mode = mode; |
| return 0; |
| } |
| --- a/drivers/clk/renesas/rcar-gen3-cpg.h |
| +++ b/drivers/clk/renesas/rcar-gen3-cpg.h |
| @@ -37,6 +37,6 @@ struct clk *rcar_gen3_cpg_clk_register(s |
| const struct cpg_core_clk *core, const struct cpg_mssr_info *info, |
| struct clk **clks, void __iomem *base); |
| int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config, |
| - unsigned int clk_extalr); |
| + unsigned int clk_extalr, u32 mode); |
| |
| #endif |