| From 391e4ad5fa7900897f6e7514d0507662f49159a3 Mon Sep 17 00:00:00 2001 |
| From: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Date: Fri, 3 Feb 2017 11:38:17 +0100 |
| Subject: [PATCH 231/255] serial: sh-sci: increase RX FIFO trigger defaults for |
| (H)SCIF |
| |
| Sets reasonable trigger defaults for the various SCIF variants. |
| Also corrects the FIFO size for SH7705-style ports. |
| |
| Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> |
| (cherry picked from commit 18e8cf159177100e69d528293f8cf6875c0b1bca) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/tty/serial/sh-sci.c | 29 ++++++++++++++++++++++++++++- |
| 1 file changed, 28 insertions(+), 1 deletion(-) |
| |
| --- a/drivers/tty/serial/sh-sci.c |
| +++ b/drivers/tty/serial/sh-sci.c |
| @@ -148,6 +148,7 @@ struct sci_port { |
| struct timer_list rx_timer; |
| unsigned int rx_timeout; |
| #endif |
| + int rx_trigger; |
| |
| bool has_rtscts; |
| bool autorts; |
| @@ -450,7 +451,7 @@ static const struct sci_port_params sci_ |
| [SCFCR] = { 0x18, 16 }, |
| [SCFDR] = { 0x1c, 16 }, |
| }, |
| - .fifosize = 16, |
| + .fifosize = 64, |
| .overrun_reg = SCxSR, |
| .overrun_mask = SCIFA_ORER, |
| .sampling_rate_mask = SCI_SR(16), |
| @@ -2064,6 +2065,7 @@ static void sci_reset(struct uart_port * |
| { |
| const struct plat_sci_reg *reg; |
| unsigned int status; |
| + struct sci_port *s = to_sci_port(port); |
| |
| do { |
| status = serial_port_in(port, SCxSR); |
| @@ -2083,6 +2085,9 @@ static void sci_reset(struct uart_port * |
| status &= ~(SCLSR_TO | SCLSR_ORER); |
| serial_port_out(port, SCLSR, status); |
| } |
| + |
| + if (s->rx_trigger > 1) |
| + scif_set_rtrg(port, s->rx_trigger); |
| } |
| |
| static void sci_set_termios(struct uart_port *port, struct ktermios *termios, |
| @@ -2621,6 +2626,28 @@ static int sci_init_single(struct platfo |
| if (unlikely(sci_port->params == NULL)) |
| return -EINVAL; |
| |
| + switch (p->type) { |
| + case PORT_SCIFB: |
| + sci_port->rx_trigger = 48; |
| + break; |
| + case PORT_HSCIF: |
| + sci_port->rx_trigger = 64; |
| + break; |
| + case PORT_SCIFA: |
| + sci_port->rx_trigger = 32; |
| + break; |
| + case PORT_SCIF: |
| + if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) |
| + /* RX triggering not implemented for this IP */ |
| + sci_port->rx_trigger = 1; |
| + else |
| + sci_port->rx_trigger = 8; |
| + break; |
| + default: |
| + sci_port->rx_trigger = 1; |
| + break; |
| + } |
| + |
| /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't |
| * match the SoC datasheet, this should be investigated. Let platform |
| * data override the sampling rate for now. |