| From d0d6f55d7423bc18a7bf61c23a7cf65153e25f12 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Mon, 3 Apr 2017 11:45:42 +0200 |
| Subject: [PATCH 274/286] ARM: dts: r8a7791: Correct parent of SSI[0-9] clocks |
| |
| The SSI-ALL gate clock is located in between the P clock and the |
| individual SSI[0-9] clocks, hence the former should be listed as their |
| parent. |
| |
| Fixes: ee9141522dcf13f8 ("ARM: shmobile: r8a7791: add MSTP10 support on DTSI") |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 16fe68dcab5702a024d85229ff7e98979cb701a5) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm/boot/dts/r8a7791.dtsi | 7 +++++-- |
| 1 file changed, 5 insertions(+), 2 deletions(-) |
| |
| --- a/arch/arm/boot/dts/r8a7791.dtsi |
| +++ b/arch/arm/boot/dts/r8a7791.dtsi |
| @@ -1447,8 +1447,11 @@ |
| compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>; |
| clocks = <&p_clk>, |
| - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| - <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, <&p_clk>, |
| + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| + <&mstp10_clks R8A7791_CLK_SSI_ALL>, <&mstp10_clks R8A7791_CLK_SSI_ALL>, |
| <&p_clk>, |
| <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
| <&mstp10_clks R8A7791_CLK_SCU_ALL>, <&mstp10_clks R8A7791_CLK_SCU_ALL>, |
