| From 39ef217c9d3c09d6ec57e1a498a25529ebff823e Mon Sep 17 00:00:00 2001 |
| From: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| Date: Wed, 27 Sep 2017 10:57:04 +0100 |
| Subject: [PATCH 0348/1795] ARM: dts: r8a7743: Add MSIOF[012] support |
| |
| Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. |
| Also, define aliases for spi[123]. |
| |
| Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> |
| Signed-off-by: Chris Paterson <chris.paterson2@renesas.com> |
| Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 7031a219f649d12acda8a70a4b6b816ee123c8e2) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| arch/arm/boot/dts/r8a7743.dtsi | 51 ++++++++++++++++++++++++++++++++++ |
| 1 file changed, 51 insertions(+) |
| |
| diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi |
| index 454f98060d6f..d541fd9ffafb 100644 |
| --- a/arch/arm/boot/dts/r8a7743.dtsi |
| +++ b/arch/arm/boot/dts/r8a7743.dtsi |
| @@ -29,6 +29,9 @@ |
| i2c7 = &iic1; |
| i2c8 = &iic3; |
| spi0 = &qspi; |
| + spi1 = &msiof0; |
| + spi2 = &msiof1; |
| + spi3 = &msiof2; |
| }; |
| |
| cpus { |
| @@ -852,6 +855,54 @@ |
| status = "disabled"; |
| }; |
| |
| + msiof0: spi@e6e20000 { |
| + compatible = "renesas,msiof-r8a7743", |
| + "renesas,rcar-gen2-msiof"; |
| + reg = <0 0xe6e20000 0 0x0064>; |
| + interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 000>; |
| + dmas = <&dmac0 0x51>, <&dmac0 0x52>, |
| + <&dmac1 0x51>, <&dmac1 0x52>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + resets = <&cpg 000>; |
| + status = "disabled"; |
| + }; |
| + |
| + msiof1: spi@e6e10000 { |
| + compatible = "renesas,msiof-r8a7743", |
| + "renesas,rcar-gen2-msiof"; |
| + reg = <0 0xe6e10000 0 0x0064>; |
| + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 208>; |
| + dmas = <&dmac0 0x55>, <&dmac0 0x56>, |
| + <&dmac1 0x55>, <&dmac1 0x56>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + resets = <&cpg 208>; |
| + status = "disabled"; |
| + }; |
| + |
| + msiof2: spi@e6e00000 { |
| + compatible = "renesas,msiof-r8a7743", |
| + "renesas,rcar-gen2-msiof"; |
| + reg = <0 0xe6e00000 0 0x0064>; |
| + interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
| + clocks = <&cpg CPG_MOD 205>; |
| + dmas = <&dmac0 0x41>, <&dmac0 0x42>, |
| + <&dmac1 0x41>, <&dmac1 0x42>; |
| + dma-names = "tx", "rx", "tx", "rx"; |
| + power-domains = <&sysc R8A7743_PD_ALWAYS_ON>; |
| + #address-cells = <1>; |
| + #size-cells = <0>; |
| + resets = <&cpg 205>; |
| + status = "disabled"; |
| + }; |
| + |
| sdhi0: sd@ee100000 { |
| compatible = "renesas,sdhi-r8a7743"; |
| reg = <0 0xee100000 0 0x328>; |
| -- |
| 2.19.0 |
| |
