| From 6a57903ef929d211486385240e3dbd8169541d37 Mon Sep 17 00:00:00 2001 |
| From: Geert Uytterhoeven <geert+renesas@glider.be> |
| Date: Thu, 12 Oct 2017 11:35:15 +0200 |
| Subject: [PATCH 0387/1795] ARM: dts: r8a7794: Add missing clock for secondary |
| CA7 CPU core |
| |
| Currently only the primary CPU in the CA7 cluster has a clocks property, |
| while the secondary CPU core is driven by the same clock. |
| Add the missing clocks property to fix this. |
| |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit 5614e69269232da1f378e5be92714b96cdb090ef) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| --- |
| arch/arm/boot/dts/r8a7794.dtsi | 1 + |
| 1 file changed, 1 insertion(+) |
| |
| diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi |
| index 7720a6ca8702..905e50c9b524 100644 |
| --- a/arch/arm/boot/dts/r8a7794.dtsi |
| +++ b/arch/arm/boot/dts/r8a7794.dtsi |
| @@ -53,6 +53,7 @@ |
| compatible = "arm,cortex-a7"; |
| reg = <1>; |
| clock-frequency = <1000000000>; |
| + clocks = <&cpg CPG_CORE R8A7794_CLK_Z2>; |
| power-domains = <&sysc R8A7794_PD_CA7_CPU1>; |
| next-level-cache = <&L2_CA7>; |
| }; |
| -- |
| 2.19.0 |
| |
