| From 005ffe875025652452adfbf2fe27497950d9e994 Mon Sep 17 00:00:00 2001 |
| From: =?UTF-8?q?Niklas=20S=C3=B6derlund?= |
| <niklas.soderlund+renesas@ragnatech.se> |
| Date: Fri, 11 Nov 2016 21:40:03 +0100 |
| Subject: [PATCH 097/299] pinctrl: sh-pfc: r8a7796: Add DU support |
| MIME-Version: 1.0 |
| Content-Type: text/plain; charset=UTF-8 |
| Content-Transfer-Encoding: 8bit |
| |
| Only the DU parallel RGB output signals are included, HDMI and TCON pins |
| will be added in separate groups. Based on a similar patch from Laurent |
| Pinchart for the r8a7795 PFC driver. |
| |
| Signed-off-by: Niklas Sรถderlund <niklas.soderlund+renesas@ragnatech.se> |
| Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> |
| Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> |
| (cherry picked from commit cccc618a0b74867efb2211be6573ecf729a56ed0) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| drivers/pinctrl/sh-pfc/pfc-r8a7796.c | 101 +++++++++++++++++++++++++++++++++++ |
| 1 file changed, 101 insertions(+) |
| |
| --- a/drivers/pinctrl/sh-pfc/pfc-r8a7796.c |
| +++ b/drivers/pinctrl/sh-pfc/pfc-r8a7796.c |
| @@ -1770,6 +1770,87 @@ static const unsigned int drif3_data1_b_ |
| RIF3_D1_B_MARK, |
| }; |
| |
| +/* - DU --------------------------------------------------------------------- */ |
| +static const unsigned int du_rgb666_pins[] = { |
| + /* R[7:2], G[7:2], B[7:2] */ |
| + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), |
| + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), |
| + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
| + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), |
| + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), |
| +}; |
| +static const unsigned int du_rgb666_mux[] = { |
| + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, |
| + DU_DR3_MARK, DU_DR2_MARK, |
| + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, |
| + DU_DG3_MARK, DU_DG2_MARK, |
| + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, |
| + DU_DB3_MARK, DU_DB2_MARK, |
| +}; |
| +static const unsigned int du_rgb888_pins[] = { |
| + /* R[7:0], G[7:0], B[7:0] */ |
| + RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 13), |
| + RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10), |
| + RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 8), |
| + RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), |
| + RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18), |
| + RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), |
| + RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 5), |
| + RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2), |
| + RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 0), |
| +}; |
| +static const unsigned int du_rgb888_mux[] = { |
| + DU_DR7_MARK, DU_DR6_MARK, DU_DR5_MARK, DU_DR4_MARK, |
| + DU_DR3_MARK, DU_DR2_MARK, DU_DR1_MARK, DU_DR0_MARK, |
| + DU_DG7_MARK, DU_DG6_MARK, DU_DG5_MARK, DU_DG4_MARK, |
| + DU_DG3_MARK, DU_DG2_MARK, DU_DG1_MARK, DU_DG0_MARK, |
| + DU_DB7_MARK, DU_DB6_MARK, DU_DB5_MARK, DU_DB4_MARK, |
| + DU_DB3_MARK, DU_DB2_MARK, DU_DB1_MARK, DU_DB0_MARK, |
| +}; |
| +static const unsigned int du_clk_out_0_pins[] = { |
| + /* CLKOUT */ |
| + RCAR_GP_PIN(1, 27), |
| +}; |
| +static const unsigned int du_clk_out_0_mux[] = { |
| + DU_DOTCLKOUT0_MARK |
| +}; |
| +static const unsigned int du_clk_out_1_pins[] = { |
| + /* CLKOUT */ |
| + RCAR_GP_PIN(2, 3), |
| +}; |
| +static const unsigned int du_clk_out_1_mux[] = { |
| + DU_DOTCLKOUT1_MARK |
| +}; |
| +static const unsigned int du_sync_pins[] = { |
| + /* EXVSYNC/VSYNC, EXHSYNC/HSYNC */ |
| + RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4), |
| +}; |
| +static const unsigned int du_sync_mux[] = { |
| + DU_EXVSYNC_DU_VSYNC_MARK, DU_EXHSYNC_DU_HSYNC_MARK |
| +}; |
| +static const unsigned int du_oddf_pins[] = { |
| + /* EXDISP/EXODDF/EXCDE */ |
| + RCAR_GP_PIN(2, 2), |
| +}; |
| +static const unsigned int du_oddf_mux[] = { |
| + DU_EXODDF_DU_ODDF_DISP_CDE_MARK, |
| +}; |
| +static const unsigned int du_cde_pins[] = { |
| + /* CDE */ |
| + RCAR_GP_PIN(2, 0), |
| +}; |
| +static const unsigned int du_cde_mux[] = { |
| + DU_CDE_MARK, |
| +}; |
| +static const unsigned int du_disp_pins[] = { |
| + /* DISP */ |
| + RCAR_GP_PIN(2, 1), |
| +}; |
| +static const unsigned int du_disp_mux[] = { |
| + DU_DISP_MARK, |
| +}; |
| + |
| /* - I2C -------------------------------------------------------------------- */ |
| static const unsigned int i2c1_a_pins[] = { |
| /* SDA, SCL */ |
| @@ -2282,6 +2363,14 @@ static const struct sh_pfc_pin_group pin |
| SH_PFC_PIN_GROUP(drif3_ctrl_b), |
| SH_PFC_PIN_GROUP(drif3_data0_b), |
| SH_PFC_PIN_GROUP(drif3_data1_b), |
| + SH_PFC_PIN_GROUP(du_rgb666), |
| + SH_PFC_PIN_GROUP(du_rgb888), |
| + SH_PFC_PIN_GROUP(du_clk_out_0), |
| + SH_PFC_PIN_GROUP(du_clk_out_1), |
| + SH_PFC_PIN_GROUP(du_sync), |
| + SH_PFC_PIN_GROUP(du_oddf), |
| + SH_PFC_PIN_GROUP(du_cde), |
| + SH_PFC_PIN_GROUP(du_disp), |
| SH_PFC_PIN_GROUP(i2c1_a), |
| SH_PFC_PIN_GROUP(i2c1_b), |
| SH_PFC_PIN_GROUP(i2c2_a), |
| @@ -2400,6 +2489,17 @@ static const char * const drif3_groups[] |
| "drif3_data1_b", |
| }; |
| |
| +static const char * const du_groups[] = { |
| + "du_rgb666", |
| + "du_rgb888", |
| + "du_clk_out_0", |
| + "du_clk_out_1", |
| + "du_sync", |
| + "du_oddf", |
| + "du_cde", |
| + "du_disp", |
| +}; |
| + |
| static const char * const i2c1_groups[] = { |
| "i2c1_a", |
| "i2c1_b", |
| @@ -2510,6 +2610,7 @@ static const struct sh_pfc_function pinm |
| SH_PFC_FUNCTION(drif1), |
| SH_PFC_FUNCTION(drif2), |
| SH_PFC_FUNCTION(drif3), |
| + SH_PFC_FUNCTION(du), |
| SH_PFC_FUNCTION(i2c1), |
| SH_PFC_FUNCTION(i2c2), |
| SH_PFC_FUNCTION(i2c6), |