| From 4f20215fc1aac53917a0195c6b59ba69e22790cc Mon Sep 17 00:00:00 2001 |
| From: Vladimir Barinov <vladimir.barinov@cogentembedded.com> |
| Date: Thu, 3 Nov 2016 21:07:20 +0300 |
| Subject: [PATCH 132/299] arm64: dts: m3ulcb: enable SCIF clk and pins |
| |
| This enables the external crystal for the SCIF_CLK and its pinctrl, to |
| be used by the Baud Rate Generator for External Clock (BRG) on (H)SCIF. |
| |
| Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| (cherry picked from commit d92ce1a57480e17aff1fb8693cc919bb46a6e0fd) |
| Signed-off-by: Simon Horman <horms+renesas@verge.net.au> |
| --- |
| arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts | 13 +++++++++++++ |
| 1 file changed, 13 insertions(+) |
| |
| --- a/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts |
| +++ b/arch/arm64/boot/dts/renesas/r8a7796-m3ulcb.dts |
| @@ -37,10 +37,18 @@ |
| }; |
| |
| &pfc { |
| + pinctrl-0 = <&scif_clk_pins>; |
| + pinctrl-names = "default"; |
| + |
| scif2_pins: scif2 { |
| groups = "scif2_data_a"; |
| function = "scif2"; |
| }; |
| + |
| + scif_clk_pins: scif_clk { |
| + groups = "scif_clk_a"; |
| + function = "scif_clk"; |
| + }; |
| }; |
| |
| &scif2 { |
| @@ -49,3 +57,8 @@ |
| |
| status = "okay"; |
| }; |
| + |
| +&scif_clk { |
| + clock-frequency = <14745600>; |
| + status = "okay"; |
| +}; |